riscv/qemu: QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org - qemu

QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org

Branch: master

History

Jamin Lin a39d7662cd hw/i3c/mock-i3c-target: Simplify GETMRL byte extraction logic The GETMRL handling logic extracted MSB/LSB bytes from s->cfg.buf_size using a mask-and-shift expression: (buf_size & (0xff00 >> (offset * 8))) >> (8 - (offset * 8)) While functionally correct, the expression is difficult to read and obscures the intent, which is simply to return a 16-bit value in MSB-first order. Replace the mask/shift formula with explicit MSB/LSB extraction: offset == 0 -> buf_size >> 8 offset == 1 -> buf_size & 0xff This makes the code clearer and easier to review without altering behavior or data ordering. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260303013322.1297499-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>		4 weeks ago
..
Kconfig	hw/i3c: Add Mock target	4 weeks ago
aspeed_i3c.c	hw/i3c/aspeed: Add I3C bus get function	4 weeks ago
core.c	hw/i3c/core: Initialize num_sent in i3c_send_byte()	4 weeks ago
dw-i3c.c	hw/i3c/dw-i3c: Use ROUND_UP() for RX buffer allocation alignment	4 weeks ago
meson.build	hw/i3c: Add Mock target	4 weeks ago
mock-i3c-target.c	hw/i3c/mock-i3c-target: Simplify GETMRL byte extraction logic	4 weeks ago
trace-events	hw/i3c: Add Mock target	4 weeks ago
trace.h	hw/misc/aspeed_i3c: Move to i3c directory	4 weeks ago