riscv/qemu - qemu - Gitea: Git with a cup of tea

Author	SHA1	Message	Date
Keith Packard	a10b9d93ec	riscv: Add semihosting support Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>	6 years ago
Bin Meng	138ca49a82	target/riscv: Remove built-in GDB XML files for CSRs Now that we have switched to generate the RISC-V CSR XML dynamically, remove the built-in hardcoded XML files. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	6 years ago
Paolo Bonzini	a9a7490786	default-configs: use TARGET_ARCH key Replace the individual TARGET_*=y lines with TARGET_ARCH, similar to how TARGET_BASE_ARCH is handled already. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	6 years ago
Paolo Bonzini	fdb75aeff7	configure: remove target configuration The config-target.mak files are small constant, we can therefore just write them down explicitly. This removes a pretty large part of the configure script, including the whole logic to detect which accelerators are supported by each target. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	6 years ago