riscv/qemu - qemu - Gitea: Git with a cup of tea

Author	SHA1	Message	Date
Stefan Weil	b980c1aec6	Fix some typos in documentation (found by codespell) Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20211117210702.1393570-1-sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [thuth: "what's" --> "what is" as suggested by philmd] Signed-off-by: Thomas Huth <thuth@redhat.com>	4 years ago
Paolo Bonzini	c2c7f3351a	docs/system: move x86 CPU configuration to a separate document Currently, cpu-models-x86.rst.inc is included in target-i386.rst directly. To make the toctree more homogeneous when adding more documentation, include it through a first-class .rst file. Together with the previous changes to the man page skeletons, this also frees "===" for the headings, so that cpu-models-x86.rst.inc need not assume anything about the headings used by target-i386.rst. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	5 years ago
Daniel P. Berrangé	2edb76ea57	docs: fix typo s/Intel/AMD/ in CPU model notes Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>	5 years ago
Daniel P. Berrangé	38dec0ef76	docs: add a table showing x86-64 ABI compatibility levels It is useful to know which CPUs satisfy each x86-64 ABI compatibility level, when dealing with guest OS that require something newer than the baseline ABI. These ABI levels are defined in: https://gitlab.com/x86-psABIs/x86-64-ABI/ and supported by GCC, Clang, glibc and more. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210607135843.196595-2-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>	5 years ago
Daniel P. Berrangé	1bd39ea911	docs: update to show preferred boolean syntax for -cpu The preferred syntax is to use "foo=on\|off", rather than a bare "+foo" or "-foo" Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210216191027.595031-10-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	5 years ago
Kashyap Chamarthy	3b2c52c017	qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl - Add the '-noTSX' variants for CascadeLake and SkyLake. - Document the three MSR bits: 'mds-no', 'taa-no', and 'tsx-ctrl' Two confusing things about 'mds-no' (and the first point applies to the other two MSRs too): (1) The 'mds-no' bit will _not_ show up in the guest's /proc/cpuinfo. Rather it is used to fill in the guest's sysfs: /sys/devices/system/cpu/vulnerabilities/mds:Not affected Paolo confirmed on IRC as such. (2) There are _three_ variants[+] of CascadeLake CPUs, with different stepping levels: 5, 6, and 7. To quote wikichip.org[]: "note that while steppings 6 & 7 are fully mitigated, earlier stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM" The above is also indicated in the Intel's document[+], as indicated by "No" under the three columns of MFBDS, MSBDS, and MLPDS. I've expressed this in the docs without belabouring the details. [+] https://software.intel.com/security-software-guidance/insights/processors-affected-microarchitectural-data-sampling [] https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake#Key_changes_from_Skylake Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> Message-Id: <20200225165618.6571-3-kchamart@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	6 years ago
Kashyap Chamarthy	1bf84a1e2e	docs/system: Convert qemu-cpu-models.texi to rST This doc was originally written by Daniel P. Berrangé <berrange@redhat.com>, introduced via commit[1]: `2544e9e4aa` (docs: add guidance on configuring CPU models for x86, 2018-06-27). In this patch: - 1-1 conversion of Texinfo to rST, besides a couple of minor tweaks that are too trivial to mention. (Thanks to Stephen Finucane on IRC for the suggestion to use rST "definition lists" instead of bullets in some places.) Further modifications will be done via a separate patch. - rST and related infra changes: manual page generation, Makefile fixes, clean up references to qemu-cpu-models.texi, update year in the copyright notice, etc. [1] https://git.qemu.org/?p=qemu.git;a=commit;h=2544e9e4aa As part of the conversion, we use a more generic 'author' attribution for the manpage than we previously had, as agreed with the original author Dan Berrange. Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200228153619.9906-16-peter.maydell@linaro.org Message-id: 20200226113034.6741-15-pbonzini@redhat.com [Move macros to defs.rst.inc, split in x86 and MIPS parts, make qemu-cpu-models.rst a standalone document. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PMM: Move defs.rst.inc setup to its own commit; fix minor issues with MAINTAINERS file updates; drop copyright date change; keep capitalization of "QEMU Project developers" consistent with other uses; minor Makefile fixups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	6 years ago