riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Jamin Lin	7c79c954aa	tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE tests Update AST2700 HACE qtests to use the "ast2700-evb" machine alias instead of a specific silicon revision. The AST2700 A1 and A2 revisions are compatible for the HACE model, so the tests do not depend on a particular EVB revision. Using the "ast2700-evb" alias ensures the tests always run the latest supported AST2700 silicon revision. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	bed8917d98	hw/arm/aspeed_ast27x0_evb: Move ast2700-evb alias to AST2700 A2 EVB Make AST2700 A2 EVB the default ast2700-evb machine. The "ast2700-evb" machine alias is moved from the AST2700 A1 EVB to the AST2700 A2 EVB, making A2 the default evaluation board for AST2700. This ensures that users selecting "ast2700-evb" will run on the latest AST2700 silicon revision. The AST2700 A1 EVB machine remains available explicitly as "ast2700a1-evb". Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	ec270a67d3	hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine Add a new AST2700 A2 EVB machine to model the newer A2 silicon. The ast2700a2-evb machine is largely identical to ast2700a1-evb. The only difference is the default DRAM size, which is increased to 2 GB. This change adds a dedicated ast2700a2-evb machine by copying the existing ast2700a1-evb configuration and updating the DRAM size accordingly. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	ecfa7ae956	hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support AST2700 A2 is functionally identical to AST2700 A1. There are no changes to the IRQ layout, memory map, or peripheral configuration. The only difference is the silicon revision. This commit introduces a dedicated AST2700 A2 SoC type by reusing the existing AST2700 A1 implementation and setting the A2 silicon revision accordingly. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Tested-by: Nabih Estefan <nabihestefan@google.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	6c5e1c5c73	hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions Add silicon revision definitions for AST2700 A2, and include them in the list of supported Aspeed silicon revisions. This allows newer AST27x0 A2 silicon to be correctly identified via the SCU silicon revision register. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	e202a765c6	hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions Several legacy Aspeed SoC silicon revision definitions are no longer used by any machine models or runtime logic. Remove unused silicon revision macros and corresponding entries from the silicon revision table to reduce dead code and improve maintainability. No functional change intended. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Kane Chen	2451fca14a	tests/functional/arm/aspeed_ast2600: Enhance OTP test with functional validation Improve the OTP test script by adding functional verification of OTP strap registers. The test now validates that OTP modifications made in U-Boot persist through the Linux boot process and survive a subsequent reboot. Key changes: - Added interactive console commands for U-Boot and Linux. - Implemented verification for OTP register 0x30 across reboots. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211052326.430475-2-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	93a5fed3d9	hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0 According to the AST2700 A1 datasheet, the register space for each I2C device instance has been expanded from 0x80 bytes to 0xA0 bytes. Update the AST2700 I2C controller configuration to reflect the new register layout by increasing the per-device register size to 0xA0 and adjusting the register gap size accordingly. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Fixes: `4f53de2f10` ("hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC") Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260210024331.3984696-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Jamin Lin	c2c5beec42	hw/i2c/aspeed_i2c: Fix out-of-bounds read in I2C MMIO handlers The ASPEED I2C controller exposes a per-bus MMIO window of 0x80 bytes on AST2600/AST1030/AST2700, but the backing regs[] array was sized for only 28 dwords (0x70 bytes). This allows guest reads in the range [0x70..0x7f] to index past the end of regs[]. Fix this by: - Sizing ASPEED_I2C_NEW_NUM_REG to match the 0x80-byte window (0x80 >> 2 = 32 dwords). - Avoiding an unconditional pre-read from regs[] in the legacy/new read handlers. Initialize the return value to -1 and only read regs[] for offsets that are explicitly handled/valid, leaving invalid offsets to return -1 with a guest error log. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3290 Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260210024331.3984696-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Cédric Le Goater	308eef22d9	tests/functional: Add SDK tests with Linux 5.15 Add functional tests for AST2500 and AST2600 machines using the OpenBMC SDK v11.00 with Linux kernel 5.15. These tests complement the existing SDK tests and verify that QEMU correctly boots older kernel versions on these platforms. Link: https://lore.kernel.org/qemu-devel/20260209065044.239378-3-clg@redhat.com Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Cédric Le Goater	6b1a1fc1d1	tests/functional: Split Aspeed ARM tests into separate files Reorganize the monolithic Aspeed functional test files into separate files based on firmware type (Buildroot vs SDK) and specific test scenarios. This allows the test suite to run tests in parallel more effectively and makes it easier to identify and run specific test scenarios independently. Link: https://lore.kernel.org/qemu-devel/20260209065044.239378-2-clg@redhat.com Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Peter Maydell	039fae56bb	* Updates to MAINTAINERS file * Fix CI (broken pkg_resources in python, revert RCU change to fix alpha test) * Fix endianness issue in PCI code on s390x * Implement DIVIDE TO INTEGER instruction for s390x TCG emulation * Bitesized documentation updates (run-tcg-tests target and fd-bootchk property) -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmmNu6ERHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbU+9Q//WVNddXAhre9g40SMvUULwFsoXIHtXASq 0WcL+GiZEenuON8YYvKVEUobNPEHtwm6GRKUwAeqCXQPXGEHamY3htMK5/HY9h2D dFG6XJr/0JozAFp381lhUt/Gu1b56uljqF3CzSf/AvidmFoxOH2Pi+IHcyzZZTkI DvsXbbIHim6dsMzxLpGBSDGj4+Jdz9t9HJF59Q7XO41EMgFKJzqBUDuVzL1ZZzg8 rcV1yfrEJ1RmdK9+ZCweLTn1SnCjn1yywigzQUvMlguw2Tl9IWPFNmuhfs9u8KOv LEqteHnxJyslFZpBXTN5vxwM9FghWnACvGAKDln38N3kI56PbKRe6De6dZYh9Ihb ea3Uiaji2z8TI1xRHnWqGuT9gz9aRo1bMM6pCaX5rfxZ05xHmoP0qA1Ul20pr4I0 +YPyhKG45JmrGkV+HKnQtq1k+8Xnl8Xon9gIgKM/f2r9fQ4wXjU0lIGWCxhSl9UV MntuoZtYeDs4S5WFnW2bhVYDIKsf+mbfoSBUYmAYAVqjbuqSX5tAsGPfYJ2l9+sR rwG0iuJcW/kYpkyNFV9xKKuhX7qh17N4TUgU7KkvIoVkRP++2quzwXuHOniDOiJ5 Gl68R96GRSleWUusL1tKexVmOuQcZGST/SzGLol/L1Ob3iXawjfy0Y2C+rYsfOO7 5XX4X7alVew= =oaJh -----END PGP SIGNATURE----- Merge tag 'pull-request-2026-02-12v2' of https://gitlab.com/thuth/qemu into staging * Updates to MAINTAINERS file * Fix CI (broken pkg_resources in python, revert RCU change to fix alpha test) * Fix endianness issue in PCI code on s390x * Implement DIVIDE TO INTEGER instruction for s390x TCG emulation * Bitesized documentation updates (run-tcg-tests target and fd-bootchk property) # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCgAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmmNu6ERHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbU+9Q//WVNddXAhre9g40SMvUULwFsoXIHtXASq # 0WcL+GiZEenuON8YYvKVEUobNPEHtwm6GRKUwAeqCXQPXGEHamY3htMK5/HY9h2D # dFG6XJr/0JozAFp381lhUt/Gu1b56uljqF3CzSf/AvidmFoxOH2Pi+IHcyzZZTkI # DvsXbbIHim6dsMzxLpGBSDGj4+Jdz9t9HJF59Q7XO41EMgFKJzqBUDuVzL1ZZzg8 # rcV1yfrEJ1RmdK9+ZCweLTn1SnCjn1yywigzQUvMlguw2Tl9IWPFNmuhfs9u8KOv # LEqteHnxJyslFZpBXTN5vxwM9FghWnACvGAKDln38N3kI56PbKRe6De6dZYh9Ihb # ea3Uiaji2z8TI1xRHnWqGuT9gz9aRo1bMM6pCaX5rfxZ05xHmoP0qA1Ul20pr4I0 # +YPyhKG45JmrGkV+HKnQtq1k+8Xnl8Xon9gIgKM/f2r9fQ4wXjU0lIGWCxhSl9UV # MntuoZtYeDs4S5WFnW2bhVYDIKsf+mbfoSBUYmAYAVqjbuqSX5tAsGPfYJ2l9+sR # rwG0iuJcW/kYpkyNFV9xKKuhX7qh17N4TUgU7KkvIoVkRP++2quzwXuHOniDOiJ5 # Gl68R96GRSleWUusL1tKexVmOuQcZGST/SzGLol/L1Ob3iXawjfy0Y2C+rYsfOO7 # 5XX4X7alVew= # =oaJh # -----END PGP SIGNATURE----- # gpg: Signature made Thu Feb 12 11:38:09 2026 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [undefined] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2026-02-12v2' of https://gitlab.com/thuth/qemu: python: drop uses of pkg_resources hw/i386/pc.c: add description for fd-bootchk option tests/Makefile.include: add run-tcg-tests-TARGET to check-help tests/tcg/s390x: Test DIVIDE TO INTEGER target/s390x: Implement DIVIDE TO INTEGER fpu: Restrict parts_round_to_int_normal to target precision target/s390x: Extract s390_get_bfp_rounding_mode() target/s390x: Dump Floating-Point-Control Register Revert "rcu: Unify force quiescent state" s390x/pci: Fix endianness for zPCI BAR values. virtio-ccw: virtio_ccw_set_guest_notifier(): fix failure path tests/.../reverse_debugging: Remove unsatisfiable condition MAINTAINERS: Replace backup for s390 PCI MAINTAINERS: Switch to my NVIDIA email Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
John Snow	e44a26ba94	python: drop uses of pkg_resources pkg_resources has been fully dropped from modern pip/setuptools distributions and we should phase out its use. This patch is enough to, by itself, repair most GitLab CI tests upstream; with the exception of tox tests which are still making use of avocado - which will be dropped in a separate series to restore functionality there. Signed-off-by: John Snow <jsnow@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20260211195804.135144-3-jsnow@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Choon Keong	e8cf82eb72	hw/i386/pc.c: add description for fd-bootchk option The 'fd-bootchk' option for pc and q35 machines currently lacks of description in the help output. This makes it difficult for users to understand the purpose of the command. This commit solve this issue by adding description using object_class_property_set_description() in hw/i386/pc.c, adding the the description message for the option 'fd-bootchk'. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Thomas Huth <thuth@redhat.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3193 Signed-off-by: Choon Keong <ckeong.teo17@gmail.com> Message-ID: <20260211162909.6550-1-ckeong.teo17@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Choon Keong	76959197dd	tests/Makefile.include: add run-tcg-tests-TARGET to check-help User can execute TCG tests for a specific TARGET using the command: $ make run-tcg-tests-TARGET-softmmu However, this command is not showing in 'make check-help' documentation, making it hard for new contributors to discover. This commit help to resolve this by adding the description for the command, to the "check-tcg" section, as suggested by Thomas, in tests/Makefile.include. Additionally, reformat the alignment to accommodate the length of the new command, ensuring the consistency of the output. Suggested-by: Thomas Huth <thuth@redhat.com> Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/228 Signed-off-by: ck <ckeong.teo17@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20260206170059.4913-1-ckeong.teo17@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Ilya Leoshkevich	a6364b292f	tests/tcg/s390x: Test DIVIDE TO INTEGER Add a test to prevent regressions. Data is generated using a libFuzzer-based fuzzer and hopefully covers all the important corner cases. Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20260210214044.1174699-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Ilya Leoshkevich	8eb8c1bc59	target/s390x: Implement DIVIDE TO INTEGER DIVIDE TO INTEGER computes floating point remainder and is used by LuaJIT, so add it to QEMU. Put the main logic into fpu/, because it is way more convenient to operate on FloatParts than to convert floats back-and-forth. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20260210214044.1174699-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Ilya Leoshkevich	b4a85d8fe7	fpu: Restrict parts_round_to_int_normal to target precision Currently parts_round_to_int_normal() assumes that its input has just been unpacked and therefore doesn't expect non-zero fraction bits past target precision. The upcoming DIVIDE TO INTEGER use cases needs it to support calculations on intermediate values that utilize all fraction bits, while at the same time restricting the result's precision to frac_size. Delete the "All integral" check, because even though really large values are always integer, their low fraction bits still need to be truncated. For the same reason, make sure rnd_mask covers at least fraction bits past target precision. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20260210214044.1174699-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Ilya Leoshkevich	f5682b9dee	target/s390x: Extract s390_get_bfp_rounding_mode() For DIVIDE TO INTEGER it will be helpful to pass final-quotient rounding mode around explicitly rather than setting it in fpu_status implicitly. To facilitate this, extract a function for converting the mask to the rounding mode. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20260210214044.1174699-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Ilya Leoshkevich	5b251330e4	target/s390x: Dump Floating-Point-Control Register Knowing the value of this register is very useful for debugging floating-point code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20260210214044.1174699-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Thomas Huth	ddb4d9d174	Revert "rcu: Unify force quiescent state" This reverts commit `55d98e3ede`. The commit introduced a regression in the replay functional test on alpha (tests/functional/alpha/test_replay.py), that causes CI failures regularly. Thus revert this change until someone has figured out what is going wrong here. Buglink: https://gitlab.com/qemu-project/qemu/-/issues/3197 Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20260209120336.41454-1-thuth@redhat.com>	2 months ago
Peter Maydell	44dba5a0c8	Merge tpm 2026/02/10 v1 -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEuBi5yt+QicLVzsZrda1lgCoLQhEFAmmLUPwACgkQda1lgCoL QhH6Dwf/b2CqCmWwt4otJIYteKdhOGOuurL9jo2YWthJKj6hr3SuefRnflSweQTD 2Mij2tdfu089gWC7qmvLNeqCBKT0L9q80sV6YPD4RJBrybcVBQRYeO7aDM2HhYjq Q5AjHnToIdKgwr8rniccH0dOnGyCTMbe3jmamT8hr32Cev8Lu2++Hkxu0FEj/6Ur +yGIu0yNn5Es+IOX1Kd01n3LZb0TLpDRGglWScWZxh4jc99CHhzRNFn4IQfSqbAE A5rqN5bWY0p855h/+XNNdOiocx/hlrzyl47FWatzFJTaxvGka3N4WYVtrd6U0g1w ByP8ajaONqiQgo1tsV+52yWz7jj+vg== =quEE -----END PGP SIGNATURE----- Merge tag 'pull-tpm-2026-02-10-1' of https://github.com/stefanberger/qemu-tpm into staging Merge tpm 2026/02/10 v1 # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEuBi5yt+QicLVzsZrda1lgCoLQhEFAmmLUPwACgkQda1lgCoL # QhH6Dwf/b2CqCmWwt4otJIYteKdhOGOuurL9jo2YWthJKj6hr3SuefRnflSweQTD # 2Mij2tdfu089gWC7qmvLNeqCBKT0L9q80sV6YPD4RJBrybcVBQRYeO7aDM2HhYjq # Q5AjHnToIdKgwr8rniccH0dOnGyCTMbe3jmamT8hr32Cev8Lu2++Hkxu0FEj/6Ur # +yGIu0yNn5Es+IOX1Kd01n3LZb0TLpDRGglWScWZxh4jc99CHhzRNFn4IQfSqbAE # A5rqN5bWY0p855h/+XNNdOiocx/hlrzyl47FWatzFJTaxvGka3N4WYVtrd6U0g1w # ByP8ajaONqiQgo1tsV+52yWz7jj+vg== # =quEE # -----END PGP SIGNATURE----- # gpg: Signature made Tue Feb 10 15:38:36 2026 GMT # gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * tag 'pull-tpm-2026-02-10-1' of https://github.com/stefanberger/qemu-tpm: tpm_emulator: tpm_emulator_set_state_blobs(): move to boolean return tpm_emulator: drop direct use of errno variable tpm_emulator: print error on error-ignore path Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Peter Maydell	2f0870fd6a	target-arm queue: * Add whpx accelerator support for the virt board * Implement FEAT_E2H0 * Implement WFE, SEV and SEVONPEND for Cortex-M -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmmLN9kZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jlTD/9RlOP4M+qJQ67v5/vzJkOC tml5W+iUINIuPrJyZn3+AtLZoyS5GHH+lkBLwuRkdIpx9LjEApfr/4/T45quRqj1 T0ziJXPQpSC6+3eVyJcfAg4ROtQSZq1+JUGQdCGocxyrwHxTKKI3LHyQezLhe56G +U/z1cI+DZPuYIdzz3LneIrNopsxEdmlWLlcR3e9HaSp15rcYrYwjOn08eTTk8HV e5pCu/1kq8LHlf8lwqwDwHL9odfW9W5570hPcuFZcjy1cUzzOJty3AW644Jlj4aw MEnyvvqCXKPSgOQ9N+W9TT2veU60h7aWov3N5S+HmYix3ZsFgbI8w/9SdDjeJlkH RFb/apdK8xcEktbsGaToEZOp1Wz1vxOMoGVCGayfYZ4byBhTAjOp5YLH2+26JDze I7o4q2PYENNP4r0ayOIbPcayBzlkp53VROZKILyQfQfwfChnoaFlkBeqVvF/PUxt CNsei6qDY2jsArhUieZ8CkHbOSlCeg22+7HjNTjp6b1h4lr3p4/tnFobJAYJrtRB 5v6EGaWnejEvsbcKV0aZhtVITygcny7tENZUkKlKoPeNr4k0R6dyFNKDcShLhv75 42ms95D7T/j4weJt6G3E9t1kqFCMl3KM8qwMT7nDJ1xiSVOw329sMtCcazAssDQ/ 5ecCq9cGSaGUROwlnoUDpQ== =pzkY -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20260210' of https://gitlab.com/pm215/qemu into staging target-arm queue: * Add whpx accelerator support for the virt board * Implement FEAT_E2H0 * Implement WFE, SEV and SEVONPEND for Cortex-M # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmmLN9kZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jlTD/9RlOP4M+qJQ67v5/vzJkOC # tml5W+iUINIuPrJyZn3+AtLZoyS5GHH+lkBLwuRkdIpx9LjEApfr/4/T45quRqj1 # T0ziJXPQpSC6+3eVyJcfAg4ROtQSZq1+JUGQdCGocxyrwHxTKKI3LHyQezLhe56G # +U/z1cI+DZPuYIdzz3LneIrNopsxEdmlWLlcR3e9HaSp15rcYrYwjOn08eTTk8HV # e5pCu/1kq8LHlf8lwqwDwHL9odfW9W5570hPcuFZcjy1cUzzOJty3AW644Jlj4aw # MEnyvvqCXKPSgOQ9N+W9TT2veU60h7aWov3N5S+HmYix3ZsFgbI8w/9SdDjeJlkH # RFb/apdK8xcEktbsGaToEZOp1Wz1vxOMoGVCGayfYZ4byBhTAjOp5YLH2+26JDze # I7o4q2PYENNP4r0ayOIbPcayBzlkp53VROZKILyQfQfwfChnoaFlkBeqVvF/PUxt # CNsei6qDY2jsArhUieZ8CkHbOSlCeg22+7HjNTjp6b1h4lr3p4/tnFobJAYJrtRB # 5v6EGaWnejEvsbcKV0aZhtVITygcny7tENZUkKlKoPeNr4k0R6dyFNKDcShLhv75 # 42ms95D7T/j4weJt6G3E9t1kqFCMl3KM8qwMT7nDJ1xiSVOw329sMtCcazAssDQ/ # 5ecCq9cGSaGUROwlnoUDpQ== # =pzkY # -----END PGP SIGNATURE----- # gpg: Signature made Tue Feb 10 13:51:21 2026 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20260210' of https://gitlab.com/pm215/qemu: (26 commits) target/arm: implement FEAT_E2H0 target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M target/arm: Remove entry for "any" from cpu32 arm_tcg_cpus[] list hw/arm/virt: Rename arm_virt_compat into arm_virt_compat_defaults whpx: arm64: add partition-wide reset on the reboot path whpx: enable arm64 builds target/arm: whpx: instantiate GIC early whpx: arm64: implement -cpu host hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF whpx: arm64: clamp down IPA size target/arm: cpu: mark WHPX as supporting PSCI 1.3 whpx: change memory management logic whpx: add arm64 support hw, target, accel: whpx: change apic_in_platform to kernel_irqchip whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define whpx: ifdef out winhvemulation on non-x86_64 whpx: reshuffle common code whpx: Move around files before introducing AArch64 support docs: arm: update virt machine model description qtest: hw/arm: virt: add new test case for GICv3 + GICv2m ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Jaehoon Kim	00ebc44514	s390x/pci: Fix endianness for zPCI BAR values. During zPCI scan, BAR configuration data retrieved via CLP Query was misinterpreted due to an endianness mismatch between QEMU and the guest kernel. The guest kernel's clp_store_query_pci_fn() expects BAR values in little-endian format and converts them with le32_to_cpu(). However, QEMU was incorrectly sending them in big-endian format, not following the architecture specification. This caused incorrect bit-swapping in the kernel, leading zpci_setup_bus_resources() to perform registration checks against invalid flags, making the process ineffective. Observation values for zPCI device (NVMe passthrough): LPAR from real CLP: [ 0.865595] Resource: PCI Bus 0000:00 -> zdev->bar[0].val: 0x4 [ 0.865597] start: 0x4000000000000000 [ 0.865598] end: 0x4000000000003fff [ 0.865600] flags: 0x100200 QEMU before fix (wrong): [ 0.601083] Resource: PCI Bus 0001:00 -> zdev->bar[0].val: 0x4000000 [ 0.601085] start: 0x4003000000000000 [ 0.601086] end: 0x4003000000003fff [ 0.601087] flags: 0x200 QEMU after fix (correct): [ 0.601116] Resource: PCI Bus 0001:00 -> zdev->bar[0].val: 0x4 [ 0.601117] start: 0x4003000000000000 [ 0.601118] end: 0x4003000000003fff [ 0.601119] flags: 0x100200 Signed-off-by: Jaehoon Kim <jhkim@linux.ibm.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Farhan Ali <alifm@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-ID: <20260206164645.1845366-1-jhkim@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>	2 months ago
Vladimir Sementsov-Ogievskiy	46565a8db1	tpm_emulator: tpm_emulator_set_state_blobs(): move to boolean return The returned error is only used to check for success, so no reason to use specific errno values. Also, this is the only function with -errno contract in the file, so converting it simplifies the whole file from three types of contract (0/-1, 0/-errno, true/false) to only two (0/-1, true/false). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>	2 months ago
Vladimir Sementsov-Ogievskiy	18264ce6d6	tpm_emulator: drop direct use of errno variable The code tends to include errno into error messages after tpm_util_test_tpmdev() and tpm_emulator_ctrlcmd() calls. Both has error paths, where errno is not set, examples: tpm_emulator_ctrlcmd() qemu_chr_fe_write_all() qemu_chr_write() replay_char_write_event_load() ... *res = replay_get_dword(); ... tpm_util_test_tpmdev() tpm_util_test() tpm_util_request() ... if (n != requestlen) { return -EFAULT; } ... Both doesn't document that they set errno. Let's drop these explicit usage of errno. If we need this information, it should be added to errp deeper in the stack. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>	2 months ago
Vladimir Sementsov-Ogievskiy	e4244f84b3	tpm_emulator: print error on error-ignore path Commit `3469a56fa3` introduced errp passthrough for many errors in the file. But in this specific case in tpm_emulator_get_buffer_size(), it simply used errp=NULL, so we lose printed error. Let's bring it back Note also, that `3469a56fa3` was fixing another commit, `42e556fa3f` "backends/tpm: Propagate vTPM error on migration failure" and didn't mention it. Fixes: `3469a56fa3` "tmp_emulator: improve and fix use of errp" Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>	2 months ago
Alex Bennée	a2834b853d	target/arm: implement FEAT_E2H0 FEAT_E2H0 is a formalisation of the existing behaviour of HCR_EL2.E2H being programmable to switch between EL2 host mode and the "traditional" nVHE EL2 mode. This implies at some point we might want to model CPUs without FEAT_E2H0 which will always have EL2 host mode enabled. There are two values to represent no E2H0 systems of which 0b1110 will make HCR_EL2.NV1 RES0 for FEAT_NV systems. For FEAT_NV2 the NV1 bit is always valid. Message-ID: <20260130181648.628364-1-alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr> Message-id: 20260205210231.888199-1-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Ashish Anand	d238858bff	target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M Currently, QEMU implements the 'Wait For Event' (WFE) instruction as a simple yield. This causes high host CPU usage because guest RTOS idle loops effectively become busy-wait loops. To improve efficiency, this patch transitions WFE to use the architectural 'Halt' state (EXCP_HLT) for M-profile CPUs. This allows the host thread to sleep when the guest is idle. To support this transition, we implement the full architectural behavior required for WFE, specifically the 'Event Register', 'SEVONPEND' logic, and 'R_BPBR' exception handling requirements defined in the ARM Architecture Reference Manual. This patch enables resource-efficient idle emulation for Cortex-M. Signed-off-by: Ashish Anand <ashish.a6@samsung.com> Message-id: 20260209051931.122531-1-ashish.a6@samsung.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Philippe Mathieu-Daudé	bc3d2e7067	target/arm: Remove entry for "any" from cpu32 arm_tcg_cpus[] list Since commit `a0032cc542` ("target/arm: Make 'any' CPU just an alias for 'max'") the 'any' CPU QOM type is never used, because we change "any" to "max" before creating the object. The array entry means we have an unnecessary type in the system, and the only user-visible effect is that "any" is listed in the "-cpu help" output for qemu-arm. (System emulation already doesn't include this array entry.) Since qemu-aarch64 already doesn't include "any" in its "-cpu help" output, we can reasonably drop it for qemu-arm also; remove the not-very-useful array entry. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260202153618.78675-2-philmd@linaro.org [PMM: update commit message to note effect on help output.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Eric Auger	5484e94cd4	hw/arm/virt: Rename arm_virt_compat into arm_virt_compat_defaults Renaming arm_virt_compat into arm_virt_compat_defaults makes more obvious that those compats apply to all machine types by default, if not overriden for specific ones. This also matches the terminology used for pc-q35. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Sebastian Ott <sebott@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	ac4af772ad	whpx: arm64: add partition-wide reset on the reboot path This resets non-architectural state to allow for reboots to succeed. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	b21fa1218d	whpx: enable arm64 builds Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	515bf55441	target/arm: whpx: instantiate GIC early While figuring out a better spot for it, put it in whpx_accel_init. Needs to be done before WHvSetupPartition. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	f7fa2b8808	whpx: arm64: implement -cpu host Logic to fetch MIDR_EL1 for cpu 0 adapted from: `e6de17e72e/Source/Windows/Common/CPUFeatures.cpp (L62)` Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	293984563e	hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	ea475a5ebb	whpx: arm64: clamp down IPA size Code taken from HVF and adapted for WHPX use. Note that WHPX doesn't have a default vs maximum IPA distinction. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	5ae1609f00	target/arm: cpu: mark WHPX as supporting PSCI 1.3 Hyper-V supports PSCI 1.3, and that implementation is exposed through WHPX. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	bf36e65bda	whpx: change memory management logic This allows edk2 to work on Arm, although u-boot is still not functional. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	59432082ce	whpx: add arm64 support Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	e4c95f78a4	hw, target, accel: whpx: change apic_in_platform to kernel_irqchip Change terminology to match the KVM one, as APIC is x86-specific. And move out whpx_irqchip_in_kernel() to make it usable from common code even when not compiling with WHPX support. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	7573977b4e	whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define As of why: WHPX on arm64 doesn't have debug trap support as of today. Keep the exception bitmap interface for now - despite that being entirely unavailable on arm64 too. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	69ac30ea1b	whpx: ifdef out winhvemulation on non-x86_64 winhvemulation is x86_64 only. In the future, we might want to get rid of winhvemulation usage entirely. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	4610fee324	whpx: reshuffle common code Some code can be shared between x86_64 and arm64 WHPX. Do so as much as reasonable. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	1f1f9fd88c	whpx: Move around files before introducing AArch64 support Switch to a design where we can share whpx code between x86 and AArch64 when it makes sense to do so. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	5bc283d705	docs: arm: update virt machine model description Update the documentation to match current QEMU. Remove the mention of pre-2.7 machine models as those aren't provided anymore. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	72a231af4c	qtest: hw/arm: virt: add new test case for GICv3 + GICv2m Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	5f52ba1f34	qtest: hw/arm: virt: add ACPI tables for new GICv3 + GICv2m test case Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	2e1bb23b44	tests: data: update AArch64 ACPI tables After the previous commit introducing GICv3 + GICv2m configurations, update the AArch64 ACPI tables for the GICv2 case. Changes to the ACPI tables: tests/data/acpi/aarch64/virt/IORT.dsl: @@ -11,68 +11,49 @@ / [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 00000080 +[004h 0004 004h] Table Length : 00000054 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : B1 +[009h 0009 001h] Checksum : 3C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000002 +[024h 0036 004h] Node Count : 00000001 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 02 +[031h 0049 002h] Length : 0024 +[033h 0051 001h] Revision : 03 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 -[03Ch 0060 004h] Mapping Offset : 00000000 +[03Ch 0060 004h] Mapping Offset : 00000024 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 02 -[049h 0073 002h] Length : 0038 -[04Bh 0075 001h] Revision : 03 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000024 - -[058h 0088 008h] Memory Properties : [IORT Memory Access Properties] -[058h 0088 004h] Cache Coherency : 00000001 -[05Ch 0092 001h] Hints (decoded below) : 00 +[040h 0064 008h] Memory Properties : [IORT Memory Access Properties] +[040h 0064 004h] Cache Coherency : 00000001 +[044h 0068 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[05Dh 0093 002h] Reserved : 0000 -[05Fh 0095 001h] Memory Flags (decoded below) : 03 +[045h 0069 002h] Reserved : 0000 +[047h 0071 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[060h 0096 004h] ATS Attribute : 00000000 -[064h 0100 004h] PCI Segment Number : 00000000 -[068h 0104 001h] Memory Size Limit : 40 -[069h 0105 002h] PASID Capabilities : 0000 -[06Bh 0107 001h] Reserved : 00 +[048h 0072 004h] ATS Attribute : 00000000 +[04Ch 0076 004h] PCI Segment Number : 00000000 +[050h 0080 001h] Memory Size Limit : 40 +[051h 0081 002h] PASID Capabilities : 0000 +[053h 0083 001h] Reserved : 00 -[06Ch 0108 004h] Input base : 00000000 -[070h 0112 004h] ID Count : 0000FFFF -[074h 0116 004h] Output Base : 00000000 -[078h 0120 004h] Output Reference : 00000030 -[07Ch 0124 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 84 (0x54) -Raw Table Data: Length 128 (0x80) - - 0000: 49 4F 52 54 80 00 00 00 05 B1 42 4F 43 48 53 20 // IORT......BOCHS + 0000: 49 4F 52 54 54 00 00 00 05 3C 42 4F 43 48 53 20 // IORTT....<BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 02 38 00 03 01 00 00 00 // .........8...... - 0050: 01 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... - 0060: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... - 0070: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0020: 01 00 00 00 01 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 02 24 00 03 00 00 00 00 00 00 00 00 24 00 00 00 // .$..........$... + 0040: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ + 0050: 40 00 00 00 // @... tests/data/acpi/aarch64/virt/IORT.smmuv3-dev.dsl: @@ -11,164 +11,120 @@ / [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 0000016C +[004h 0004 004h] Table Length : 00000104 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : C8 +[009h 0009 001h] Checksum : 49 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000004 +[024h 0036 004h] Node Count : 00000003 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0044 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 000000000C000000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 000000000C000000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 00000090 -[078h 0120 004h] PRI GSIV : 00000091 -[07Ch 0124 004h] GERR GSIV : 00000093 -[080h 0128 004h] Sync GSIV : 00000092 -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 00000090 +[060h 0096 004h] PRI GSIV : 00000091 +[064h 0100 004h] GERR GSIV : 00000093 +[068h 0104 004h] Sync GSIV : 00000092 +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[074h 0116 001h] Type : 04 +[075h 0117 002h] Length : 0044 +[077h 0119 001h] Revision : 04 +[078h 0120 004h] Identifier : 00000001 +[07Ch 0124 004h] Mapping Count : 00000000 +[080h 0128 004h] Mapping Offset : 00000000 -[0A0h 0160 001h] Type : 04 -[0A1h 0161 002h] Length : 0058 -[0A3h 0163 001h] Revision : 04 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000001 -[0ACh 0172 004h] Mapping Offset : 00000044 - -[0B0h 0176 008h] Base Address : 000000000C020000 -[0B8h 0184 004h] Flags (decoded below) : 00000001 +[084h 0132 008h] Base Address : 000000000C020000 +[08Ch 0140 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[0BCh 0188 004h] Reserved : 00000000 -[0C0h 0192 008h] VATOS Address : 0000000000000000 -[0C8h 0200 004h] Model : 00000000 -[0CCh 0204 004h] Event GSIV : 00000094 -[0D0h 0208 004h] PRI GSIV : 00000095 -[0D4h 0212 004h] GERR GSIV : 00000097 -[0D8h 0216 004h] Sync GSIV : 00000096 -[0DCh 0220 004h] Proximity Domain : 00000000 -[0E0h 0224 004h] Device ID Mapping Index : 00000000 +[090h 0144 004h] Reserved : 00000000 +[094h 0148 008h] VATOS Address : 0000000000000000 +[09Ch 0156 004h] Model : 00000000 +[0A0h 0160 004h] Event GSIV : 00000094 +[0A4h 0164 004h] PRI GSIV : 00000095 +[0A8h 0168 004h] GERR GSIV : 00000097 +[0ACh 0172 004h] Sync GSIV : 00000096 +[0B0h 0176 004h] Proximity Domain : 00000000 +[0B4h 0180 004h] Device ID Mapping Index : 00000000 -[0E4h 0228 004h] Input base : 00000000 -[0E8h 0232 004h] ID Count : 0000FFFF -[0ECh 0236 004h] Output Base : 00000000 -[0F0h 0240 004h] Output Reference : 00000030 -[0F4h 0244 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[0B8h 0184 001h] Type : 02 +[0B9h 0185 002h] Length : 004C +[0BBh 0187 001h] Revision : 03 +[0BCh 0188 004h] Identifier : 00000002 +[0C0h 0192 004h] Mapping Count : 00000002 +[0C4h 0196 004h] Mapping Offset : 00000024 -[0F8h 0248 001h] Type : 02 -[0F9h 0249 002h] Length : 0074 -[0FBh 0251 001h] Revision : 03 -[0FCh 0252 004h] Identifier : 00000003 -[100h 0256 004h] Mapping Count : 00000004 -[104h 0260 004h] Mapping Offset : 00000024 - -[108h 0264 008h] Memory Properties : [IORT Memory Access Properties] -[108h 0264 004h] Cache Coherency : 00000001 -[10Ch 0268 001h] Hints (decoded below) : 00 +[0C8h 0200 008h] Memory Properties : [IORT Memory Access Properties] +[0C8h 0200 004h] Cache Coherency : 00000001 +[0CCh 0204 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[10Dh 0269 002h] Reserved : 0000 -[10Fh 0271 001h] Memory Flags (decoded below) : 03 +[0CDh 0205 002h] Reserved : 0000 +[0CFh 0207 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[110h 0272 004h] ATS Attribute : 00000000 -[114h 0276 004h] PCI Segment Number : 00000000 -[118h 0280 001h] Memory Size Limit : 40 -[119h 0281 002h] PASID Capabilities : 0000 -[11Bh 0283 001h] Reserved : 00 +[0D0h 0208 004h] ATS Attribute : 00000000 +[0D4h 0212 004h] PCI Segment Number : 00000000 +[0D8h 0216 001h] Memory Size Limit : 40 +[0D9h 0217 002h] PASID Capabilities : 0000 +[0DBh 0219 001h] Reserved : 00 -[11Ch 0284 004h] Input base : 00000000 -[120h 0288 004h] ID Count : 000001FF -[124h 0292 004h] Output Base : 00000000 -[128h 0296 004h] Output Reference : 00000048 -[12Ch 0300 004h] Flags (decoded below) : 00000000 +[0DCh 0220 004h] Input base : 00000000 +[0E0h 0224 004h] ID Count : 000001FF +[0E4h 0228 004h] Output Base : 00000000 +[0E8h 0232 004h] Output Reference : 00000030 +[0ECh 0236 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[130h 0304 004h] Input base : 00001000 -[134h 0308 004h] ID Count : 000000FF -[138h 0312 004h] Output Base : 00001000 -[13Ch 0316 004h] Output Reference : 000000A0 -[140h 0320 004h] Flags (decoded below) : 00000000 +[0F0h 0240 004h] Input base : 00001000 +[0F4h 0244 004h] ID Count : 000000FF +[0F8h 0248 004h] Output Base : 00001000 +[0FCh 0252 004h] Output Reference : 00000074 +[100h 0256 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[144h 0324 004h] Input base : 00000200 -[148h 0328 004h] ID Count : 00000DFF -[14Ch 0332 004h] Output Base : 00000200 -[150h 0336 004h] Output Reference : 00000030 -[154h 0340 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 260 (0x104) -[158h 0344 004h] Input base : 00001100 -[15Ch 0348 004h] ID Count : 0000EEFF -[160h 0352 004h] Output Base : 00001100 -[164h 0356 004h] Output Reference : 00000030 -[168h 0360 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 - -Raw Table Data: Length 364 (0x16C) - - 0000: 49 4F 52 54 6C 01 00 00 05 C8 42 4F 43 48 53 20 // IORTl.....BOCHS + 0000: 49 4F 52 54 04 01 00 00 05 49 42 4F 43 48 53 20 // IORT.....IBOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 04 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 00 0C 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 90 00 00 00 91 00 00 00 93 00 00 00 // ................ - 0080: 92 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 04 58 00 04 02 00 00 00 01 00 00 00 44 00 00 00 // .X..........D... - 00B0: 00 00 02 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................ - 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 94 00 00 00 // ................ - 00D0: 95 00 00 00 97 00 00 00 96 00 00 00 00 00 00 00 // ................ - 00E0: 00 00 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 // ................ - 00F0: 30 00 00 00 00 00 00 00 02 74 00 03 03 00 00 00 // 0........t...... - 0100: 04 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... - 0110: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... - 0120: FF 01 00 00 00 00 00 00 48 00 00 00 00 00 00 00 // ........H....... - 0130: 00 10 00 00 FF 00 00 00 00 10 00 00 A0 00 00 00 // ................ - 0140: 00 00 00 00 00 02 00 00 FF 0D 00 00 00 02 00 00 // ................ - 0150: 30 00 00 00 00 00 00 00 00 11 00 00 FF EE 00 00 // 0............... - 0160: 00 11 00 00 30 00 00 00 00 00 00 00 // ....0....... + 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D.............. + 0040: 00 00 00 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 // ................ + 0060: 91 00 00 00 93 00 00 00 92 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 04 44 00 04 01 00 00 00 00 00 00 00 // .....D.......... + 0080: 00 00 00 00 00 00 02 0C 00 00 00 00 01 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 94 00 00 00 95 00 00 00 97 00 00 00 96 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 02 4C 00 03 02 00 00 00 // .........L...... + 00C0: 02 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... + 00D0: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... + 00E0: FF 01 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 00F0: 00 10 00 00 FF 00 00 00 00 10 00 00 74 00 00 00 // ............t... + 0100: 00 00 00 00 // .... tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy.dsl: @@ -11,129 +11,92 @@ */ [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 00000114 +[004h 0004 004h] Table Length : 000000C0 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : 4A +[009h 0009 001h] Checksum : 1C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000003 +[024h 0036 004h] Node Count : 00000002 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0044 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 0000000009050000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 0000000009050000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 0000006A -[078h 0120 004h] PRI GSIV : 0000006B -[07Ch 0124 004h] GERR GSIV : 0000006D -[080h 0128 004h] Sync GSIV : 0000006C -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 0000006A +[060h 0096 004h] PRI GSIV : 0000006B +[064h 0100 004h] GERR GSIV : 0000006D +[068h 0104 004h] Sync GSIV : 0000006C +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[074h 0116 001h] Type : 02 +[075h 0117 002h] Length : 004C +[077h 0119 001h] Revision : 03 +[078h 0120 004h] Identifier : 00000001 +[07Ch 0124 004h] Mapping Count : 00000002 +[080h 0128 004h] Mapping Offset : 00000024 -[0A0h 0160 001h] Type : 02 -[0A1h 0161 002h] Length : 0074 -[0A3h 0163 001h] Revision : 03 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000004 -[0ACh 0172 004h] Mapping Offset : 00000024 - -[0B0h 0176 008h] Memory Properties : [IORT Memory Access Properties] -[0B0h 0176 004h] Cache Coherency : 00000001 -[0B4h 0180 001h] Hints (decoded below) : 00 +[084h 0132 008h] Memory Properties : [IORT Memory Access Properties] +[084h 0132 004h] Cache Coherency : 00000001 +[088h 0136 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 002h] Reserved : 0000 -[0B7h 0183 001h] Memory Flags (decoded below) : 03 +[089h 0137 002h] Reserved : 0000 +[08Bh 0139 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[0B8h 0184 004h] ATS Attribute : 00000000 -[0BCh 0188 004h] PCI Segment Number : 00000000 -[0C0h 0192 001h] Memory Size Limit : 40 -[0C1h 0193 002h] PASID Capabilities : 0000 -[0C3h 0195 001h] Reserved : 00 +[08Ch 0140 004h] ATS Attribute : 00000000 +[090h 0144 004h] PCI Segment Number : 00000000 +[094h 0148 001h] Memory Size Limit : 40 +[095h 0149 002h] PASID Capabilities : 0000 +[097h 0151 001h] Reserved : 00 -[0C4h 0196 004h] Input base : 00000000 -[0C8h 0200 004h] ID Count : 000001FF -[0CCh 0204 004h] Output Base : 00000000 -[0D0h 0208 004h] Output Reference : 00000048 -[0D4h 0212 004h] Flags (decoded below) : 00000000 +[098h 0152 004h] Input base : 00000000 +[09Ch 0156 004h] ID Count : 000001FF +[0A0h 0160 004h] Output Base : 00000000 +[0A4h 0164 004h] Output Reference : 00000030 +[0A8h 0168 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0D8h 0216 004h] Input base : 00001000 -[0DCh 0220 004h] ID Count : 000000FF -[0E0h 0224 004h] Output Base : 00001000 -[0E4h 0228 004h] Output Reference : 00000048 -[0E8h 0232 004h] Flags (decoded below) : 00000000 +[0ACh 0172 004h] Input base : 00001000 +[0B0h 0176 004h] ID Count : 000000FF +[0B4h 0180 004h] Output Base : 00001000 +[0B8h 0184 004h] Output Reference : 00000030 +[0BCh 0188 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0ECh 0236 004h] Input base : 00000200 -[0F0h 0240 004h] ID Count : 00000DFF -[0F4h 0244 004h] Output Base : 00000200 -[0F8h 0248 004h] Output Reference : 00000030 -[0FCh 0252 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 192 (0xC0) -[100h 0256 004h] Input base : 00001100 -[104h 0260 004h] ID Count : 0000EEFF -[108h 0264 004h] Output Base : 00001100 -[10Ch 0268 004h] Output Reference : 00000030 -[110h 0272 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 - -Raw Table Data: Length 276 (0x114) - - 0000: 49 4F 52 54 14 01 00 00 05 4A 42 4F 43 48 53 20 // IORT.....JBOCHS + 0000: 49 4F 52 54 C0 00 00 00 05 1C 42 4F 43 48 53 20 // IORT......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 05 09 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 6A 00 00 00 6B 00 00 00 6D 00 00 00 // ....j...k...m... - 0080: 6C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // l............... - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 02 74 00 03 02 00 00 00 04 00 00 00 24 00 00 00 // .t..........$... - 00B0: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ - 00C0: 40 00 00 00 00 00 00 00 FF 01 00 00 00 00 00 00 // @............... - 00D0: 48 00 00 00 00 00 00 00 00 10 00 00 FF 00 00 00 // H............... - 00E0: 00 10 00 00 48 00 00 00 00 00 00 00 00 02 00 00 // ....H........... - 00F0: FF 0D 00 00 00 02 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0100: 00 11 00 00 FF EE 00 00 00 11 00 00 30 00 00 00 // ............0... - 0110: 00 00 00 00 // .... + 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D.............. + 0040: 00 00 05 09 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 6A 00 00 00 // ............j... + 0060: 6B 00 00 00 6D 00 00 00 6C 00 00 00 00 00 00 00 // k...m...l....... + 0070: 00 00 00 00 02 4C 00 03 01 00 00 00 02 00 00 00 // .....L.......... + 0080: 24 00 00 00 01 00 00 00 00 00 00 03 00 00 00 00 // $............... + 0090: 00 00 00 00 40 00 00 00 00 00 00 00 FF 01 00 00 // ....@........... + 00A0: 00 00 00 00 30 00 00 00 00 00 00 00 00 10 00 00 // ....0........... + 00B0: FF 00 00 00 00 10 00 00 30 00 00 00 00 00 00 00 // ........0....... Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	5f834ccdcf	hw: arm: virt: rework MSI-X configuration Introduce a -M msi= argument to be able to control MSI-X support independently from ITS, as part of supporting GICv3 + GICv2m platforms. Remove vms->its as it's no longer needed after that change. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago

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126813 Commits (7c79c954aaab9391f554f2d3ef12abeefb1345db) All Branches Search

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