4 Commits (6a8b1ae2020bf06d438f6bfd05a0e8fc2abe10d1)

Author SHA1 Message Date
ths b5dc7732e1 More efficient target register / TC accesses. 18 years ago
ths d0dc7dc327 Make MIPS MT implementation more cache friendly. 18 years ago
blueswir1 992f48a036 Support for 32 bit ABI on 64 bit targets (only enabled Sparc64) 19 years ago
ths 540635ba65 Code provision for n32/n64 mips userland emulation. Not functional yet. 19 years ago