When vIOMMU is configured x-flts=on in scalable mode, first stage page table
is passed to host to construct nested page table for passthrough devices.
We need to check compatibility of some critical IOMMU capabilities between
vIOMMU and host IOMMU to ensure guest first stage page table could be used by
host.
For instance, vIOMMU supports first stage 1GB large page mapping, but host does
not, then this IOMMUFD backed device should fail.
Even of the checks pass, for now we willingly reject the association because
all the bits are not there yet, it will be relaxed in the end of this series.
Note vIOMMU has exposed VIOMMU_FLAG_WANT_NESTING_PARENT flag to force
VFIO core to create nesting parent HWPT, if host doesn't support nested
translation, the creation will fail. So no need to check nested
capability here.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-10-zhenzhong.duan@intel.com
[ clg: - hw/i386/intel_iommu_accel.[hc]: Changed Copyright date 2025 -> 2026
- in commit log :
IOMMU_HWPT_ALLOC_NEST_PARENT -> VIOMMU_FLAG_WANT_NESTING_PARENT ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Call pci_device_get_viommu_flags() to get if vIOMMU supports
VIOMMU_FLAG_WANT_NESTING_PARENT.
If yes, create a nesting parent HWPT and add it to the container's hwpt_list,
letting this parent HWPT cover the entire second stage mappings (GPA=>HPA).
This allows a VFIO passthrough device to directly attach to this default HWPT
and then to use the system address space and its listener.
Introduce a vfio_device_get_viommu_flags_want_nesting() helper to facilitate
this implementation.
It is safe to do so because a vIOMMU will be able to fail in set_iommu_device()
call, if something else related to the VFIO device or vIOMMU isn't compatible.
Suggested-by: Nicolin Chen <nicolinc@nvidia.com>
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-9-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Introduce a new structure VTDHostIOMMUDevice which replaces
HostIOMMUDevice to be stored in hash table.
It includes a reference to HostIOMMUDevice and IntelIOMMUState,
also includes BDF information which will be used in future
patches.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-8-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Implement get_viommu_flags() callback and expose a request for nesting
parent HWPT for now.
VFIO uses it to create nesting parent HWPT which is further used to create
nested HWPT in vIOMMU. All these will be implemented in following patches.
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-7-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Introduce a new PCIIOMMUOps optional callback, get_viommu_flags() which
allows to retrieve flags exposed by a vIOMMU. The first planned vIOMMU
device flag is VIOMMU_FLAG_WANT_NESTING_PARENT that advertises the
support of HW nested stage translation scheme and wants other sub-system
like VFIO's cooperation to create nesting parent HWPT.
pci_device_get_viommu_flags() is a wrapper that can be called on a PCI
device potentially protected by a vIOMMU.
get_viommu_flags() is designed to return 64bit bitmap of purely vIOMMU
flags which are only determined by user's configuration, no host
capabilities involved. Reasons are:
1. host may has heterogeneous IOMMUs, each with different capabilities
2. this is migration friendly, return value is consistent between source
and target.
Note that this op will be invoked at the attach_device() stage, at which
point host IOMMU capabilities are not yet forwarded to the vIOMMU through
the set_iommu_device() callback that will be after the attach_device().
See below sequence:
vfio_device_attach():
iommufd_cdev_attach():
pci_device_get_viommu_flags() for HW nesting cap
create a nesting parent HWPT
attach device to the HWPT
vfio_device_hiod_create_and_realize() creating hiod
...
pci_device_set_iommu_device(hiod)
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-6-zhenzhong.duan@intel.com
[ clg: include/hw/core/iommu.h: Changed Copyright date 2025 -> 2026 ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Returns true if PCI device is aliased or false otherwise. This will be
used in following patch to determine if a PCI device is under a PCI
bridge.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-5-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
VTD spec revision 3.4 released in December 2021 renamed "First-level" to
"First-stage" and "Second-level" to "Second-stage".
Do the same in intel_iommu code to match spec, change all existing
"fl/sl/FL/SL/first level/second level/stage-1/stage-2" terminology to
"fs/ss/FS/SS/first stage/second stage".
Opportunistically fix a error print of "flts=on" with "x-flts=on".
No functional changes intended.
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Suggested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-4-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
RID-PASID Support(RPS) is not set in vIOMMU ECAP register, the supporting
code is there but never takes effect.
Meanwhile, according to VTD spec section 3.4.3:
"Implementations not supporting RID_PASID capability (ECAP_REG.RPS is 0b),
use a PASID value of 0 to perform address translation for requests without
PASID."
We should delete the supporting code which fetches RID_PASID field from
scalable context entry and use 0 as RID_PASID directly, because RID_PASID
field is ignored if no RPS support according to spec.
This simplifies the code and doesn't bring any penalty.
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-3-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry
of rid2pasid, then it was extended to get any pasid entry. So a new name
vtd_ce_get_pasid_entry is better to match what it actually does.
No functional change intended.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-2-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Inline vfio_arch_wants_loading_config_after_iter() and
replace the compile time check of the TARGET_ARM definition
by a runtime call to target_base_arm().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Link: https://lore.kernel.org/qemu-devel/20251021161707.8324-1-philmd@linaro.org
Signed-off-by: Cédric Le Goater <clg@redhat.com>
- Endianness cleanups in memory core subsystem and for various targets
- Few cleanups around target_ulong type
- Build various compilation units as common
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmlleisACgkQ4+MsLN6t
wN40yw/+NYK6Q+v8YHclH0g6YkPsXYsCVOLWhYaUQ9Smc3Vk8js02LRMxomGiyjc
lRhatftrH4dCuiWavyhlK/z+tu3b2WOgjjcIocg7ztZEwzyvDPEKidBNM4Wrv27d
6WNdtCn1rOOYQBcCs/MEHnrxIl3qfl5Kqt4hzejcK4E1DFa1m5ashAEVJwMlqYWp
qkBT3fw0jfHojM+eTAbvKI1fi27GVMXbQXSM3V3vG3njxmx4JQT0p9QjyDYWZwgh
xAJvy5neoNv3T7TBELCfqSWzGA5WHrW/eAkuRuO0JVa69IOn/mh2aGKboJMT7KQF
ufyxceHMj8TLJr6c9BrvaWX7+p7xyvbX3ud+qXOV9P2FBVm+hf2lHnw0pJJ6A51g
qv3u8zUVwhmx6oF95ibQtaWKdLNhGCKtVKJu59Xxj/7Bp00BS1Jnj6E/g34To8Vm
18g3cPJ+CEhdTFSkcHusiVI4GdHb8JEGUd5kyWza3gEgYb/J1Ps/a807n6C6NQcq
MRkt2zNKS+sJeZzvl+BGH8WewMVGWm1f8IoP28ZvgyxFVutkgFcj+UQZp3J7mkpV
ja0B7+1NMK9oMeq/+YM4gUgEF0ydThlqa+qTzxVYu8qpzWT9+cqqWeQHAteE3g/v
rqqu/sBUSbh5xi+82zRbgwd7Hj31ST5XkepQN0vUTT4P3zCijy8=
=P+9/
-----END PGP SIGNATURE-----
Merge tag 'single-binary-20260112' of https://github.com/philmd/qemu into staging
Various patches related to single binary effort:
- Endianness cleanups in memory core subsystem and for various targets
- Few cleanups around target_ulong type
- Build various compilation units as common
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmlleisACgkQ4+MsLN6t
# wN40yw/+NYK6Q+v8YHclH0g6YkPsXYsCVOLWhYaUQ9Smc3Vk8js02LRMxomGiyjc
# lRhatftrH4dCuiWavyhlK/z+tu3b2WOgjjcIocg7ztZEwzyvDPEKidBNM4Wrv27d
# 6WNdtCn1rOOYQBcCs/MEHnrxIl3qfl5Kqt4hzejcK4E1DFa1m5ashAEVJwMlqYWp
# qkBT3fw0jfHojM+eTAbvKI1fi27GVMXbQXSM3V3vG3njxmx4JQT0p9QjyDYWZwgh
# xAJvy5neoNv3T7TBELCfqSWzGA5WHrW/eAkuRuO0JVa69IOn/mh2aGKboJMT7KQF
# ufyxceHMj8TLJr6c9BrvaWX7+p7xyvbX3ud+qXOV9P2FBVm+hf2lHnw0pJJ6A51g
# qv3u8zUVwhmx6oF95ibQtaWKdLNhGCKtVKJu59Xxj/7Bp00BS1Jnj6E/g34To8Vm
# 18g3cPJ+CEhdTFSkcHusiVI4GdHb8JEGUd5kyWza3gEgYb/J1Ps/a807n6C6NQcq
# MRkt2zNKS+sJeZzvl+BGH8WewMVGWm1f8IoP28ZvgyxFVutkgFcj+UQZp3J7mkpV
# ja0B7+1NMK9oMeq/+YM4gUgEF0ydThlqa+qTzxVYu8qpzWT9+cqqWeQHAteE3g/v
# rqqu/sBUSbh5xi+82zRbgwd7Hj31ST5XkepQN0vUTT4P3zCijy8=
# =P+9/
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 13 Jan 2026 09:48:11 AM AEDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'single-binary-20260112' of https://github.com/philmd/qemu: (61 commits)
target/arm/gdbstub: make compilation unit common
target/arm/gdbstub: extract aarch64_cpu_register_gdb_regs_for_features
gdbstub/helpers.h: allow header to be called from common code
accel/tcg: Un-inline WatchPoint API user-emulation stubs
target/tricore: Build system units in common source set
target/tricore: Inline translator_lduw()
target/tricore: Use little-endian variant of cpu_ld/st_data*()
target/sparc: Inline cpu_ldl_code() call in cpu_do_interrupt()
target/sparc: Inline translator_ldl()
target/sparc: Use explicit big-endian LD/ST API
hw/sparc: Use explicit big-endian LD/ST API
hw/sparc: Mark SPARC-specific peripherals as big-endian
target/sh4: drop cpu_reset from realizefn
target/sh4: Build system units in common source set
target/rx: Build system units in common source set
target/rx: Inline translator_lduw() and translator_ldl()
target/rx: Use explicit little-endian LD/ST API
target/rx: Use little-endian variant of cpu_ld/st_data*()
target/openrisc: Build system units in common source set
target/openrisc: Avoid target-specific migration headers in machine.c
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Expose and stubs aarch64 functions. All call sites are under a
"is_aarch64" check.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109053158.2800705-4-pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Target specific variants can't be used in common code, thus limit their
definition to COMPILING_PER_TARGET.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109053158.2800705-2-pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Currently we can not build files including "exec/watchpoint.h"
as meson common objects because the CONFIG_USER_ONLY definition
is poisoned. We can easily fix that by un-inlining the
user-emulation stubs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106231908.16756-5-philmd@linaro.org>
Since commit range 809b460f305..cd08bcaa36b we remove all
uses of the target_ulong type in target/rx/. Use the meson
target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-4-philmd@linaro.org>
translator_lduw() is defined in "exec/translator.h" as:
192 static inline uint16_t
193 translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc)
194 {
195 return translator_lduw_end(env, db, pc, MO_TE);
196 }
Directly use the inlined form, expanding MO_TE -> MO_LE
since we only build the TriCore target as little-endian.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224163005.91137-3-philmd@linaro.org>
We only build the TriCore target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=tricore; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Then adapting spaces style manually to pass checkpatch.pl.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20251126202200.23100-6-philmd@linaro.org>
In preparation of removing the cpu_ldl_code wrapper, inline it.
Since SPARC instructions are always stored in big-endian order,
replace MO_TE -> MO_BE.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224162642.90857-8-philmd@linaro.org>
translator_ldl() is defined in "exec/translator.h" as:
198 static inline uint32_t
199 translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc)
200 {
201 return translator_ldl_end(env, db, pc, MO_TE);
202 }
Directly use the inlined form, expanding MO_TE -> MO_BE
since we only build the SPARC targets as big-endian.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224162642.90857-7-philmd@linaro.org>
The SPARC architecture uses big endianness. Directly use
the big-endian LD/ST API.
Mechanical change running:
$ for a in uw w l q; do \
sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \
$(git grep -wlE '(ld|st)u?[wlq]_p' target/sparc/);
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224162642.90857-5-philmd@linaro.org>
The SPARC architecture uses big endianness. Directly use
the big-endian LD/ST API.
Mechanical change running:
$ for a in uw w l q; do \
sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \
$(git grep -wlE '(ld|st)u?[wlq]_p' hw/sparc*/);
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Chigot Clément <chigot@adacore.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20251218221457.73341-2-philmd@linaro.org>
These devices are only used by the SPARC target, which is
only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_BIG_ENDIAN (besides, the
DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly
using DEVICE_BIG_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224162642.90857-2-philmd@linaro.org>
Shuffle things around to ensure that gdb register creation was
done after dependant peripherals had created their cpu interfaces.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260108143423.1378674-2-alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Since commit range 42c90609b8f..82a1e739010 we remove all
uses of the target_ulong type in target/rx/. Use the meson
target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-3-philmd@linaro.org>
Since commit range 2982b948a9f..86114e43ffd we remove all
uses of the target_ulong type in target/rx/. Use the meson
target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-2-philmd@linaro.org>
The RX architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' target/rx/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224163304.91384-3-philmd@linaro.org>
We only build the RX target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=rx; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20251126202200.23100-5-philmd@linaro.org>
Since previous 2 commits and range 2795bc52af4..5b67dbf1dc3 we
remove all uses of the target_ulong type in target/rx/. Use the
meson target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-7-philmd@linaro.org>
machine.c doesn't use any target-specific macro defined by
the "migration/cpu.h" header. Use the minimum header required:
"migration/qemu-file-types.h" and "migration/vmstate.h", which
are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Prasad Pandit <pjp@fedoraproject.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-6-philmd@linaro.org>
"gdbstub/helpers.h" uses target-specific symbols, but we don't
need it, so remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-5-philmd@linaro.org>
The OpenRISC architecture uses big endianness. Directly
use the big-endian LD/ST API.
Mechanical change running:
$ for a in uw w l q; do \
sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \
$(git grep -wlE '(ld|st)u?[wlq]_p' target/openrisc/);
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224161804.90064-3-philmd@linaro.org>
The Open Multi-Processor Interrupt Controller (ompic) is only
used by the OpenRISC target, which is only built as big-endian.
Therefore the DEVICE_NATIVE_ENDIAN definition expand to
DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't
tested). Simplify directly using DEVICE_BIG_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224161804.90064-2-philmd@linaro.org>
Previous commit removed the last target-specific use in
hw model units, we can now build them once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-7-philmd@linaro.org>
Check endianness at runtime to remove the target-specific
TARGET_BIG_ENDIAN definition.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-6-philmd@linaro.org>
Previous commit removed the last target-specific use in
system units, we can now build them once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-5-philmd@linaro.org>
machine.c doesn't use any target-specific macro defined by
the "migration/cpu.h" header. Use the minimum header requiered:
"migration/qemu-file-types.h" and "migration/vmstate.h", which
are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-4-philmd@linaro.org>
The MicroBlazeCPUConfig::endi flag reports whether the CPU is
configure in little endianness. Directly use this knowledge
instead of evaluating MemOp from mo_endian().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-3-philmd@linaro.org>
m68k's monitor_defs[] array implicitly uses type=MD_TLONG for
all its entries. Since we only build this target as 32-bit,
use the explicit MD_I32 type to avoid an indirect target_long
use.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-10-philmd@linaro.org>
The LoongArch architecture uses little endianness. Directly
use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' target/loongarch/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-1-philmd@linaro.org>
In preparation of removing the cpu_ldl_code wrapper, inline it.
Since LoongArch instructions are always stored in little-endian
order, replace MO_TE -> MO_LE.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20251224161456.89707-6-philmd@linaro.org>
We only build the LoongArch target using little endianness
order, therefore the MO_TE definitions expand to the little
endian one. Use the latter which is more explicit.
Mechanical change running:
$ sed -i -e s/MO_TE/MO_LE/ \
$(git grep -wl MO_TE target/loongarch/)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-5-philmd@linaro.org>
Replace variables used with get_physical_address(), which
expect a physical addresses, by the 'hwaddr' type, instead
of the 'target_ulong' one.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-4-philmd@linaro.org>
The Direct Mapping Configuration Window and Bad Virtual
Address CSR registers are declared as uint64_t since their
introduction in commit 398cecb9c3 ("target/loongarch: Add
CSRs definition"):
296 typedef struct CPUArchState {
...
345 uint64_t CSR_TLBRBADV;
...
359 uint64_t CSR_DMW[4];
...
385 } CPULoongArchState;
Use the proper uint64_t type instead of target_ulong
(which would otherwise be truncated on 32-bit builds).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20251224161456.89707-3-philmd@linaro.org>
The LoongArch architecture uses little endianness. Directly
use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/loongarch/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-2-philmd@linaro.org>
Since commit 85c19af63e ("include/exec: Use vaddr in DisasContextBase
virtual addresses") the DisasContextBase::pc_first field is a vaddr
type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-9-philmd@linaro.org>
Zhenzhong Duan
Philippe Mathieu-Daudé
Richard Henderson
Pierrick Bouvier
Alex Bennée