riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Gustavo Romero	676ab6a211	tests/tcg: Fix run for tests with specific plugin Commit `25aaf0cb7f` (“tests/tcg: reduce the number of plugin test combinations”) added support for running tests with specific plugins passed via the EXTRA_RUNS variable. However, due to the optimization, the rules generated as a shuffled combination of tests and plugins might not cover the rules required to run the tests with a specific plugin passed via EXTRA_RUNS. This commit fixes it by correctly generating the rules for the tests that require a specific plugin to run, which are now passed via the EXTRA_RUNS_WITH_PLUGIN instead of via the EXTRA_RUNS variable. The fix essentially excludes the tests passed via EXTRA_RUNS_WITH_PLUGIN from the rules created by the shuffled combination of tests and plugins, to avoid running the tests twice, and generates the rules for the test/plugin combinations listed in the EXTRA_RUNS_WITH_PLUGIN variable. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250801001305.2352554-1-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	8 months ago
Vacha Bhavsar	97b3d732af	target/arm: Fix handling of setting SVE registers from gdb The code to handle setting SVE registers via the gdbstub is broken: * it sets each pair of elements in the zregs[].d[] array in the wrong order for the most common (little endian) case: the least significant 64-bit value comes first * it makes no attempt to handle target_endian() * it does a simple copy out of the (target endian) gdbstub buffer into the (host endan) zregs data structure, which is wrong on big endian hosts Fix all these problems: * use ldq_p() to read from the gdbstub buffer * check target_big_endian() to see if we need to handle the 128-bit values the opposite way around Cc: qemu-stable@nongnu.org Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> Message-id: 20250722173736.2332529-3-vacha.bhavsar@oss.qualcomm.com [PMM: adjusted commit message, fixed spacing] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	8 months ago
Vacha Bhavsar	35cca0f95f	target/arm: Fix big-endian handling of NEON gdb remote debugging In the code for allowing the gdbstub to set the value of an AArch64 FP/SIMD register, we weren't accounting for target_big_endian() being true. This meant that for aarch64_be-linux-user we would set the two halves of the FP register the wrong way around. The much more common case of a little-endian guest is not affected; nor are big-endian hosts. Correct the handling of this case. Cc: qemu-stable@nongnu.org Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> Message-id: 20250722173736.2332529-2-vacha.bhavsar@oss.qualcomm.com [PMM: added comment, expanded commit message, fixed missing space] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	8 months ago
Peter Maydell	4f2b82f604	target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat In commit `655659a74a` we fixed some bugs in the encoding of the Debug Communications Channel registers, including that we were incorrectly exposing an AArch32 register at p14, 3, c0, c5, 0. Unfortunately removing a register is a break of forwards migration compatibility for TCG, because we will fail the migration if the source QEMU passes us a cpreg which the destination QEMU does not have. We don't have a mechanism for saying "it's OK to ignore this sysreg in the inbound data", so for the 10.1 release reinstate the incorrect AArch32 register. (We probably have had other cases in the past of breaking migration compatibility like this, but we didn't notice because we didn't test and in any case not that many people care about TCG migration compatibility. KVM migration compat is not affected because for KVM we treat the kernel as the source of truth for what system registers are present.) Fixes: `655659a74a` ("target/arm: Correct encoding of Debug Communications Channel registers") Reported-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250731134338.250203-1-peter.maydell@linaro.org	8 months ago
Peter Maydell	e7b77e681f	hw/display/framebuffer: Add cast to force 64x64 multiply In framebuffer_update_display(), Coverity complains because we multiply two values of type 'int' (which will be done as a 32x32 multiply and so in theory might overflow) and then add the result to a ram_addr_t, which can be 64 bits. 4GB framebuffers are not plausible anyway, but keep Coverity happy by adding casts which force these multiplies to be done as 64x64. Coverity: CID 1487248 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-id: 20250710174312.1313177-1-peter.maydell@linaro.org	9 months ago
Zenghui Yu	b10bd4bd17	hw/intc/arm_gicv3_kvm: Write all 1's to clear enable/active KVM's userspace access interface to the GICD enable and active bits is via set/clear register pairs which implement the hardware's "write 1s to the clear register to clear the 0 bits, and write 1s to the set register to set the 1 bits" semantics. We didn't get this right, because we were writing 0 to the clear register. Writing 0 to GICD_IC{ENABLE,ACTIVE}R architecturally has no effect on interrupt status (all writes are simply ignored by KVM) and doesn't comply with the intention of "first write to the clear-reg to clear all bits". Write all 1's to actually clear the enable/active status. This didn't have any adverse effects on migration because there we start with a clean VM state; it would be guest-visible when doing a system reset, but since Linux always cleans up the register state of the GIC during bootup before it enables it most users won't have run into a problem here. Cc: qemu-stable@nongnu.org Fixes: `367b9f527b` ("hw/intc/arm_gicv3_kvm: Implement get/put functions") Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Message-id: 20250729161650.43758-3-zenghui.yu@linux.dev Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	8 months ago
Zenghui Yu	a0555e36fc	hw/intc/arm_gicv3_kvm: Remove writes to ICPENDR registers As per the arm-vgic-v3 kernel doc [1]: Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have RAZ/WI semantics, meaning that reads always return 0 and writes are always ignored. The state behind these registers (both 0 and 1 bits) is written by writing to the GICD_ISPENDR and GICR_ISPENDR0 registers, unlike some of the other set/clear register pairs. Remove the useless writes to ICPENDR registers in kvm_arm_gicv3_put(). [1] https://docs.kernel.org/virt/kvm/devices/arm-vgic-v3.html Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Message-id: 20250729161650.43758-2-zenghui.yu@linux.dev Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	8 months ago
Alex Richardson	cd9f752fee	target/arm: add support for 64-bit PMCCNTR in AArch32 mode In the PMUv3, a new AArch32 64-bit (MCRR/MRRC) accessor for the PMCCNTR was added. In QEMU we forgot to implement this, so only provide the 32-bit accessor. Since we have a 64-bit PMCCNTR sysreg for AArch64, adding the 64-bit AArch32 version is easy. We add the PMCCNTR to the v8_cp_reginfo because PMUv3 was added in the ARMv8 architecture. This is consistent with how we handle the existing PMCCNTR support, where we always implement it for all v7 CPUs. This is arguably something we should clean up so it is gated on ARM_FEATURE_PMU and/or an ID register check for the relevant PMU version, but we should do that as its own tidyup rather than being inconsistent between this PMCCNTR accessor and the others. Since the register name is the same as the 32-bit PMCCNTR, we set ARM_CP_NO_GDB on the 32-bit one to avoid generating an invalid GDB XML. See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en Note for potential backporting: * this code in cpregs-pmu.c will be in helper.c on stable branches that don't have commit `ae2086426d` Cc: qemu-stable@nongnu.org Signed-off-by: Alex Richardson <alexrichardson@google.com> Message-id: 20250725170136.145116-1-alexrichardson@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	8 months ago
Stefan Hajnoczi	4e06566dbd	Third RISC-V PR for 10.1 * Fix pmp range wraparound on zero * Update FADT and MADT versions in ACPI tables * Fix target register read when source is inactive * Add riscv_hwprobe entry to linux-user strace list * Do not call GETPC() in check_ret_from_m_mode() * Revert "Generate strided vector loads/stores with tcg nodes." * Fix exception type when VU accesses supervisor CSRs * Restrict mideleg/medeleg/medelegh access to S-mode harts * Restrict midelegh access to S-mode harts -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmiJbsUACgkQr3yVEwxT gBPXCxAAhgcGh/mbdk/DZM4Gx9WqbfjU/1jZR9FCld9im3GLtJfq7IdEcsUZzpNb E4sp49lr99qoogKhh3exYhBl0/t0WBoT5mtHNPLFRD3LX2gw6EFQWnD8FN1D//sO QvyulomYbmI/Ywf5n5SszF4BpOKh7nyUEZBp4PU6vLT5btsZheSoTyCypH4a7KAy GMFNO+O1k6NEwkUqqiIb9Pg8NOp/R3TlNWOjS8fwqyPSU/F8/pzehJQu4WOMAyM8 eGvqCZiwTg5CcLZfhQZ8dmqJ2qqI44FEzPjyq/Woq5hDmGDMl1iYhgjX5Ozy0X5j m4Q+ZH0KIr18EkUD9z4fJbcQAMIm/2b90TShYon6+JYXX8DI8gUCvtg2vgsPAlnS M6vgNT25qY8QZa/FbUGcP2+96AlaqX11jUou+TMuJMSr036gTP7gXux5hqYDrd0B 4WL1XPcfNZshK5+LAQ+2uwQ9JcKlEaw/mkZHvHgYN7a03UynjCn0oFZtTYvaB4Qx Du8Rm9VPlLp3e25VmOiObYyq2Cf6sQXlWomKLJbvfCj217ZXvjOwEjj8hBcg3zJ/ 6ix/wmDic+YtwmYE7EaGZaExpV5ZjZog61jzMziilZrCJarAoguq0P9tThXGtViX TqQcn1V391EfVZYbS3JBO08xmkkX2k7Ia//Th35nByLt7zzrRbs= =pKhf -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging Third RISC-V PR for 10.1 * Fix pmp range wraparound on zero * Update FADT and MADT versions in ACPI tables * Fix target register read when source is inactive * Add riscv_hwprobe entry to linux-user strace list * Do not call GETPC() in check_ret_from_m_mode() * Revert "Generate strided vector loads/stores with tcg nodes." * Fix exception type when VU accesses supervisor CSRs * Restrict mideleg/medeleg/medelegh access to S-mode harts * Restrict midelegh access to S-mode harts # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmiJbsUACgkQr3yVEwxT # gBPXCxAAhgcGh/mbdk/DZM4Gx9WqbfjU/1jZR9FCld9im3GLtJfq7IdEcsUZzpNb # E4sp49lr99qoogKhh3exYhBl0/t0WBoT5mtHNPLFRD3LX2gw6EFQWnD8FN1D//sO # QvyulomYbmI/Ywf5n5SszF4BpOKh7nyUEZBp4PU6vLT5btsZheSoTyCypH4a7KAy # GMFNO+O1k6NEwkUqqiIb9Pg8NOp/R3TlNWOjS8fwqyPSU/F8/pzehJQu4WOMAyM8 # eGvqCZiwTg5CcLZfhQZ8dmqJ2qqI44FEzPjyq/Woq5hDmGDMl1iYhgjX5Ozy0X5j # m4Q+ZH0KIr18EkUD9z4fJbcQAMIm/2b90TShYon6+JYXX8DI8gUCvtg2vgsPAlnS # M6vgNT25qY8QZa/FbUGcP2+96AlaqX11jUou+TMuJMSr036gTP7gXux5hqYDrd0B # 4WL1XPcfNZshK5+LAQ+2uwQ9JcKlEaw/mkZHvHgYN7a03UynjCn0oFZtTYvaB4Qx # Du8Rm9VPlLp3e25VmOiObYyq2Cf6sQXlWomKLJbvfCj217ZXvjOwEjj8hBcg3zJ/ # 6ix/wmDic+YtwmYE7EaGZaExpV5ZjZog61jzMziilZrCJarAoguq0P9tThXGtViX # TqQcn1V391EfVZYbS3JBO08xmkkX2k7Ia//Th35nByLt7zzrRbs= # =pKhf # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Jul 2025 21:00:53 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu: target/riscv: Restrict midelegh access to S-mode harts target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts target/riscv: Fix exception type when VU accesses supervisor CSRs riscv: Revert "Generate strided vector loads/stores with tcg nodes." target/riscv: do not call GETPC() in check_ret_from_m_mode() linux-user/strace.list: add riscv_hwprobe entry intc/riscv_aplic: Fix target register read when source is inactive tests/data/acpi/riscv64: Update expected FADT and MADT hw/riscv/virt-acpi-build.c: Update FADT and MADT versions bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes target/riscv: Fix pmp range wraparound on zero Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Jay Chang	86bc3a0abf	target/riscv: Restrict midelegh access to S-mode harts RISC-V AIA Spec states: "For a machine-level environment, extension Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels. For a supervisor-level environment, extension Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com> Message-ID: <20250701030021.99218-3-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	9 months ago
Jay Chang	e443ba0336	target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts RISC-V Privileged Spec states: "In harts with S-mode, the medeleg and mideleg registers must exist, and setting a bit in medeleg or mideleg will delegate the corresponding trap , when occurring in S-mode or U-mode, to the S-mode trap handler. In harts without S-mode, the medeleg and mideleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com> Message-ID: <20250701030021.99218-2-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	9 months ago
Xu Lu	30ef718423	target/riscv: Fix exception type when VU accesses supervisor CSRs When supervisor CSRs are accessed from VU-mode, a virtual instruction exception should be raised instead of an illegal instruction. Fixes: `c1fbcecb3a` (target/riscv: Fix csr number based privilege checking) Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> Reviewed-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Message-ID: <20250708060720.7030-1-luxu.kernel@bytedance.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	9 months ago
Daniel Henrique Barboza	09ac27a9b5	riscv: Revert "Generate strided vector loads/stores with tcg nodes." This reverts commit `28c12c1f2f`. As reported in [1] this commit is breaking Linux vector code, and although a simpler reproducer was provided, the fix itself isn't trivial due to the amount and the nature of the changes. And we really do not want to keep Linux broken while we work on it. The revert will fix Linux and will give us time to do a proper fix. [1] https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02525.html Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Eric Biggers <ebiggers@kernel.org> Message-ID: <20250710100525.372985-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	9 months ago
Daniel Henrique Barboza	16aa7771af	target/riscv: do not call GETPC() in check_ret_from_m_mode() GETPC() should always be called from the top level helper, e.g. the first helper that is called by the translation code. We stopped doing that in commit `3157a553ec`, and then we introduced problems when unwinding the exceptions being thrown by helper_mret(), as reported by [1]. Call GETPC() at the top level helper and pass the value along. [1] https://gitlab.com/qemu-project/qemu/-/issues/3020 Suggested-by: Richard Henderson <richard.henderson@linaro.org> Fixes: `3157a553ec` ("target/riscv: Add Smrnmi mnret instruction") Closes: https://gitlab.com/qemu-project/qemu/-/issues/3020 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250714133739.1248296-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	9 months ago
Daniel Henrique Barboza	e111ffe48b	linux-user/strace.list: add riscv_hwprobe entry We're missing a strace entry for riscv_hwprobe, and using -strace will report it as "Unknown syscall 258". After this patch we'll have: $ ./build/qemu-riscv64 -strace test_mutex_riscv 110182 riscv_hwprobe(0x7f207efdc700,1,0,0,0,0) = 0 110182 brk(NULL) = 0x0000000000082000 (...) Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250728170633.113384-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	8 months ago
Yang Jialong	b6f1244678	intc/riscv_aplic: Fix target register read when source is inactive The RISC-V Advanced interrupt Architecture: 4.5.16. Interrupt targets: If interrupt source i is inactive in this domain, register target[i] is read-only zero. Signed-off-by: Yang Jialong <z_bajeer@yeah.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250728055114.252024-1-z_bajeer@yeah.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	8 months ago
Sunil V L	f3c8b7767f	tests/data/acpi/riscv64: Update expected FADT and MADT Update the expected tables for the version change. /* * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) / [000h 0000 004h] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 004h] Table Length : 00000114 [008h 0008 001h] Revision : 06 -[009h 0009 001h] Checksum : 13 +[009h 0009 001h] Checksum : 12 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] FACS Address : 00000000 [028h 0040 004h] DSDT Address : 00000000 [02Ch 0044 001h] Model : 00 [02Dh 0045 001h] PM Profile : 00 [Unspecified] [02Eh 0046 002h] SCI Interrupt : 0000 [030h 0048 004h] SMI Command Port : 00000000 [034h 0052 001h] ACPI Enable Value : 00 [035h 0053 001h] ACPI Disable Value : 00 [036h 0054 001h] S4BIOS Command : 00 [037h 0055 001h] P-State Control : 00 @@ -86,33 +86,33 @@ Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 1 Low Power S0 Idle (V5) : 0 [074h 0116 00Ch] Reset Register : [Generic Address Structure] [074h 0116 001h] Space ID : 00 [SystemMemory] [075h 0117 001h] Bit Width : 00 [076h 0118 001h] Bit Offset : 00 [077h 0119 001h] Encoded Access Width : 00 [Undefined/Legacy] [078h 0120 008h] Address : 0000000000000000 [080h 0128 001h] Value to cause reset : 00 [081h 0129 002h] ARM Flags (decoded below) : 0000 PSCI Compliant : 0 Must use HVC for PSCI : 0 -[083h 0131 001h] FADT Minor Revision : 05 +[083h 0131 001h] FADT Minor Revision : 06 [084h 0132 008h] FACS Address : 0000000000000000 [...] / * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 004h] Table Length : 00000074 -[008h 0008 001h] Revision : 06 -[009h 0009 001h] Checksum : B4 +[008h 0008 001h] Revision : 07 +[009h 0009 001h] Checksum : B3 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [...] Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Message-ID: <20250724110350.452828-4-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	8 months ago
Sunil V L	a3b95362ce	hw/riscv/virt-acpi-build.c: Update FADT and MADT versions RISC-V support is added only in ACPI 6.6. According to the ACPI 6.6 specification, the minor version of the Fixed ACPI Description Table (FADT) should be 6, and the Multiple APIC Description Table (MADT) should use revision 7. So, update the RISC-V FADT and MADT to reflect correct versions. Update the code comments to reflect ACPI 6.6 version details. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Message-ID: <20250724110350.452828-3-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	8 months ago
Sunil V L	35d129399d	bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Message-ID: <20250724110350.452828-2-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	8 months ago
Vac Chen	77707bfdf8	target/riscv: Fix pmp range wraparound on zero pmp_is_in_range() prefers to match addresses within the interval [start, end]. To archieve this, pmpaddrX is decremented during the end address update. In TOR mode, a rule is ignored if its start address is greater than or equal to its end address. However, if pmpaddrX is set to 0, this decrement operation causes the calulated end address to wrap around to UINT_MAX. In this scenario, the address guard for this PMP entry would become ineffective. This patch addresses the issue by moving the guard check earlier, preventing the problematic wraparound when pmpaddrX is zero. Signed-off-by: Vac Chen <vacantron@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250706065554.42953-1-vacantron@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	9 months ago
Stefan Hajnoczi	9b80226ece	Update version for the v10.1.0-rc1 release Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	7a3abf7243	QAPI patches for 2025-07-29 -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmiIxAYSHGFybWJydUBy ZWRoYXQuY29tAAoJEDhwtADrkYZTmvEP/iYxb+1mNWLimDE/Q0nO89KDBvxLMsIr +Z/dB4GTffvfITX5bxlzf4CaivCBGxoV02kFnzhYVHNYZD9CFA7pPwKySg2kpOeh NIrR7OAI9/W7H+uOyZslU78HhFSoKSfeYWssXnRyrXKPFXwyO7eJacXY9YlMz2ap A1aQT843I60ldsW2/7oJ4wy/TwHnIwXwFyBXSuKq7447LpospXDXdNdaghEjxTsQ LkYKcmSVgonCGnZf43OyiITdkXRdttZUoSQTMKJWBzg2UZkikqDeUt67t3XYkjWk irvBnF0lt2oEbmyeuWNciEkI5/fyoENh0bNeLWDAKwEqDf2Dc3s19/SYV8y8N3pY UuJRPSeJ4m2cNGv/5SU8C72GMMxcP50Usrk9JvJ1ZhS7C/rWXENC1CTm4uZDkJ0t TJt0KC4lFW0wDoXMQv1zWSXqri6+n7Ts1iYsHq5jEpDPNvQB7TGHA1VN2FBipN2d FXFCKWfpIxYbXsAh32mAUe1wiEkZTQdBZ/ZFFNRupMgg34B7X9gGg0kUBY161IfJ x2N9/508kgCWppz5AR8Y3sniLGtWv0KMwfQcLK1392w8AcuhVSnmejY3SUaXlmGE JRTqnMgo1EvS/7+We5OV1NuAbHbsk/bQUeN4ZDAkzQFAQscJvCQD/uD7jzY4xBFr 4LhegQM8eG57 =Opw0 -----END PGP SIGNATURE----- Merge tag 'pull-qapi-2025-07-29' of https://repo.or.cz/qemu/armbru into staging QAPI patches for 2025-07-29 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmiIxAYSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTmvEP/iYxb+1mNWLimDE/Q0nO89KDBvxLMsIr # +Z/dB4GTffvfITX5bxlzf4CaivCBGxoV02kFnzhYVHNYZD9CFA7pPwKySg2kpOeh # NIrR7OAI9/W7H+uOyZslU78HhFSoKSfeYWssXnRyrXKPFXwyO7eJacXY9YlMz2ap # A1aQT843I60ldsW2/7oJ4wy/TwHnIwXwFyBXSuKq7447LpospXDXdNdaghEjxTsQ # LkYKcmSVgonCGnZf43OyiITdkXRdttZUoSQTMKJWBzg2UZkikqDeUt67t3XYkjWk # irvBnF0lt2oEbmyeuWNciEkI5/fyoENh0bNeLWDAKwEqDf2Dc3s19/SYV8y8N3pY # UuJRPSeJ4m2cNGv/5SU8C72GMMxcP50Usrk9JvJ1ZhS7C/rWXENC1CTm4uZDkJ0t # TJt0KC4lFW0wDoXMQv1zWSXqri6+n7Ts1iYsHq5jEpDPNvQB7TGHA1VN2FBipN2d # FXFCKWfpIxYbXsAh32mAUe1wiEkZTQdBZ/ZFFNRupMgg34B7X9gGg0kUBY161IfJ # x2N9/508kgCWppz5AR8Y3sniLGtWv0KMwfQcLK1392w8AcuhVSnmejY3SUaXlmGE # JRTqnMgo1EvS/7+We5OV1NuAbHbsk/bQUeN4ZDAkzQFAQscJvCQD/uD7jzY4xBFr # 4LhegQM8eG57 # =Opw0 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Jul 2025 08:52:22 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2025-07-29' of https://repo.or.cz/qemu/armbru: MAINTAINERS: Cover docs/devel/qapi-domain.rst properly docs/qapi-domain: Fix typos tests/qapi-schema: Bury dead test case doc-non-first-section qapi/accelerator: Fix markup of heading qapi: Add more cross-references Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	e52966be20	Misc HW patches - Fix MIPS MVPControl.EVP update - Fix qxl_unpack_chunks() chunk size calculation - Fix Cadence GEM register mask initialization - Fix AddressSpaceDispatch use after free - Fix building npcm7xx/npcm8xx bootroms - Include missing headers -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmiItwoACgkQ4+MsLN6t wN5OGw//SFNgCvin6ic3H+QoUNwrRAH7eFuVfAKSKGopSqWf19imHy8rZl/8DYeo WsCRUPkVcAGzgRHZFc+8VYGdSR5GW7AulSzHh7fGQ8EFNunu3cnGsDflVV6UjgRP wnCfFuyrnyGfXVWkkjWYqCLI78AR0hB0Gp1E5nR4ZwGM4OhatDjKpYxWlRZbnjSA pBArLw8eKUrq90RekVpsa15oF9eMU89HzDBfxYvk0tb4//BWBiWfgQ+cz7j9f1wC wtTOEQ2BTkvGhqhe9VacV4YpQDXE9comlTked48GzHGqsAgp55NcB6FAR438qiG1 3z7LpL4LQn39+oC0S9cR2OahIGFEveOvGJoj014Iny4QR/ghNzt3F2Z9tgPISIKj MhJ0Bu7K7X+RWikY9xiAu24ORrRd5O6EItgLsl+24vkySOKODZ85WdKtIx0DQ7Yj rvRTkFDs/3K3kzMfZ20Jpeu7Bc74qUgsii27rivM/9rN0R9w+Br8MWLe0QSFalUe 08NoRZMVuSPCWlvJGGb0SRYpVAZsZaE9Ucd8wQzEcjHdVu0/+7KQfACXrJ09Y8sq lTgytCL8gO2jSEAh4cN/Ds1uBc8X5KKL32hNzRgddZVujqAuriBjAYEEk1pc7qe4 yBxVkhASOpY53b1O2UqanajT2vY4T3JX5w+Jqn1HubZ/ZUwcK64= =H2Ie -----END PGP SIGNATURE----- Merge tag 'hw-misc-20250729' of https://github.com/philmd/qemu into staging Misc HW patches - Fix MIPS MVPControl.EVP update - Fix qxl_unpack_chunks() chunk size calculation - Fix Cadence GEM register mask initialization - Fix AddressSpaceDispatch use after free - Fix building npcm7xx/npcm8xx bootroms - Include missing headers # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmiItwoACgkQ4+MsLN6t # wN5OGw//SFNgCvin6ic3H+QoUNwrRAH7eFuVfAKSKGopSqWf19imHy8rZl/8DYeo # WsCRUPkVcAGzgRHZFc+8VYGdSR5GW7AulSzHh7fGQ8EFNunu3cnGsDflVV6UjgRP # wnCfFuyrnyGfXVWkkjWYqCLI78AR0hB0Gp1E5nR4ZwGM4OhatDjKpYxWlRZbnjSA # pBArLw8eKUrq90RekVpsa15oF9eMU89HzDBfxYvk0tb4//BWBiWfgQ+cz7j9f1wC # wtTOEQ2BTkvGhqhe9VacV4YpQDXE9comlTked48GzHGqsAgp55NcB6FAR438qiG1 # 3z7LpL4LQn39+oC0S9cR2OahIGFEveOvGJoj014Iny4QR/ghNzt3F2Z9tgPISIKj # MhJ0Bu7K7X+RWikY9xiAu24ORrRd5O6EItgLsl+24vkySOKODZ85WdKtIx0DQ7Yj # rvRTkFDs/3K3kzMfZ20Jpeu7Bc74qUgsii27rivM/9rN0R9w+Br8MWLe0QSFalUe # 08NoRZMVuSPCWlvJGGb0SRYpVAZsZaE9Ucd8wQzEcjHdVu0/+7KQfACXrJ09Y8sq # lTgytCL8gO2jSEAh4cN/Ds1uBc8X5KKL32hNzRgddZVujqAuriBjAYEEk1pc7qe4 # yBxVkhASOpY53b1O2UqanajT2vY4T3JX5w+Jqn1HubZ/ZUwcK64= # =H2Ie # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Jul 2025 07:56:58 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250729' of https://github.com/philmd/qemu: hw/display/sm501: fix missing error-report.h roms/Makefile: fix npcmNxx_bootrom build rules system/physmem: fix use-after-free with dispatch hw/xen/passthrough: add missing error-report include hw/net/cadence_gem: fix register mask initialization migration: rename target.c to vfio.c hw/vfio/vfio-migration: Remove unnecessary 'qemu/typedefs.h' include hw/display/qxl-render: fix qxl_unpack_chunks() chunk size calculation target/mips: Only update MVPControl.EVP bit if executed by master VPE Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	0ae375ab08	vfio queue: * Fixed regression introduced by the `use-legacy-x86-rom` property * Fixed regressions on IGD passthrough in legacy mode * Fixed region mappings of sub-page BARs after CPR * Removed build of SEV on 32-bit hosts -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmiIaXIACgkQUaNDx8/7 7KHEUw//S/9+Aw7sHI0dLvYLLxMUfoDHY2B7nx/o3EgDMc3we4L19+t9d2RTxsc0 QLz1wufhWn4gGIrb46fwqaU1ggu9cHi0o0E57cU+ZeADe/H9YRdFQ1q88yUzBARd /exYAMV9L9NejzA/gvJDr2pZgf5ZZGY8H2MoiYw21z5nGJXlCS+1kXah7rZPHRcu NEPw9jqab78jvHoFK1L1EaRCPN/qTaU8XGCFguDP0icFZCGnu4pIMHHQC6Btcjft 2k5FDkQ9bzYqpq9W0KLimREBCnhmvBnCVSG/KTf/gsU222anGGgS8+80OABG7xrZ 6LjFsBor2vKRhZ1JsL21BANg7M9iLPe3CB8KOgNdWl+RIkNfbUvt/tOqlAQgw9EI JN7g9Ru1B0JVg18SHkTQ6/5eiWxnYRZvQA3R0BJXF23f2qqUtCm9VsQFUfYppc92 Ci/hEtCXej8HoiJFK4gUHLYKRtk4DGbpiWgx1FYLid0ks5I+31m6x/PUMSvUbJez oeKv5oCjvl3ORGrjpiDSA2O3gIEiMSru6jejN0RKEeRpSWOMcEsGPL7nySJaZElR PrR/Cw+n4brTTIwUw7VnpeJnQ+XQbxD6wEzcDB7ZZ+gVs7BvmMT2LeDHzhPcaJuf vDsTSss+YBSDCC8TCmcWPGOQB5SHPRNO/5aMPyYLulfa+VnHQmY= =kKby -----END PGP SIGNATURE----- Merge tag 'pull-vfio-20250729' of https://github.com/legoater/qemu into staging vfio queue: * Fixed regression introduced by the `use-legacy-x86-rom` property * Fixed regressions on IGD passthrough in legacy mode * Fixed region mappings of sub-page BARs after CPR * Removed build of SEV on 32-bit hosts # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmiIaXIACgkQUaNDx8/7 # 7KHEUw//S/9+Aw7sHI0dLvYLLxMUfoDHY2B7nx/o3EgDMc3we4L19+t9d2RTxsc0 # QLz1wufhWn4gGIrb46fwqaU1ggu9cHi0o0E57cU+ZeADe/H9YRdFQ1q88yUzBARd # /exYAMV9L9NejzA/gvJDr2pZgf5ZZGY8H2MoiYw21z5nGJXlCS+1kXah7rZPHRcu # NEPw9jqab78jvHoFK1L1EaRCPN/qTaU8XGCFguDP0icFZCGnu4pIMHHQC6Btcjft # 2k5FDkQ9bzYqpq9W0KLimREBCnhmvBnCVSG/KTf/gsU222anGGgS8+80OABG7xrZ # 6LjFsBor2vKRhZ1JsL21BANg7M9iLPe3CB8KOgNdWl+RIkNfbUvt/tOqlAQgw9EI # JN7g9Ru1B0JVg18SHkTQ6/5eiWxnYRZvQA3R0BJXF23f2qqUtCm9VsQFUfYppc92 # Ci/hEtCXej8HoiJFK4gUHLYKRtk4DGbpiWgx1FYLid0ks5I+31m6x/PUMSvUbJez # oeKv5oCjvl3ORGrjpiDSA2O3gIEiMSru6jejN0RKEeRpSWOMcEsGPL7nySJaZElR # PrR/Cw+n4brTTIwUw7VnpeJnQ+XQbxD6wEzcDB7ZZ+gVs7BvmMT2LeDHzhPcaJuf # vDsTSss+YBSDCC8TCmcWPGOQB5SHPRNO/5aMPyYLulfa+VnHQmY= # =kKby # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Jul 2025 02:25:54 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20250729' of https://github.com/legoater/qemu: vfio/igd: Fix VGA regions are not exposed in legacy mode vfio/igd: Require host VGA decode for legacy mode vfio: fix sub-page bar after cpr i386: Build SEV only for 64-bit target hw/i386: Fix 'use-legacy-x86-rom' property compatibility Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Markus Armbruster	a95b3c0ad8	MAINTAINERS: Cover docs/devel/qapi-domain.rst properly Section QAPI already covers it, and that's fine. It's missing from "Sphinx documentation configuration and build machinery". Add it there. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250729091642.3513895-3-armbru@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> [Improved commit message]	8 months ago
Markus Armbruster	a14f6d3288	docs/qapi-domain: Fix typos Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250729091642.3513895-2-armbru@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>	8 months ago
Markus Armbruster	1047cc2816	tests/qapi-schema: Bury dead test case doc-non-first-section The test passed when it was added. However, the commit adding it neglected to make Meson aware of it, so it never ran automatically. The test stopped making sense when we changed headings markup, and ceased to pass then. It should've been removed then. Do that now. Fixes: `6c10778826` (docs/sphinx: remove special parsing for freeform sections) Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250724091742.1950167-3-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>	8 months ago
Markus Armbruster	a3004697f7	qapi/accelerator: Fix markup of heading The docs generated for qapi/accelerator.json shows text "= Accelerators" instead of a heading. This is because the patch that added the heading crossed with the commit that changed heading markup (commit `6c10778826` "docs/sphinx: remove special parsing for freeform sections"). Fix the markup. Fixes: `18da42ee42` (qapi/accel: Move definitions related to accelerators in their own file) Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250724091742.1950167-2-armbru@redhat.com>	8 months ago
Markus Armbruster	d4d91ed42e	qapi: Add more cross-references We recently (merge commit `504632dcc6`) enclosed command and type names in `backquotes`, so they become links in generated HTML. Take care of a few we missed. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250717115751.3832597-1-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>	9 months ago
Clément Chigot	67e4808403	hw/display/sm501: fix missing error-report.h "qemu/error-report.h" was previously implicitly included. This is no longer the case following `012842c075`. However, the issue predates this change as `error-report.h` should have been included when the `warn_report` call was introduced. Fixes: `fa140b9562` ("hw/sm501: allow compiling without PIXMAN") Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250728090518.963573-1-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	8 months ago
Michael Tokarev	653a75a9d7	roms/Makefile: fix npcmNxx_bootrom build rules Since commit `70ce076fa6`, the actual rom source dirs are subdirs of vbootrom/ submodule, not in top-level of it. Fixes: `70ce076fa6` "roms: Update vbootrom to 1287b6e" Fixes: `269b7effd9` ("pc-bios: Add NPCM8XX vBootrom") Cc: qemu-stable@nongnu.org Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250727215511.807880-1-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	8 months ago
Pierrick Bouvier	2865bf1c57	system/physmem: fix use-after-free with dispatch A use-after-free bug was reported when booting a Linux kernel during the pci setup phase. It's quite hard to reproduce (needs smp, and favored by having several pci devices with BAR and specific Linux config, which is Debian default one in this case). After investigation (see the associated bug ticket), it appears that, under specific conditions, we might access a cached AddressSpaceDispatch that was reclaimed by RCU thread meanwhile. In the Linux boot scenario, during the pci phase, memory region are destroyed/recreated, resulting in exposition of the bug. The core of the issue is that we cache the dispatch associated to current cpu in cpu->cpu_ases[asidx].memory_dispatch. It is updated with tcg_commit, which runs asynchronously on a given cpu. At some point, we leave the rcu critial section, and the RCU thread starts reclaiming it, but tcg_commit is not yet invoked, resulting in the use-after-free. It's not the first problem around this area, and commit `0d58c66068` [1] ("softmmu: Use async_run_on_cpu in tcg_commit") already tried to address it. It did a good job, but it seems that we found a specific situation where it's not enough. This patch takes a simple approach: remove the cached value creating the issue, and make sure we always get the current mapping for address space, using address_space_to_dispatch(cpu->cpu_ases[asidx].as). It's equivalent to qatomic_rcu_read(&as->current_map)->dispatch; This is not really costly, we just need two dereferences, including one atomic (rcu) read, which is negligible considering we are already on mmu slow path anyway. Note that tcg_commit is still needed, as it's taking care of flushing TLB, removing previously mapped entries. Another solution would be to cache directly values under the dispatch (dispatch themselves are not ref counted), keep an active reference on associated memory section, and release it when appropriate (tricky). Given the time already spent debugging this area now and previously, I strongly prefer eliminating the root of the issue, instead of adding more complexity for a hypothetical performance gain. RCU is precisely used to ensure good performance when reading data, so caching is not as beneficial as it might seem IMHO. [1] `0d58c66068` Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3040 Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Message-ID: <20250724161142.2803091-1-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	8 months ago
Adam Williamson	014bb30d21	hw/xen/passthrough: add missing error-report include In commit `cfcacbab38` ("xen/passthrough: use gsi to map pirq when dom0 is PVH") an `error_report` was added to this file, but the corresponding include of `qemu/error-report.h` was missed. This only becomes apparent when building against Xen 4.20+ with trace backend log disabled. Fixes: `cfcacbab38` (xen/passthrough: use gsi to map pirq when dom0 is PVH) Signed-off-by: Adam Williamson <awilliam@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250717220207.171040-1-awilliam@redhat.com> [PMD: Improved commit description, added Fixes: tag] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	9 months ago
Luc Michel	2bfcd27e00	hw/net/cadence_gem: fix register mask initialization The gem_init_register_masks function was called at init time but it relies on the num-priority-queues property. Call it at realize time instead. Cc: qemu-stable@nongnu.org Fixes: `4c70e32f05` ("net: cadence_gem: Define access permission for interrupt registers") Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Message-ID: <20250716095432.81923-2-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	9 months ago
Pierrick Bouvier	b496a392fe	migration: rename target.c to vfio.c Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Message-ID: <20250725201729.17100-3-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	8 months ago
Philippe Mathieu-Daudé	962316a6a3	hw/vfio/vfio-migration: Remove unnecessary 'qemu/typedefs.h' include "qemu/typedefs.h" is already included by "qemu/osdep.h". Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250708085859.7885-3-philmd@linaro.org>	9 months ago
Michael Tokarev	8e8cb3b572	hw/display/qxl-render: fix qxl_unpack_chunks() chunk size calculation In case of multiple chunks, code in qxl_unpack_chunks() takes size of the wrong (next in the chain) chunk, instead of using current chunk size. This leads to wrong number of bytes being copied, and to crashes if next chunk size is larger than the current one. Based on the code by Gao Yong. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1628 Tested-by: Thaddeus Hogan <thaddeus@thogan.com> Tested-by: Vadim Zeitlin <vadim@wxwidgets.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250221134856.478806-1-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	e895095c78	target/mips: Only update MVPControl.EVP bit if executed by master VPE According to the 'MIPS MT Application-Speciﬁc Extension' manual: If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction. Modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit if executed on a master VPE. Cc: qemu-stable@nongnu.org Reported-by: Hansni Bu Buglink: https://bugs.launchpad.net/qemu/+bug/1926277 Fixes: `f249412c74` ("mips: Add MT halting and waking of VPEs") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-ID: <20210427133343.159718-1-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	5 years ago
Tomita Moeko	0db7e4cb62	vfio/igd: Fix VGA regions are not exposed in legacy mode In commit `a59d06305f` ("vfio/pci: Introduce x-pci-class-code option"), pci_register_vga() has been moved ouside of vfio_populate_vga(). As a result, IGD VGA ranges are no longer properly exposed to guest. To fix this, call pci_register_vga() after vfio_populate_vga() legacy mode. A wrapper function vfio_pci_config_register_vga() is introduced to handle it. Fixes: `a59d06305f` ("vfio/pci: Introduce x-pci-class-code option") Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250723160906.44941-3-tomitamoeko@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	8 months ago
Tomita Moeko	e0b33efe2a	vfio/igd: Require host VGA decode for legacy mode Commit `a59d06305f` ("vfio/pci: Introduce x-pci-class-code option") allows user to expose non-VGA IGD device as VGA controller to the guest. However, legacy mode requires host VGA range access. Check that GGC.IVD == 0 before enabling legacy mode to ensure IGD is a real VGA device claiming host VGA ranges. Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250723160906.44941-2-tomitamoeko@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	8 months ago
Steve Sistare	9751377c3a	vfio: fix sub-page bar after cpr Regions for sub-page BARs are normally mapped here, in response to the guest writing to PCI config space: vfio_pci_write_config() pci_default_write_config() pci_update_mappings() memory_region_add_subregion() vfio_sub_page_bar_update_mapping() ... vfio_dma_map() However, after CPR, the guest does not reconfigure the device and the code path above is not taken. To fix, in vfio_cpr_pci_post_load, call vfio_sub_page_bar_update_mapping for each sub-page BAR with a valid address. Fixes: `7e9f214113` ("vfio/container: restore DMA vaddr") Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Link: https://lore.kernel.org/qemu-devel/1752520890-223356-1-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	9 months ago
Cédric Le Goater	1dc1220fbd	i386: Build SEV only for 64-bit target Recent changes broke build on 32-bit host. Since there is no 32-bit support, restrict SEV to 64-bit. Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250716071554.377356-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	9 months ago
Cédric Le Goater	1ebdd2d926	hw/i386: Fix 'use-legacy-x86-rom' property compatibility Commit `350785d41d` ("ramfb: Add property to control if load the romfile") introduced the `use-legacy-x86-rom` property for the `vfio-pci-nohotplug` device, allowing control over VGA BIOS ROM loading. However, the property compatibility setting was incorrectly applied to the `vfio-pci` device instead, which causes all `vfio-pci` devices to fail to load. This change fixes the issue by ensuring the property is set on the correct device. Fixes: `d5fcf0d960` ("hw/i386: Add the ramfb romfile compatibility") Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Shaoqin Huang <shahuang@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250723062714.1245826-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	8 months ago
Stefan Hajnoczi	92c05be4df	QGA documentation patches for 2025-07-28 -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmiHY8cSHGFybWJydUBy ZWRoYXQuY29tAAoJEDhwtADrkYZTNgQP/3VZHHJtEqhGil+7ugTXffciJfBKZCkQ K1SpEjp0BQX3DPycLek3/gz39X0S8HpvNOkLPZ8qXpZVKRHK9Qoqc0ad+RuSqoGn 6O8prUQgfw1Cva4ZYB9Hg7hqKM1ABBv4wBJ1elNppYl9Gy0VZANkGTRnnf0226hZ Vf422Drwi4FR632r//teKC1DIDu1Gr23x4eZi6XIW2ooXWYShrmd8l/iYS6zERa4 f6PidxkRWtmTspVT/yNlzgxYezzdlGy3sSQ1YAZldVQBp4w7bnoQZjcdX8x55GJU 6CYwxf4rkHZ069uGVSM2bWJ1i47uVdu0ehIytKB69tGKdppspTwHGWpnfqH9k1lq W/S5PIF732IWw4EZhhnxB2UIDP2D4bAywoHEY6DJ67m2oJG+Jr7aSO7SRMGSBAL3 7YCcWDKAbgINjzagPHKWeatmklOYdnFKIRihyM5D1N26DZE1Tzxv+PztGMgSl0vv /mR3wR8Nhjt90QxW0yKuyjbXDopSBQhXSavPYnxV5QSp/elVJa6mxaFaahCv838t WX8DQIeLja0d7rLjVr4jqbWIa0Zj4G6yftxrUTiaAyAu8bVyDp4S3FBBfOg16x44 iPYk3BUM5YsxhgPPvahgHlD4vyPf8HvzJqn2CByW8a+iSF4upVGnSl2JU+olyC/+ MgFRqRgBbnJU =86XO -----END PGP SIGNATURE----- Merge tag 'pull-qga-2025-07-28' of https://repo.or.cz/qemu/armbru into staging QGA documentation patches for 2025-07-28 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmiHY8cSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTNgQP/3VZHHJtEqhGil+7ugTXffciJfBKZCkQ # K1SpEjp0BQX3DPycLek3/gz39X0S8HpvNOkLPZ8qXpZVKRHK9Qoqc0ad+RuSqoGn # 6O8prUQgfw1Cva4ZYB9Hg7hqKM1ABBv4wBJ1elNppYl9Gy0VZANkGTRnnf0226hZ # Vf422Drwi4FR632r//teKC1DIDu1Gr23x4eZi6XIW2ooXWYShrmd8l/iYS6zERa4 # f6PidxkRWtmTspVT/yNlzgxYezzdlGy3sSQ1YAZldVQBp4w7bnoQZjcdX8x55GJU # 6CYwxf4rkHZ069uGVSM2bWJ1i47uVdu0ehIytKB69tGKdppspTwHGWpnfqH9k1lq # W/S5PIF732IWw4EZhhnxB2UIDP2D4bAywoHEY6DJ67m2oJG+Jr7aSO7SRMGSBAL3 # 7YCcWDKAbgINjzagPHKWeatmklOYdnFKIRihyM5D1N26DZE1Tzxv+PztGMgSl0vv # /mR3wR8Nhjt90QxW0yKuyjbXDopSBQhXSavPYnxV5QSp/elVJa6mxaFaahCv838t # WX8DQIeLja0d7rLjVr4jqbWIa0Zj4G6yftxrUTiaAyAu8bVyDp4S3FBBfOg16x44 # iPYk3BUM5YsxhgPPvahgHlD4vyPf8HvzJqn2CByW8a+iSF4upVGnSl2JU+olyC/+ # MgFRqRgBbnJU # =86XO # -----END PGP SIGNATURE----- # gpg: Signature made Mon 28 Jul 2025 07:49:27 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qga-2025-07-28' of https://repo.or.cz/qemu/armbru: qga: Add cross-references qga: Rephrase return docs to avoid type name qga: Remove trivial "Returns:" sections qga: Fix guest-network-get-route return value documentation Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	20b28f58b4	documentation and test cleanups - improve clarity of user-mode docs - remove reference to TAP tarball - add new hypervisor test for aarch64 EL2 - reduce combinatorial explosion of plugin tests - make docker-all-test-cross more friendly to non-x86 hosts - expose unittests to sysv.args for embedded help -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmiFUdoACgkQ+9DbCVqe KkQn+Af/RpTh4XmIcqiLvXrygLWo8hSELS0gjIRZgAA8QyBmojZ+e13los3pzm2Z WWlQhh4T0OHgMtZCPPrP+XUc/QDgV3Pt41C1O6SWRwqD4v/7oWNNZz+pFra7x160 CLBJfcVuRKdFzuR1NZldR8LJufmAMnPnBwE+cV9SpBlGe/lvcLPPvjF0eXQnW1yP fWmNgf7VnLBPEQ3NQkliZ23Ku6p4yWDfJLfqgUAXe57Eom1PpDEaPlc+5UaYtAKs ee6Gk5CqVFUhIj0v50qBn1giLyaqaXyGn9yWiwiNDL/qVV1v+DK7LNt5B0bTXCfd X1KTwpJJdbzmcDftrAq+oacaeXryIA== =Sxa/ -----END PGP SIGNATURE----- Merge tag 'pull-10.1-rc1-maintainer-260725-1' of https://gitlab.com/stsquad/qemu into staging documentation and test cleanups - improve clarity of user-mode docs - remove reference to TAP tarball - add new hypervisor test for aarch64 EL2 - reduce combinatorial explosion of plugin tests - make docker-all-test-cross more friendly to non-x86 hosts - expose unittests to sysv.args for embedded help # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmiFUdoACgkQ+9DbCVqe # KkQn+Af/RpTh4XmIcqiLvXrygLWo8hSELS0gjIRZgAA8QyBmojZ+e13los3pzm2Z # WWlQhh4T0OHgMtZCPPrP+XUc/QDgV3Pt41C1O6SWRwqD4v/7oWNNZz+pFra7x160 # CLBJfcVuRKdFzuR1NZldR8LJufmAMnPnBwE+cV9SpBlGe/lvcLPPvjF0eXQnW1yP # fWmNgf7VnLBPEQ3NQkliZ23Ku6p4yWDfJLfqgUAXe57Eom1PpDEaPlc+5UaYtAKs # ee6Gk5CqVFUhIj0v50qBn1giLyaqaXyGn9yWiwiNDL/qVV1v+DK7LNt5B0bTXCfd # X1KTwpJJdbzmcDftrAq+oacaeXryIA== # =Sxa/ # -----END PGP SIGNATURE----- # gpg: Signature made Sat 26 Jul 2025 18:08:26 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-10.1-rc1-maintainer-260725-1' of https://gitlab.com/stsquad/qemu: tests/functional: expose sys.argv to unittest.main tests/docker: handle host-arch selection for all-test-cross tests/docker: add --arch-only to qemu deps for all-test-cross tests/tcg: reduce the number of plugin tests combinations configure: expose PYTHON to test/tcg/config-host.mak tests/tcg: don't include multiarch tests if not supported tests/tcg: remove ADDITIONAL_PLUGINS_TESTS tests/tcg: skip libsyscall.so on softmmu tests tests/functional: add hypervisor test for aarch64 docs/user: expand section on threading docs/user: slightly reword section on system calls docs/user: clean up headings docs/system: reword the TAP notes to remove tarball ref docs/user: clarify user-mode expects the same OS Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	bf7da34454	linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals linux-user/aarch64: Support TPIDR2_MAGIC signal frame record linux-user/aarch64: Support ZT_MAGIC signal frame record -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmiF1rwdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV935wf7BXGiD3m1MfLofofa w5/j4AjKw2sNAS3gVhmu9+BKKdctvNDxpNv4vx79j58iTuPCpi6roQ3vOEJWR0Vb 0UdJc/vNvFrXWLTW+W5nncKjCYZeTgSbWy3xwfnR3u4fk8YkUbGjVZ9TAgXl3dA1 NGagGqrlCqJpDYxbRWRIhXE+dF5zfNqU4gDTLG+C8xCN/gT7TkDIOU9sNb2uu1PC eI/SplpZYBDpdzpjko35peyq0tqUJrYT6P1MMjQckGpnKTSMynQmYvKVkloALRpW Zx3mBu9cWl77D57Fw4AijEiuUGhN0kZB12gH9VRp29rlTRr/MR4Y0seOU6XDc341 eGe5pg== =avvX -----END PGP SIGNATURE----- Merge tag 'pull-lu-20250726' of https://gitlab.com/rth7680/qemu into staging linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals linux-user/aarch64: Support TPIDR2_MAGIC signal frame record linux-user/aarch64: Support ZT_MAGIC signal frame record # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmiF1rwdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV935wf7BXGiD3m1MfLofofa # w5/j4AjKw2sNAS3gVhmu9+BKKdctvNDxpNv4vx79j58iTuPCpi6roQ3vOEJWR0Vb # 0UdJc/vNvFrXWLTW+W5nncKjCYZeTgSbWy3xwfnR3u4fk8YkUbGjVZ9TAgXl3dA1 # NGagGqrlCqJpDYxbRWRIhXE+dF5zfNqU4gDTLG+C8xCN/gT7TkDIOU9sNb2uu1PC # eI/SplpZYBDpdzpjko35peyq0tqUJrYT6P1MMjQckGpnKTSMynQmYvKVkloALRpW # Zx3mBu9cWl77D57Fw4AijEiuUGhN0kZB12gH9VRp29rlTRr/MR4Y0seOU6XDc341 # eGe5pg== # =avvX # -----END PGP SIGNATURE----- # gpg: Signature made Sun 27 Jul 2025 03:35:24 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-lu-20250726' of https://gitlab.com/rth7680/qemu: linux-user/aarch64: Support ZT_MAGIC signal frame record linux-user/aarch64: Support TPIDR2_MAGIC signal frame record linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	061758d7b8	trivial patches for 2025-07-25 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmiDqDsACgkQgqpKJDse lHitSg//Uy6gv6Xk+Q4WW220ik9Mr0U00bJmOFiD14I3S1z7D/L8ZvjZlA85WpZs XhSgXzHW2qFKDAz4suEh/u4p6fboYYf0r/+QiK0Qxumup23ClcClWRBQ14GVp3T4 JXzojzJtzYTCvr0LixNHGai8ZNr8D5XsTeKH4noH9sgDC0uRS2fD20GD5AnyJiNS sdAlfFLJM8yLSE+pgwUr06m3s/m+wn+xH5wMVr4vUzprgXxOubz4CkOyoPMIsOxZ 679CPfsfYueEjZ6EJJHCgLwlQIXwTEfPHWkw3GMHdgHD3qbezXH4HUanRX8zK/k1 KeDj/goeTYQuevsLss30HgxGaoEJXAS8pPmyP7biDrxfpN+aJRIJXVZbXa0bgdFW RF6CT+kfZCyC2/kAdUlbVNvUfgsfANWD7toIRbRwcyk7awg1jUJElEbEx17DMqr3 nCLzfFiS09Y/9c7rtLfTwyPW1k6XAr9fykVziup5KeOEQaetpPTtvV6DFqcvQ57p OdwMZytY+f8KKctV+X0XckmDVRQu9I9/FaWsQT82sXUSI21apAwl22Vh3mRMGkHv eHSa+I9KQwFpXEh/LE9PYWnQBR95DIuI1u2TP1tyXdu53/seUFmTUQ6JHeQynNJ3 E25yxYzxRXwtfTINo+YWzORVe5Gie/aWek8AnC3GSQ2yaJXBCH4= =0G1o -----END PGP SIGNATURE----- Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging trivial patches for 2025-07-25 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmiDqDsACgkQgqpKJDse # lHitSg//Uy6gv6Xk+Q4WW220ik9Mr0U00bJmOFiD14I3S1z7D/L8ZvjZlA85WpZs # XhSgXzHW2qFKDAz4suEh/u4p6fboYYf0r/+QiK0Qxumup23ClcClWRBQ14GVp3T4 # JXzojzJtzYTCvr0LixNHGai8ZNr8D5XsTeKH4noH9sgDC0uRS2fD20GD5AnyJiNS # sdAlfFLJM8yLSE+pgwUr06m3s/m+wn+xH5wMVr4vUzprgXxOubz4CkOyoPMIsOxZ # 679CPfsfYueEjZ6EJJHCgLwlQIXwTEfPHWkw3GMHdgHD3qbezXH4HUanRX8zK/k1 # KeDj/goeTYQuevsLss30HgxGaoEJXAS8pPmyP7biDrxfpN+aJRIJXVZbXa0bgdFW # RF6CT+kfZCyC2/kAdUlbVNvUfgsfANWD7toIRbRwcyk7awg1jUJElEbEx17DMqr3 # nCLzfFiS09Y/9c7rtLfTwyPW1k6XAr9fykVziup5KeOEQaetpPTtvV6DFqcvQ57p # OdwMZytY+f8KKctV+X0XckmDVRQu9I9/FaWsQT82sXUSI21apAwl22Vh3mRMGkHv # eHSa+I9KQwFpXEh/LE9PYWnQBR95DIuI1u2TP1tyXdu53/seUFmTUQ6JHeQynNJ3 # E25yxYzxRXwtfTINo+YWzORVe5Gie/aWek8AnC3GSQ2yaJXBCH4= # =0G1o # -----END PGP SIGNATURE----- # gpg: Signature made Fri 25 Jul 2025 11:52:27 EDT # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [unknown] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [unknown] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: hw/display/qxl-render.c: fix qxl_unpack_chunks() chunk size calculation Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Stefan Hajnoczi	26453a7f35	* rust: small cleanups + script to update packages * target/i386: AVX bugfix -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmiDfdIUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroO94Af7BJomIpZfOvtE/NJFXNfjdMrVQMhc A1BzFahs0MY0Zg3SzVu+wQa6yG2m4sHlqFVQBBCoUCL8Fu7UQoCJesMkCvI6KQly rZ/5Pp6zZWs4CXR+3mBsw0YqPGG/+rjPxsJf32Z04yrCFPZha7+V9Y+ABDCHv3cZ IIRQwzIPNu0kv8qeBeXZ5ZfBghsmRiQTJTCv0agezp+5jMH1mtATLUqnKiOMLlLh ERcw6n74bY7MXqIfFlYRfNmJ+v2jHZQbP3MhEk8ReXfhx2yC9axpppfm6a/bDjhU iCSSgAi7+Kj/7GPp6TdDmvQTvg3tKRdiEcvnxF95EIvcsu8L8wEPNJAzFA== =H4e7 -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * rust: small cleanups + script to update packages * target/i386: AVX bugfix # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmiDfdIUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroO94Af7BJomIpZfOvtE/NJFXNfjdMrVQMhc # A1BzFahs0MY0Zg3SzVu+wQa6yG2m4sHlqFVQBBCoUCL8Fu7UQoCJesMkCvI6KQly # rZ/5Pp6zZWs4CXR+3mBsw0YqPGG/+rjPxsJf32Z04yrCFPZha7+V9Y+ABDCHv3cZ # IIRQwzIPNu0kv8qeBeXZ5ZfBghsmRiQTJTCv0agezp+5jMH1mtATLUqnKiOMLlLh # ERcw6n74bY7MXqIfFlYRfNmJ+v2jHZQbP3MhEk8ReXfhx2yC9axpppfm6a/bDjhU # iCSSgAi7+Kj/7GPp6TdDmvQTvg3tKRdiEcvnxF95EIvcsu8L8wEPNJAzFA== # =H4e7 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 25 Jul 2025 08:51:30 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386: fix width of third operand of VINSERTx128 scripts: add script to help distros use global Rust packages rust/pl011: merge device_class.rs into device.rs rust: devices are not staticlibs Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	8 months ago
Markus Armbruster	62e1fa22f5	qga: Add cross-references Enclose command and type names in `backquotes`, so they become links in generated HTML. We did this for qapi/ in merge commit `504632dcc6`. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250717115246.3830007-5-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>	9 months ago
Markus Armbruster	ef7e21964d	qga: Rephrase return docs to avoid type name "Returns: <description>" is rendered like Return: <Type> – <description> Mentioning the type in the description again is commonly redundant. There is just one such description. Rephrase it not to mention the type. We did this for qapi/ in commit `f7296f8de5` (qapi: rephrase return docs to avoid type name). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250717115246.3830007-4-armbru@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>	9 months ago

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