riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Mohamed Mediouni	2e1bb23b44	tests: data: update AArch64 ACPI tables After the previous commit introducing GICv3 + GICv2m configurations, update the AArch64 ACPI tables for the GICv2 case. Changes to the ACPI tables: tests/data/acpi/aarch64/virt/IORT.dsl: @@ -11,68 +11,49 @@ / [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 00000080 +[004h 0004 004h] Table Length : 00000054 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : B1 +[009h 0009 001h] Checksum : 3C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000002 +[024h 0036 004h] Node Count : 00000001 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 02 +[031h 0049 002h] Length : 0024 +[033h 0051 001h] Revision : 03 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 -[03Ch 0060 004h] Mapping Offset : 00000000 +[03Ch 0060 004h] Mapping Offset : 00000024 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 02 -[049h 0073 002h] Length : 0038 -[04Bh 0075 001h] Revision : 03 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000024 - -[058h 0088 008h] Memory Properties : [IORT Memory Access Properties] -[058h 0088 004h] Cache Coherency : 00000001 -[05Ch 0092 001h] Hints (decoded below) : 00 +[040h 0064 008h] Memory Properties : [IORT Memory Access Properties] +[040h 0064 004h] Cache Coherency : 00000001 +[044h 0068 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[05Dh 0093 002h] Reserved : 0000 -[05Fh 0095 001h] Memory Flags (decoded below) : 03 +[045h 0069 002h] Reserved : 0000 +[047h 0071 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[060h 0096 004h] ATS Attribute : 00000000 -[064h 0100 004h] PCI Segment Number : 00000000 -[068h 0104 001h] Memory Size Limit : 40 -[069h 0105 002h] PASID Capabilities : 0000 -[06Bh 0107 001h] Reserved : 00 +[048h 0072 004h] ATS Attribute : 00000000 +[04Ch 0076 004h] PCI Segment Number : 00000000 +[050h 0080 001h] Memory Size Limit : 40 +[051h 0081 002h] PASID Capabilities : 0000 +[053h 0083 001h] Reserved : 00 -[06Ch 0108 004h] Input base : 00000000 -[070h 0112 004h] ID Count : 0000FFFF -[074h 0116 004h] Output Base : 00000000 -[078h 0120 004h] Output Reference : 00000030 -[07Ch 0124 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 84 (0x54) -Raw Table Data: Length 128 (0x80) - - 0000: 49 4F 52 54 80 00 00 00 05 B1 42 4F 43 48 53 20 // IORT......BOCHS + 0000: 49 4F 52 54 54 00 00 00 05 3C 42 4F 43 48 53 20 // IORTT....<BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 02 38 00 03 01 00 00 00 // .........8...... - 0050: 01 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... - 0060: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... - 0070: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0020: 01 00 00 00 01 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 02 24 00 03 00 00 00 00 00 00 00 00 24 00 00 00 // .$..........$... + 0040: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ + 0050: 40 00 00 00 // @... tests/data/acpi/aarch64/virt/IORT.smmuv3-dev.dsl: @@ -11,164 +11,120 @@ / [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 0000016C +[004h 0004 004h] Table Length : 00000104 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : C8 +[009h 0009 001h] Checksum : 49 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000004 +[024h 0036 004h] Node Count : 00000003 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0044 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 000000000C000000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 000000000C000000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 00000090 -[078h 0120 004h] PRI GSIV : 00000091 -[07Ch 0124 004h] GERR GSIV : 00000093 -[080h 0128 004h] Sync GSIV : 00000092 -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 00000090 +[060h 0096 004h] PRI GSIV : 00000091 +[064h 0100 004h] GERR GSIV : 00000093 +[068h 0104 004h] Sync GSIV : 00000092 +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[074h 0116 001h] Type : 04 +[075h 0117 002h] Length : 0044 +[077h 0119 001h] Revision : 04 +[078h 0120 004h] Identifier : 00000001 +[07Ch 0124 004h] Mapping Count : 00000000 +[080h 0128 004h] Mapping Offset : 00000000 -[0A0h 0160 001h] Type : 04 -[0A1h 0161 002h] Length : 0058 -[0A3h 0163 001h] Revision : 04 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000001 -[0ACh 0172 004h] Mapping Offset : 00000044 - -[0B0h 0176 008h] Base Address : 000000000C020000 -[0B8h 0184 004h] Flags (decoded below) : 00000001 +[084h 0132 008h] Base Address : 000000000C020000 +[08Ch 0140 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[0BCh 0188 004h] Reserved : 00000000 -[0C0h 0192 008h] VATOS Address : 0000000000000000 -[0C8h 0200 004h] Model : 00000000 -[0CCh 0204 004h] Event GSIV : 00000094 -[0D0h 0208 004h] PRI GSIV : 00000095 -[0D4h 0212 004h] GERR GSIV : 00000097 -[0D8h 0216 004h] Sync GSIV : 00000096 -[0DCh 0220 004h] Proximity Domain : 00000000 -[0E0h 0224 004h] Device ID Mapping Index : 00000000 +[090h 0144 004h] Reserved : 00000000 +[094h 0148 008h] VATOS Address : 0000000000000000 +[09Ch 0156 004h] Model : 00000000 +[0A0h 0160 004h] Event GSIV : 00000094 +[0A4h 0164 004h] PRI GSIV : 00000095 +[0A8h 0168 004h] GERR GSIV : 00000097 +[0ACh 0172 004h] Sync GSIV : 00000096 +[0B0h 0176 004h] Proximity Domain : 00000000 +[0B4h 0180 004h] Device ID Mapping Index : 00000000 -[0E4h 0228 004h] Input base : 00000000 -[0E8h 0232 004h] ID Count : 0000FFFF -[0ECh 0236 004h] Output Base : 00000000 -[0F0h 0240 004h] Output Reference : 00000030 -[0F4h 0244 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[0B8h 0184 001h] Type : 02 +[0B9h 0185 002h] Length : 004C +[0BBh 0187 001h] Revision : 03 +[0BCh 0188 004h] Identifier : 00000002 +[0C0h 0192 004h] Mapping Count : 00000002 +[0C4h 0196 004h] Mapping Offset : 00000024 -[0F8h 0248 001h] Type : 02 -[0F9h 0249 002h] Length : 0074 -[0FBh 0251 001h] Revision : 03 -[0FCh 0252 004h] Identifier : 00000003 -[100h 0256 004h] Mapping Count : 00000004 -[104h 0260 004h] Mapping Offset : 00000024 - -[108h 0264 008h] Memory Properties : [IORT Memory Access Properties] -[108h 0264 004h] Cache Coherency : 00000001 -[10Ch 0268 001h] Hints (decoded below) : 00 +[0C8h 0200 008h] Memory Properties : [IORT Memory Access Properties] +[0C8h 0200 004h] Cache Coherency : 00000001 +[0CCh 0204 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[10Dh 0269 002h] Reserved : 0000 -[10Fh 0271 001h] Memory Flags (decoded below) : 03 +[0CDh 0205 002h] Reserved : 0000 +[0CFh 0207 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[110h 0272 004h] ATS Attribute : 00000000 -[114h 0276 004h] PCI Segment Number : 00000000 -[118h 0280 001h] Memory Size Limit : 40 -[119h 0281 002h] PASID Capabilities : 0000 -[11Bh 0283 001h] Reserved : 00 +[0D0h 0208 004h] ATS Attribute : 00000000 +[0D4h 0212 004h] PCI Segment Number : 00000000 +[0D8h 0216 001h] Memory Size Limit : 40 +[0D9h 0217 002h] PASID Capabilities : 0000 +[0DBh 0219 001h] Reserved : 00 -[11Ch 0284 004h] Input base : 00000000 -[120h 0288 004h] ID Count : 000001FF -[124h 0292 004h] Output Base : 00000000 -[128h 0296 004h] Output Reference : 00000048 -[12Ch 0300 004h] Flags (decoded below) : 00000000 +[0DCh 0220 004h] Input base : 00000000 +[0E0h 0224 004h] ID Count : 000001FF +[0E4h 0228 004h] Output Base : 00000000 +[0E8h 0232 004h] Output Reference : 00000030 +[0ECh 0236 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[130h 0304 004h] Input base : 00001000 -[134h 0308 004h] ID Count : 000000FF -[138h 0312 004h] Output Base : 00001000 -[13Ch 0316 004h] Output Reference : 000000A0 -[140h 0320 004h] Flags (decoded below) : 00000000 +[0F0h 0240 004h] Input base : 00001000 +[0F4h 0244 004h] ID Count : 000000FF +[0F8h 0248 004h] Output Base : 00001000 +[0FCh 0252 004h] Output Reference : 00000074 +[100h 0256 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[144h 0324 004h] Input base : 00000200 -[148h 0328 004h] ID Count : 00000DFF -[14Ch 0332 004h] Output Base : 00000200 -[150h 0336 004h] Output Reference : 00000030 -[154h 0340 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 260 (0x104) -[158h 0344 004h] Input base : 00001100 -[15Ch 0348 004h] ID Count : 0000EEFF -[160h 0352 004h] Output Base : 00001100 -[164h 0356 004h] Output Reference : 00000030 -[168h 0360 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 - -Raw Table Data: Length 364 (0x16C) - - 0000: 49 4F 52 54 6C 01 00 00 05 C8 42 4F 43 48 53 20 // IORTl.....BOCHS + 0000: 49 4F 52 54 04 01 00 00 05 49 42 4F 43 48 53 20 // IORT.....IBOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 04 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 00 0C 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 90 00 00 00 91 00 00 00 93 00 00 00 // ................ - 0080: 92 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 04 58 00 04 02 00 00 00 01 00 00 00 44 00 00 00 // .X..........D... - 00B0: 00 00 02 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................ - 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 94 00 00 00 // ................ - 00D0: 95 00 00 00 97 00 00 00 96 00 00 00 00 00 00 00 // ................ - 00E0: 00 00 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 // ................ - 00F0: 30 00 00 00 00 00 00 00 02 74 00 03 03 00 00 00 // 0........t...... - 0100: 04 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... - 0110: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... - 0120: FF 01 00 00 00 00 00 00 48 00 00 00 00 00 00 00 // ........H....... - 0130: 00 10 00 00 FF 00 00 00 00 10 00 00 A0 00 00 00 // ................ - 0140: 00 00 00 00 00 02 00 00 FF 0D 00 00 00 02 00 00 // ................ - 0150: 30 00 00 00 00 00 00 00 00 11 00 00 FF EE 00 00 // 0............... - 0160: 00 11 00 00 30 00 00 00 00 00 00 00 // ....0....... + 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D.............. + 0040: 00 00 00 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 // ................ + 0060: 91 00 00 00 93 00 00 00 92 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 04 44 00 04 01 00 00 00 00 00 00 00 // .....D.......... + 0080: 00 00 00 00 00 00 02 0C 00 00 00 00 01 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 94 00 00 00 95 00 00 00 97 00 00 00 96 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 02 4C 00 03 02 00 00 00 // .........L...... + 00C0: 02 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... + 00D0: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... + 00E0: FF 01 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 00F0: 00 10 00 00 FF 00 00 00 00 10 00 00 74 00 00 00 // ............t... + 0100: 00 00 00 00 // .... tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy.dsl: @@ -11,129 +11,92 @@ */ [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 00000114 +[004h 0004 004h] Table Length : 000000C0 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : 4A +[009h 0009 001h] Checksum : 1C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000003 +[024h 0036 004h] Node Count : 00000002 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0044 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 0000000009050000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 0000000009050000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 0000006A -[078h 0120 004h] PRI GSIV : 0000006B -[07Ch 0124 004h] GERR GSIV : 0000006D -[080h 0128 004h] Sync GSIV : 0000006C -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 0000006A +[060h 0096 004h] PRI GSIV : 0000006B +[064h 0100 004h] GERR GSIV : 0000006D +[068h 0104 004h] Sync GSIV : 0000006C +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[074h 0116 001h] Type : 02 +[075h 0117 002h] Length : 004C +[077h 0119 001h] Revision : 03 +[078h 0120 004h] Identifier : 00000001 +[07Ch 0124 004h] Mapping Count : 00000002 +[080h 0128 004h] Mapping Offset : 00000024 -[0A0h 0160 001h] Type : 02 -[0A1h 0161 002h] Length : 0074 -[0A3h 0163 001h] Revision : 03 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000004 -[0ACh 0172 004h] Mapping Offset : 00000024 - -[0B0h 0176 008h] Memory Properties : [IORT Memory Access Properties] -[0B0h 0176 004h] Cache Coherency : 00000001 -[0B4h 0180 001h] Hints (decoded below) : 00 +[084h 0132 008h] Memory Properties : [IORT Memory Access Properties] +[084h 0132 004h] Cache Coherency : 00000001 +[088h 0136 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 002h] Reserved : 0000 -[0B7h 0183 001h] Memory Flags (decoded below) : 03 +[089h 0137 002h] Reserved : 0000 +[08Bh 0139 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[0B8h 0184 004h] ATS Attribute : 00000000 -[0BCh 0188 004h] PCI Segment Number : 00000000 -[0C0h 0192 001h] Memory Size Limit : 40 -[0C1h 0193 002h] PASID Capabilities : 0000 -[0C3h 0195 001h] Reserved : 00 +[08Ch 0140 004h] ATS Attribute : 00000000 +[090h 0144 004h] PCI Segment Number : 00000000 +[094h 0148 001h] Memory Size Limit : 40 +[095h 0149 002h] PASID Capabilities : 0000 +[097h 0151 001h] Reserved : 00 -[0C4h 0196 004h] Input base : 00000000 -[0C8h 0200 004h] ID Count : 000001FF -[0CCh 0204 004h] Output Base : 00000000 -[0D0h 0208 004h] Output Reference : 00000048 -[0D4h 0212 004h] Flags (decoded below) : 00000000 +[098h 0152 004h] Input base : 00000000 +[09Ch 0156 004h] ID Count : 000001FF +[0A0h 0160 004h] Output Base : 00000000 +[0A4h 0164 004h] Output Reference : 00000030 +[0A8h 0168 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0D8h 0216 004h] Input base : 00001000 -[0DCh 0220 004h] ID Count : 000000FF -[0E0h 0224 004h] Output Base : 00001000 -[0E4h 0228 004h] Output Reference : 00000048 -[0E8h 0232 004h] Flags (decoded below) : 00000000 +[0ACh 0172 004h] Input base : 00001000 +[0B0h 0176 004h] ID Count : 000000FF +[0B4h 0180 004h] Output Base : 00001000 +[0B8h 0184 004h] Output Reference : 00000030 +[0BCh 0188 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0ECh 0236 004h] Input base : 00000200 -[0F0h 0240 004h] ID Count : 00000DFF -[0F4h 0244 004h] Output Base : 00000200 -[0F8h 0248 004h] Output Reference : 00000030 -[0FCh 0252 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 192 (0xC0) -[100h 0256 004h] Input base : 00001100 -[104h 0260 004h] ID Count : 0000EEFF -[108h 0264 004h] Output Base : 00001100 -[10Ch 0268 004h] Output Reference : 00000030 -[110h 0272 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 - -Raw Table Data: Length 276 (0x114) - - 0000: 49 4F 52 54 14 01 00 00 05 4A 42 4F 43 48 53 20 // IORT.....JBOCHS + 0000: 49 4F 52 54 C0 00 00 00 05 1C 42 4F 43 48 53 20 // IORT......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 05 09 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 6A 00 00 00 6B 00 00 00 6D 00 00 00 // ....j...k...m... - 0080: 6C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // l............... - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 02 74 00 03 02 00 00 00 04 00 00 00 24 00 00 00 // .t..........$... - 00B0: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ - 00C0: 40 00 00 00 00 00 00 00 FF 01 00 00 00 00 00 00 // @............... - 00D0: 48 00 00 00 00 00 00 00 00 10 00 00 FF 00 00 00 // H............... - 00E0: 00 10 00 00 48 00 00 00 00 00 00 00 00 02 00 00 // ....H........... - 00F0: FF 0D 00 00 00 02 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0100: 00 11 00 00 FF EE 00 00 00 11 00 00 30 00 00 00 // ............0... - 0110: 00 00 00 00 // .... + 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D.............. + 0040: 00 00 05 09 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 6A 00 00 00 // ............j... + 0060: 6B 00 00 00 6D 00 00 00 6C 00 00 00 00 00 00 00 // k...m...l....... + 0070: 00 00 00 00 02 4C 00 03 01 00 00 00 02 00 00 00 // .....L.......... + 0080: 24 00 00 00 01 00 00 00 00 00 00 03 00 00 00 00 // $............... + 0090: 00 00 00 00 40 00 00 00 00 00 00 00 FF 01 00 00 // ....@........... + 00A0: 00 00 00 00 30 00 00 00 00 00 00 00 00 10 00 00 // ....0........... + 00B0: FF 00 00 00 00 10 00 00 30 00 00 00 00 00 00 00 // ........0....... Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	5f834ccdcf	hw: arm: virt: rework MSI-X configuration Introduce a -M msi= argument to be able to control MSI-X support independently from ITS, as part of supporting GICv3 + GICv2m platforms. Remove vms->its as it's no longer needed after that change. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	eb1c60997c	qtest: hw/arm: virt: skip ACPI test for IORT with GICv2 Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Philippe Mathieu-Daudé	7ca22ae3e6	accel/system: Introduce hwaccel_enabled() helper hwaccel_enabled() return whether any hardware accelerator is enabled. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Sebastian Ott	d30b420c9c	target/arm/kvm: add constants for new PSCI versions Add constants for PSCI version 1_2 and 1_3. Signed-off-by: Sebastian Ott <sebott@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Peter Maydell	0b91040d23	pull-loongarch-2026-02-10 -----BEGIN PGP SIGNATURE----- iLMEAAEKAB0WIQTKRzxE1qCcGJoZP81FK5aFKyaCFgUCaYqcuAAKCRBFK5aFKyaC FkgeA/9G0mHfS7GOrna5V3mUkTmCZt0vDRyhoUvQYhq5xOxiw6xTwUHSnUGhrW1X Rl5I7TcRiv/Bl6pmDB3c0lZ4+V70MQBufxpwURA3XzKT1C2RSjVHEr7p2WzRiXPF 0Zgam8cG2xugT3Al9gdsrba1br/OLXtJHj1+n/L6tgAI8V2Beg== =WO9M -----END PGP SIGNATURE----- Merge tag 'pull-loongarch-20260210' of https://github.com/gaosong715/qemu into staging pull-loongarch-2026-02-10 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQTKRzxE1qCcGJoZP81FK5aFKyaCFgUCaYqcuAAKCRBFK5aFKyaC # FkgeA/9G0mHfS7GOrna5V3mUkTmCZt0vDRyhoUvQYhq5xOxiw6xTwUHSnUGhrW1X # Rl5I7TcRiv/Bl6pmDB3c0lZ4+V70MQBufxpwURA3XzKT1C2RSjVHEr7p2WzRiXPF # 0Zgam8cG2xugT3Al9gdsrba1br/OLXtJHj1+n/L6tgAI8V2Beg== # =WO9M # -----END PGP SIGNATURE----- # gpg: Signature made Tue Feb 10 02:49:28 2026 GMT # gpg: using RSA key CA473C44D6A09C189A193FCD452B96852B268216 # gpg: Good signature from "Song Gao <gaosong@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CA47 3C44 D6A0 9C18 9A19 3FCD 452B 9685 2B26 8216 * tag 'pull-loongarch-20260210' of https://github.com/gaosong715/qemu: target/loongarch: Add LA v1.1 instructions to max cpu target/loongarch: Add sc.q instructions target/loongarch: Add llacq/screl instructions target/loongarch: Add estimated reciprocal instructions target/loongarch: Add amcas[_db].{b/h/w/d} target/loongarch: Add am{swap/add}[_db].{b/h} target/loongarch: Require atomics to be aligned Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Peter Maydell	37daf4ec82	Various patches related to single binary effort: - Reduce RISC-V Boston tests - Prohibit target_ulong / TARGET_PAGE_SIZE uses on s390x target - Build target/arm/arm-qmp-cmds once - Forbid legacy native endianness & ld/st_phys APIs on SPARC targets - Forbid legacy ld/st_phys APIs on x86 targets - Rename OpenRISC -> or1k - Avoid QAPI parsing in target_arch() -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmmKO5wACgkQ4+MsLN6t wN5EchAAxWVK1eWW5cO7R3+PxWFFzAMcyTzVUftNIyMLZQcXg5C6P2MSt8gsU8KC oOwl9S85u5dYh/PlAJtQYC+wtNUxawaJk26vUm3k+uOY2XgqCLtFKts+id15F3Hb RueLTEM095jbFgl5OzDwFVRAXP/z727vRsSN2ULXdphHpSVnrROGLz++Uqn7wAmd S9u8q35VVRkHl5TRQBDCYNddvGkW6PY0lSdDPhPMYFDH0Pln1Ao3fEn1zfa1c2gP HQ1d4MdHi8XX041o2TPFZf74tEs0EeSaxBtfyFEMByOs2kVe8oiX5oaM37vbejLa WAfwkG1imw9LcMo0VyjMGgQMb0tkdCVJWzp47eEAEhxSHBsfX5w7+jG0pBng3BBJ 6BrcfzVcWeqScUJPdXbM+mY+uBW09JHsTH37aM1NCsRlJI3gys2TfY/oIyVb7aqM C17DPKwxv+LVC5BI8LPAkh/nM2/sh5jtC+DjqaAFfAlo3JPLIUOcEIpFikiGbbzU MFH1k6YRAee3e7fW1Sw26R17Sf+VTYO9EhYiyWdyAIaBPZ5r7V/fVZWNNrBvh3Zd +ETHyRr/mwxbPx3fiNRg880jsP6mVhpLqykRJN1ttW0eQPaA96aqLmDrez/NFF4D NisJI8nlJNSEnF84cKgpV74mbIM5lmwMQi684rnI/Ty31X1hLxU= =dY6o -----END PGP SIGNATURE----- Merge tag 'single-binary-20260206' of https://github.com/philmd/qemu into staging Various patches related to single binary effort: - Reduce RISC-V Boston tests - Prohibit target_ulong / TARGET_PAGE_SIZE uses on s390x target - Build target/arm/arm-qmp-cmds once - Forbid legacy native endianness & ld/st_phys APIs on SPARC targets - Forbid legacy ld/st_phys APIs on x86 targets - Rename OpenRISC -> or1k - Avoid QAPI parsing in target_arch() # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmmKO5wACgkQ4+MsLN6t # wN5EchAAxWVK1eWW5cO7R3+PxWFFzAMcyTzVUftNIyMLZQcXg5C6P2MSt8gsU8KC # oOwl9S85u5dYh/PlAJtQYC+wtNUxawaJk26vUm3k+uOY2XgqCLtFKts+id15F3Hb # RueLTEM095jbFgl5OzDwFVRAXP/z727vRsSN2ULXdphHpSVnrROGLz++Uqn7wAmd # S9u8q35VVRkHl5TRQBDCYNddvGkW6PY0lSdDPhPMYFDH0Pln1Ao3fEn1zfa1c2gP # HQ1d4MdHi8XX041o2TPFZf74tEs0EeSaxBtfyFEMByOs2kVe8oiX5oaM37vbejLa # WAfwkG1imw9LcMo0VyjMGgQMb0tkdCVJWzp47eEAEhxSHBsfX5w7+jG0pBng3BBJ # 6BrcfzVcWeqScUJPdXbM+mY+uBW09JHsTH37aM1NCsRlJI3gys2TfY/oIyVb7aqM # C17DPKwxv+LVC5BI8LPAkh/nM2/sh5jtC+DjqaAFfAlo3JPLIUOcEIpFikiGbbzU # MFH1k6YRAee3e7fW1Sw26R17Sf+VTYO9EhYiyWdyAIaBPZ5r7V/fVZWNNrBvh3Zd # +ETHyRr/mwxbPx3fiNRg880jsP6mVhpLqykRJN1ttW0eQPaA96aqLmDrez/NFF4D # NisJI8nlJNSEnF84cKgpV74mbIM5lmwMQi684rnI/Ty31X1hLxU= # =dY6o # -----END PGP SIGNATURE----- # gpg: Signature made Mon Feb 9 19:55:08 2026 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'single-binary-20260206' of https://github.com/philmd/qemu: (30 commits) target-info: Statically initialize target_arch meson: Add TARGET_ARCH to config_target_data qapi: Add hexagon to SysEmuTarget hw/or1k: Rename or1k-sim.c from openrisc_sim.c docs/system/or1k: Rename from openrisc tests/tcg/or1k: Rename from openrisc hw/or1k: Rename from openrisc include/hw/or1k: Rename from openrisc target/or1k: Rename from openrisc configs/targets: Restrict the legacy ldst_phys() API on x86 targets hw/intc/ioapic: Replace legacy st_phys() -> address_space_st() hw/intc: Mark x86-specific [IO]APIC peripherals as little-endian target/i386: Use explicit little-endian LD/ST API configs/targets: Restrict legacy ldst_phys() API on 32-bit SPARC target target/sparc: Replace legacy st_phys() -> address_space_st() configs/targets: Forbid SPARC to use legacy native endianness APIs target/sparc: Replace MO_TE -> MO_BE target/sparc: Remove dubious swapping in LD_code() helper target/arm/arm-qmp-cmds.c: make compilation unit common target/s390x: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Jiajie Chen	59c8adc283	target/loongarch: Add LA v1.1 instructions to max cpu Add LA v1.1 new instructinos to max cpu by enabling new features in CPUCFG2. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Jiajie Chen	424227ff54	target/loongarch: Add sc.q instructions Add the sc.q instruction in LoongArch v1.1, guarded by CPUCFG2.SCQ. It is implemented by reading 128bit data (llval + llval_high) in ll.d when aligned to 16B boundary, and cmpxchg 128bit in sc.q. If ld.d matches the higher part of the 128bit, its data is taken from llval_high. Expected assembly sequence: ll.d lo, base, 0 ld.d hi, base, 8 sc.q lo, hi, base Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Jiajie Chen	6e533aca52	target/loongarch: Add llacq/screl instructions Add the following instructions in LoongArch v1.1: - llacq.w - screl.w - llacq.d - screl.d They are guarded by CPUCFG2.LLACQ_SCREL. Signed-off-by: Jiajie Chen <c@jia.je> Co-developed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Jiajie Chen	ebe521ad93	target/loongarch: Add estimated reciprocal instructions Add the following new instructions in LoongArch v1.1: - frecipe.s - frecipe.d - frsqrte.s - frsqrte.d - vfrecipe.s - vfrecipe.d - vfrsqrte.s - vfrsqrte.d - xvfrecipe.s - xvfrecipe.d - xvfrsqrte.s - xvfrsqrte.d They are guarded by CPUCFG2.FRECIPE. Altought the instructions allow implementation to improve performance by reducing precision, we use the existing softfloat implementation. Signed-off-by: Jiajie Chen <c@jia.je> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Jiajie Chen	c1db8eb023	target/loongarch: Add amcas[_db].{b/h/w/d} The new instructions are introduced in LoongArch v1.1: - amcas.b - amcas.h - amcas.w - amcas.d - amcas_db.b - amcas_db.h - amcas_db.w - amcas_db.d The new instructions are gated by CPUCFG2.LAMCAS. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Jiajie Chen	2276261a01	target/loongarch: Add am{swap/add}[_db].{b/h} The new instructions are introduced in LoongArch v1.1: - amswap.b - amswap.h - amadd.b - amadd.h - amswap_db.b - amswap_db.h - amadd_db.b - amadd_db.h The instructions are gated by CPUCFG2.LAM_BH. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Jiajie Chen	5cf9a035aa	target/loongarch: Require atomics to be aligned Currently, all atomic instructions in LoongArch require the address to be aligned. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>	4 months ago
Richard Henderson	e934c624f3	target-info: Statically initialize target_arch Use TARGET_ARCH and token pasting to initialize target_arch from SYS_EMU_TARGET_*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260205030617.266625-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	f87f7e145d	meson: Add TARGET_ARCH to config_target_data Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260205030617.266625-3-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	3fdc58a30b	qapi: Add hexagon to SysEmuTarget Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20260205030617.266625-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	afc63fb067	hw/or1k: Rename or1k-sim.c from openrisc_sim.c Match the filename to the machine type: or1k-sim. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Stafford Horne <shorne@gmail.com> Message-ID: <20260205030244.266447-7-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	322963969e	docs/system/or1k: Rename from openrisc Also rename docs/system/target-or1k.rst from target-openrisc.rst, and update all toctree entries to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Stafford Horne <shorne@gmail.com> Message-ID: <20260205030244.266447-6-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	e4dad5f55f	tests/tcg/or1k: Rename from openrisc Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Stafford Horne <shorne@gmail.com> Message-ID: <20260205030244.266447-5-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	44967f9422	hw/or1k: Rename from openrisc Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260205030244.266447-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	8cbc31d341	include/hw/or1k: Rename from openrisc Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Stafford Horne <shorne@gmail.com> Message-ID: <20260205030244.266447-3-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Richard Henderson	62822fc7e0	target/or1k: Rename from openrisc This is the minimal change beginning with TARGET_ARCH in configs/targets/or1k-* from openrisc to or1k, then adjust TARGET_OR1K, QEMU_ARCH_OR1K, directory names, and meson.build to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260205030244.266447-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	a8b5e57635	configs/targets: Restrict the legacy ldst_phys() API on x86 targets The x86 targets don't use the legacy ldst_phys() API anymore. Set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable to hide the legacy API to the x86 binaries, avoiding further API uses to creep in. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260204204103.46343-5-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	33f79f636f	hw/intc/ioapic: Replace legacy st_phys() -> address_space_st() Prefer the address_space_ld/st API over the legacy ld_phys() because it allow checking for bus access fault. However the IOAPIC datasheet (82093AA Order Number: 290566-001) doesn't mention any fault occuring when the system bus (ISA bus) is accessed. The ISA bus neither offer a way to signal recoverable access faults. Therefore just inline the stl_le_phys() call, not specifying any memory transaction attribute nor expecting transation result, per the definition in "system/memory_ldst_phys_endian.h.inc": 42 static inline void ST_PHYS(l)(ARG1_DECL, hwaddr addr, uint32_t val) 43 { 44 ADDRESS_SPACE_ST(l)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); 45 } No logical change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260204204103.46343-4-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	3f19262008	hw/intc: Mark x86-specific [IO]APIC peripherals as little-endian These devices are only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260204204103.46343-3-philmd@linaro.org>	4 months ago
Philippe Mathieu-Daudé	c2e7579505	target/i386: Use explicit little-endian LD/ST API The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change running: $ for a in uw w l q; do \ sed -i -e "s/ld${a}_p(/ld${a}_le_p(/" \ $(git grep -wlE '(ld\|st)u?[wlq]_p' target/i386/); done Coding style adapted manually. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260204204103.46343-2-philmd@linaro.org>	4 months ago
Philippe Mathieu-Daudé	6172a4257e	configs/targets: Restrict legacy ldst_phys() API on 32-bit SPARC target Since we removed the last legacy uses of the legacy ldst_phys() API, set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable to hide the legacy API to the qemu-system-sparc binary, avoiding further API uses to creep in. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260204215304.52757-3-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	11eb2f873b	target/sparc: Replace legacy st_phys() -> address_space_st() Prefer the address_space_ld/st API over the legacy ld_phys() because it allow checking for bus access fault. get_physical_address() already accessed the PTE stored at %pde_ptr and is going to update it. Assume the address space is also writeable there. The SPARC v8 manual only mentions faults (with error condition bits updated) in the READ path but not on the WRITE (update) one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260204215304.52757-2-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	3563f60931	configs/targets: Forbid SPARC to use legacy native endianness APIs All SPARC-related binaries are buildable without a single use of the legacy "native endian" API. Set the transitional TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API definition to forbid further uses of the legacy API. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260203230054.23667-6-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	136b115809	target/sparc: Replace MO_TE -> MO_BE We only build the SPARC targets using big endianness order, therefore the MO_TE definitions expand to the big endian one. Use the latter which is more explicit. Mechanical change running: $ sed -i -e s/MO_TE/MO_BE/ \ $(git grep -wl MO_TE target/sparc/) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260203230054.23667-5-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	f811e8ba6c	target/sparc: Remove dubious swapping in LD_code() helper Since the endianness is contained in %oi, cpu_ld*_code_mmu() has already honored it. Swapping again makes no sense. Remove the bswap() calls. Fixes: `2786a3f8d3` ("Use GET_ASI_CODE for ASI_KERNELTXT / ASI_USERTXT") Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260203230054.23667-4-philmd@linaro.org>	2 months ago
Pierrick Bouvier	3ca2cadd39	target/arm/arm-qmp-cmds.c: make compilation unit common Move gic_cap_kvm_probe to target/arm/kvm.c to remove #ifdef CONFIG_KVM. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20260206042150.912578-2-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	e9c3aafb5f	target/s390x: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64() The s390x target is a 64-bit one, so tcg_global_mem_new() expands to tcg_global_mem_new_i64(). Use the latter which is more explicit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-11-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	b29c1d33a2	target/s390x: Expand tcg_gen_qemu_ld/st_tl() as 64-bit target The s390x target is a 64-bit one, so we have these expansions in the "tcg/tcg-op.h" header: . tcg_gen_qemu_ld_tl() -> tcg_gen_qemu_ld_i64() . tcg_gen_qemu_st_tl() -> tcg_gen_qemu_st_i64() Use the expanded form which is more explicit when a target isn't built for different words size. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-10-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	ad429e3a38	target/s390x: Expand TCGv type as 64-bit target The s390x target is a 64-bit one, so TCGv expands to TCGv_i64. Use the latter which is already used about a hundred times in this file, and is also more explicit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-9-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	dacb7a6510	target/s390x: Build system units in common source set Except the ioinst.c file which uses the TARGET_PAGE_SIZE definition in the ioinst_handle_chsc() method, all other files in meson's s390x_system_ss[] source set don't use any target-specific code. Moving them in the other s390x_common_system_ss[] set to build as common objects ensures these files won't use any target-specific API such target_ulong / TARGET_PAGE_SIZE, thus forcing to use the appropriate types instead (such vaddr, hwaddr, uint64_t, ...). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-8-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	8d2fd86965	target/s390x: Add more unreachable KVM stubs Next patch will move s390x system objects from the target specific source set to the common one. Unfortunately the kvm_enabled() macro won't be evaluable at built-time anymore. Add stubs for KVM symbols unreachable at runtime. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20260206181953.18683-7-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	e0abd3de76	target/s390x: Un-inline KVM Protected Virtualization stubs By removing the target-specific 'CONFIG_KVM' definition this header can be used by files in meson common_ss[]. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20260206181953.18683-6-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	4a41b5ecc5	target/s390x: Replace %target_ulong -> %hwaddr where appropriate Use the %hwaddr type for physical addresses. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-5-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	1ba04414cc	target/s390x: Replace %target_ulong -> %vaddr where appropriate Use the %vaddr type for virtual addresses. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-4-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	8a2286cd40	target/s390x: Rename get_phys_page_debug() @vaddr argument as @v_addr In order to use the %vaddr type in s390_cpu_get_phys_page_debug() in the next commit, rename the argument @vaddr -> @v_addr. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260206181953.18683-3-philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	4d784c9120	target/s390x: Use address_space_ldq_be() in read_table_entry() address_space_read/write() is meant for accessing random amount of memory blobs. When the access size is known, use the address_space_ld/st() API which can directly swap endianness. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20260206181953.18683-2-philmd@linaro.org>	3 months ago
Daniel Henrique Barboza	03f1049bc5	riscv64/test_boston.py: fix intermitent test timeout The recently added Boston MIPS board selftest times out consistently in a machine running 'make check-functional' with -j 16: 18/18 func-thorough+func-riscv64-thorough+thorough - qemu:func-riscv64-boston TIMEOUT 120.09s killed by signal 15 SIGTERM The reason is quite boring: it is testing too much stuff. Note that functional tests aren't supposed to be used as stress tests, e.g. it doesn't have to test every single corner case that might hit the board. It is supposed to catch most common user ooopsies. A timeout, in this context, is most likely to be considered something abnormal slowing down the emulation, not a lack of CPU horsepower to run all the tests before timeout. Some of the tests claim to test odd CPU SMP numbers to either "ensures proper core distribution across clusters" or "validating proper handling of larger asymmetric SMP configurations". But there's no SMP/NUMA check made anywhere after boot, so in the end we're just testing whether the board is able to boot with 7/35 CPUs. As far as these tests are concerned we could have a completely broken, but bootable, SMP topology with 7/35 CPUS, and we're oblivious about it. Remove the 7 and 35 SMP tests, keeping the minimal CPUs (2) and maximum (64) tests. With these changes we're now able to run the test with a good TIMEOUT margin: 17/18 func-thorough+func-riscv64-thorough+thorough - qemu:func-riscv64-boston OK 61.28s 3 subtests passed Fixes: `e71111e26b` ("test/functional: Add test for boston-aia board") Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Djordje Todorovic <Djordje.Todorovic@htecgroup.com> Message-ID: <20260126174534.9860-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Peter Maydell	b3abdfa486	Pull request Andrey Drobyshev's qemugdb script improvements and my --device scsi-block,migrate-pr=on\|off live migration support for SCSI Persistent Reservations. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmmJ8t0ACgkQnKSrs4Gr c8goXggAgx8Fehp5q1e1xUulb/WwnHw14lfl2+O4Or3FxK9TDWSUjT0Htk0+QwAf W+7Q7MTnSzLTDYKbsPj+4RxZ+Pth/ra2rhIS3YWMQLNAjFKAIWKvQdD0krOlJ8t+ i3DkERhaw/ke2ImR7GSr7SZjJjhHaxTaC+R/DEPWVxgK1j4mLt/pwAhigWxlvVLT SInnZAvfy7+OspFu3AcBtwDEe0MvIQKdTgxZS7wSf/tWS/9WZqsM8pSL/1+ozPGg hWjHevhGI6LS4QfRqdF6+dq/XaGT81hFNosCL2o9YWbLuipk/9TyUSX7uevo1IFz SpXwxFltCyPicaGJcufX4MjASJqjrg== =DKtL -----END PGP SIGNATURE----- Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging Pull request Andrey Drobyshev's qemugdb script improvements and my --device scsi-block,migrate-pr=on\|off live migration support for SCSI Persistent Reservations. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmmJ8t0ACgkQnKSrs4Gr # c8goXggAgx8Fehp5q1e1xUulb/WwnHw14lfl2+O4Or3FxK9TDWSUjT0Htk0+QwAf # W+7Q7MTnSzLTDYKbsPj+4RxZ+Pth/ra2rhIS3YWMQLNAjFKAIWKvQdD0krOlJ8t+ # i3DkERhaw/ke2ImR7GSr7SZjJjhHaxTaC+R/DEPWVxgK1j4mLt/pwAhigWxlvVLT # SInnZAvfy7+OspFu3AcBtwDEe0MvIQKdTgxZS7wSf/tWS/9WZqsM8pSL/1+ozPGg # hWjHevhGI6LS4QfRqdF6+dq/XaGT81hFNosCL2o9YWbLuipk/9TyUSX7uevo1IFz # SpXwxFltCyPicaGJcufX4MjASJqjrg== # =DKtL # -----END PGP SIGNATURE----- # gpg: Signature made Mon Feb 9 14:44:45 2026 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: docs: add SCSI migrate-pr documentation scsi: save/load SCSI reservation state scsi: track SCSI reservation state for live migration scsi: add error reporting to scsi_SG_IO() scsi: generalize scsi_SG_IO_FROM_DEV() to scsi_SG_IO() scripts/qemugdb: coroutine: Add option for obtaining detailed trace in coredump scripts/qemugdb: timers: Improve 'qemu timers' command readability scripts/qemugdb: timers: Fix KeyError in 'qemu timers' command scripts/qemugdb: mtree: Fix OverflowError in mtree with 128-bit addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Peter Maydell	51e36e86d9	linux-user/syscall.c: Prevent acquiring clone_lock while fork() accel/tcg: Remove a redundant argument attrs in io_prepare() accel/tcg: Fix uninitialized hostp in get_page_addr_code_hostp Revert "tcg/user: do not set exit_request gratuitously" -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmmFkJ0dHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9aLQgAjOLW3deluyYPggdi YXDAS8YfCFbtXJ36jAeMZnRisXnIXcXkWZr/dseVyVoghz3WUbbRAJrbPuIFrTMq b+IX2Gjh7uXgh65EhmwYrinH2jygOdIK5SdJV7x2DtukA1MdRbDHeM8k1gvFNOdn Y4nNbTFzI6wuNfti6rvat2SaPm+b7QgMckxB3R8cTAb3o4zvzeUqJ1HMbYil9VG8 EHQOGJyq2fViTtBm6ZBQ98BylHxqXOsVclchqwARYTlWrvxeVrJ7LopjbD6BfAUr 3qasEKoM9Gu1J+i2HXC14qHofScqVYIO3zFl4jbMSwBSsABGZY1OQBxynfOw3cJ9 15BiXQ== =1ALE -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20260206' of https://gitlab.com/rth7680/qemu into staging linux-user/syscall.c: Prevent acquiring clone_lock while fork() accel/tcg: Remove a redundant argument attrs in io_prepare() accel/tcg: Fix uninitialized hostp in get_page_addr_code_hostp Revert "tcg/user: do not set exit_request gratuitously" # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmmFkJ0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9aLQgAjOLW3deluyYPggdi # YXDAS8YfCFbtXJ36jAeMZnRisXnIXcXkWZr/dseVyVoghz3WUbbRAJrbPuIFrTMq # b+IX2Gjh7uXgh65EhmwYrinH2jygOdIK5SdJV7x2DtukA1MdRbDHeM8k1gvFNOdn # Y4nNbTFzI6wuNfti6rvat2SaPm+b7QgMckxB3R8cTAb3o4zvzeUqJ1HMbYil9VG8 # EHQOGJyq2fViTtBm6ZBQ98BylHxqXOsVclchqwARYTlWrvxeVrJ7LopjbD6BfAUr # 3qasEKoM9Gu1J+i2HXC14qHofScqVYIO3zFl4jbMSwBSsABGZY1OQBxynfOw3cJ9 # 15BiXQ== # =1ALE # -----END PGP SIGNATURE----- # gpg: Signature made Fri Feb 6 06:56:29 2026 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20260206' of https://gitlab.com/rth7680/qemu: accel/tcg: Remove a redundant argument attrs in io_prepare() Revert "tcg/user: do not set exit_request gratuitously" linux-user/syscall.c: Prevent acquiring clone_lock while fork() accel/tcg: Fix uninitialized hostp in get_page_addr_code_hostp accel/tcg: Don't pass NULL to get_page_addr_code_hostp Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Stefan Hajnoczi	a67819adb2	docs: add SCSI migrate-pr documentation Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20260129212035.219676-6-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	2 months ago
Stefan Hajnoczi	ab57b51f13	scsi: save/load SCSI reservation state Add a vmstate subsection to SCSIDiskState so that scsi-block devices can transfer their reservation state during live migration. Upon loading the subsection, the destination QEMU invokes the PERSISTENT RESERVE OUT command's PREEMPT service action to atomically move the reservation from the source I_T nexus to the destination I_T nexus. This results in transparent live migration of SCSI reservations. This approach is incomplete since SCSI reservations are cooperative and other hosts could interfere. Neither the source QEMU nor the destination QEMU are aware of changes made by other hosts. The assumption is that reservation is not taken over by a third host without cooperation from the source host. I considered adding the vmstate subsection to SCSIDevice instead of SCSIDiskState, since reservations are part of the SCSI Primary Commands that other devices apart from disks could support. However, due to fragility of migrating reservations, we will probably limit support to scsi-block and maybe scsi-disk in the future. In the end, I think it makes sense to place this within scsi-disk.c. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20260129212035.219676-5-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	2 months ago
Stefan Hajnoczi	70f0e0cedb	scsi: track SCSI reservation state for live migration SCSI Persistent Reservations are stateful and external to the guest. In order to transparently move reservations to the destination host during live migration, it is necessary to track the state built up on the source host before migration. Only then can the destination host ensure an equivalent state is restored upon migration. Snoop on successful PERSISTENT RESERVE OUT commands and save the reservation key and reservation type. This will allow registered keys and reservations to be migrated. Also patch PERSISTENT RESERVE IN replies with the REPORT CAPABILITIES service action since features that involve the physical SCSI bus target ports must not be exposed to the guest (it sees a virtual SCSI bus). Usually this plays out as follows: 1. The guest invokes the REGISTER service action to register a reservation key on its I_T nexus. 2. The guest invokes the RESERVE service action to create a reservation using the previously-registered key. This commit implements the snooping and stores the reservation key and type (if any) for each LUN. The snooped PR state and the migrate_pr flag to enable PR migration will be used in later commits. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20260129212035.219676-4-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	2 months ago
Stefan Hajnoczi	6302598fe5	scsi: add error reporting to scsi_SG_IO() Report the details of the SG_IO ioctl failure if an Error pointer is provided. This information aids troubleshooting and will be used by the SCSI Persistent Reservations migration code. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20260129212035.219676-3-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>	2 months ago

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