This touches code in xen_enable_tpm() that is obviously wrong. Since
I don't know how to fix it properly, I'm adding a FIXME there.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20251119130855.105479-6-armbru@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20251119130855.105479-5-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
connect_thread_func() sets a variable to null, then error_propagate()s
an Error * to it. This is a roundabout way to assign the Error * to
it, so replace it by just that.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20251119130855.105479-4-armbru@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
bbram_bdrv_error() interpolates a "detail" string into a template with
error_setg_errno(), then reports the result with error_report().
Produces error messages with an unwanted '.':
BLK-NAME: BBRAM backstore DETAIL failed.: STERROR
Replace both calls of bbram_bdrv_error() by straightforward
error_report(), and drop the function. This is less code, easier to
read, and the error message is more greppable.
Also delete the unwanted '.'.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20251119130855.105479-3-armbru@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20251119130855.105479-2-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
* Removed the ast2700-a0 SoC and ast2700a0-evb machine.
* Added SGPIO support to the ast2700 SoC, including unit tests.
* Added several FRU EEPROMs to the Catalina board.
* Added support for the new AST1060 SoC and ast1060-evb machine,
including functional tests.
* Fixed the silicon revision ID register for AST2600 and AST1030 SoCs.
* Added an SFDP table for a Winbond flash chip.
* Updated documentation for Aspeed boards.
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Merge tag 'pull-aspeed-20260105' of https://github.com/legoater/qemu into staging
aspeed queue:
* Removed the ast2700-a0 SoC and ast2700a0-evb machine.
* Added SGPIO support to the ast2700 SoC, including unit tests.
* Added several FRU EEPROMs to the Catalina board.
* Added support for the new AST1060 SoC and ast1060-evb machine,
including functional tests.
* Fixed the silicon revision ID register for AST2600 and AST1030 SoCs.
* Added an SFDP table for a Winbond flash chip.
* Updated documentation for Aspeed boards.
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# gpg: Signature made Mon 05 Jan 2026 11:53:55 PM AEDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
* tag 'pull-aspeed-20260105' of https://github.com/legoater/qemu: (36 commits)
hw/i2c/aspeed: Fix wrong I2CC_DMA_LEN when I2CM_DMA_TX/RX_ADDR set first
hw/intc/aspeed: Remove TSP 128 - 138
hw/intc/aspeed: Remove SSP 128 - 138
docs/specs/aspeed-intc: Remove GIC 128 - 136
hw/intc/aspeed: Remove GIC 128 - 136
hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC
hw/arm: Remove ast2700a0-evb machine
tests/functional: Fix URL of gb200nvl-bmc image
test/qtest: Add Unit test for Aspeed SGPIO
hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC
hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers
hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling
hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins
hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO
hw/arm/aspeed: catalina: add Cable Cartridge FRU EEPROM
hw/arm/aspeed: catalina: add NIC FRU EEPROM
hw/arm/aspeed: catalina: add HMC FRU EEPROM
hw/arm/aspeed: catalina: add GB200-IO FRU EEPROM
hw/arm/aspeed: catalina: add GB200 FRU EEPROM
hw/arm/aspeed: catalina: add HDD FRU EEPROM
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
In the previous design, the I2C model would update I2CC_DMA_LEN (0x54) based on
the value of I2CM_DMA_LEN (0x1C) when the firmware set either I2CM_DMA_TX_ADDR
(0x30) or I2CM_DMA_RX_ADDR (0x34). However, this only worked correctly if the
firmware set I2CM_DMA_LEN before setting I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR.
If the firmware instead set I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR before setting
I2CM_DMA_LEN, the value written to I2CC_DMA_LEN would be incorrect.
To fix this issue, the model should be updated to set I2CC_DMA_LEN when the
firmware writes to the I2CM_DMA_LEN register, rather than when it writes to the
I2CM_DMA_RX_ADDR and I2CM_DMA_TX_ADDR registers.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: ba2cccd64e ("aspeed: i2c: Add new mode support")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260102090746.1130033-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260102090746.1130033-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260102090746.1130033-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The ast2700-a1 SOC represented the first revision of the AST2700 and
was intended as an early engineering sample rather than a production
platform. A newer revision, A1, is now supported, and the ast2700-a1
SOC should replace the older A0 version.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The ast2700a0-evb machine represents the first revision of the AST2700 and
serves as the initial engineering sample rather than a production version.
A newer revision, A1, is now supported, and the ast2700a1-evb should replace
the older A0 version.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-2-jamin_lin@aspeedtech.com
[ clg: Updated docs/about/removed-features.rst ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit [1] moved the FW image of the gb200nvl-bmc machine and broke
the associated functional test. Fix that.
[1] 52451b2472
Cc: Ed Tanous <etanous@nvidia.com>
Cc: Patrick Williams <patrick@stwcx.xyz>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20251222073351.166720-1-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit introduces a new qtest for the Aspeed SGPIO controller
The test covers the following:
- Setting and clearing SGPIO output pins and verifying the pin state.
- Setting and clearing SGPIO input pins and verifying the pin state.
- Verifying that level-high interrupts are correctly triggered and cleared.
Signed-off-by: Yubin Zou <yubinz@google.com>
Reviewed-by: Kane Chen <kane_chen@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-6-fd5593178144@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit updates the Aspeed SoC model to support two SGPIO
controllers, reflecting the hardware capabilities of the AST2700
The memory map and interrupt map are updated to include entries for
two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a
prerequisite for the full implementation of the SGPIO device model.
Signed-off-by: Yubin Zou <yubinz@google.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-4-fd5593178144@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The SGPIO controller can generate interrupts based on various pin state
changes, such as rising/falling edges or high/low levels. This change
adds the necessary logic to detect these events, update the interrupt
status registers, and signal the interrupt to the SoC.
Signed-off-by: Yubin Zou <yubinz@google.com>
Reviewed-by: Kane Chen <kane_chen@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-3-fd5593178144@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are
implemented to get and set the level of individual SGPIO pins. These
are then exposed as boolean properties on the SGPIO device object.
Signed-off-by: Yubin Zou <yubinz@google.com>
Reviewed-by: Kane Chen <kane_chen@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-2-fd5593178144@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This initial implementation includes the basic device structure,
memory-mapped register definitions, and read/write handlers for the
SGPIO control registers.
Signed-off-by: Yubin Zou <yubinz@google.com>
Reviewed-by: Kane Chen <kane_chen@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-1-fd5593178144@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate a Cable Cart image based on a
sanitized set of data from a real device EEPROM. The EEPROM
bus/address did not match device tree for one of the EEPROMs so move
it from bus 13 / 55 to bus 12 / 54.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-11-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate a CX-7 NIC image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-10-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate a GB200-IO image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-8-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate a GB200 image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-7-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate an FIO image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-5-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate an OSFP image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-4-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Use ipmitool/frugen tool to generate a DC-SCM image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-2-dc7b276efd57@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Added details describing AST1060 as a Platform Root of Trust processor board alongside
AST1030 MiniBMC, and extended the list of missing devices to include
SMBus Filter and QSPI Monitor controllers.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-13-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Remove the ast2700-evb entry from the Aspeed family boards list in
the documentation. The AST2700 platform now belongs to the new Aspeed
2700 family group, which has its own dedicated documentation section
and board definitions.
Update the Aspeed 2700 family boards list in the documentation to include
the new ast2700fc board entry.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-12-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Add functional tests for the Aspeed AST1060 SoC and its evaluation board.
The new test test_aspeed_ast1060.py validates booting the AST1060 EVB
machine using the Zephyr OS and ASPEED PROT application (ast1060_prot_v03.02.tgz)
and ensures basic console functionality.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-11-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Add a new machine definition ast1060-evb to support the Aspeed AST1060
evaluation board. The new EVB reuses the same MiniBMC framework used by
AST1030, as both SoCs share the same core peripherals and controller
designs.
The AST1060 EVB machine initializes the ast1060-a2 SoC and sets the
FMC and SPI flash models (w25q80bl and w25q02jvm) for simulation.
This enables QEMU to boot and emulate firmware images for AST1060-based
platforms.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most
of the AST1030 peripheral device models, as the two SoCs share nearly
the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC,
and SPI.
A new common initialization and realization framework (ast10x0_init
and ast10x0_realize) is leveraged so AST1060 can instantiate the
existing AST1030 models without redefining duplicate device types.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-9-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Refactor the AST10x0 common initialization to accept a socname
parameter.
The AST1030 model can be reused by AST1060 since they share most of the
same controllers. This approach allows AST1060 to leverage the existing
AST1030 initialization flow while keeping separate SoC-specific init
functions for components that differ.
This prepares the framework for AST1060 support, allowing it to reuse
AST1030 device models and initialization flow without code duplication.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-8-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Introduce a new common realize function aspeed_soc_ast10x0_realize()
for AST10x0 series SoCs. The shared initialization and realization logic
is now placed in this common function to improve code reuse and reduce
duplication between different SoCs in the same family.
The AST1030 realization function aspeed_soc_ast1030_realize() is
updated to call the new common routine and then perform realization of
its own specific devices such as LPC and PECI, which are not present on
future SoCs like AST1060.
This refactor simplifies maintenance and prepares the framework for
adding AST1060 support.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Introduce a new common initialization function
aspeed_soc_ast10x0_init() for AST10x0 series SoCs. This separates the
shared initialization logic from the AST1030-specific part, allowing
reuse by future SoCs such as AST1060.
The AST1060 does not include the LPC and PECI models, so the common
initializer is used for all shared modules, while
aspeed_soc_ast1030_init() adds initialization of LPC and PECI, which
are unique to AST1030.
This refactor improves code reuse and prepares the codebase for
supporting the AST1060 platform.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-6-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Add a new silicon revision constant AST1060_A2_SILICON_REV for the
AST1060 SoC. This allows the SCU model and related SoC layers to
identify and handle AST1060 A2 revision properly in the same way as
other Aspeed SoC families.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
According to the design of the AST2600, it has a Silicon Revision ID
Register, specifically SCU004 and SCU014, to set the Revision ID for the
AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is
set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was
used for SCU014. The value of "s->silicon_rev" is set by the SoC layer
via the "silicon-rev" property. This patch aligns both SCU004 and SCU014
to use "s->silicon_rev" for consistency and flexibility.
Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed
revision constant ("AST1030_A1_SILICON_REV"). This change updates it to
use the same "s->silicon_rev" property, ensuring that both SoCs follow
a consistent and configurable revision handling mechanism.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Add the SFDP data table for Winbond W25Q02JVM flash device. The table
was generated under Linux kernel by dumping the SFDP content using
the following command:
```
hexdump -v -e '8/1 "0x%02x, " "\n"' \
/sys/bus/spi/devices/spi0.0/spi-nor/sfdp
```
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
These functions don't "log" anything, they just generate the write
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Note there are two functions impacted
gen_log_vreg_write -> gen_vreg_write
gen_log_vreg_write_pair -> gen_vreg_write_pair
These functions don't "log" anything, they just generate the write
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The function doesn't "log" anything, it just generates the write
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The gen_log_reg_write function is a memnant of the original Hexagon
target design. With the addition of gen_analyze_funcs.py and the
ability to short-circuit a packet commit, this function can be
removed.
Note that the implementation of gen_log_reg_write contains a check
of the register mutability mask. This is only needed for control
registers, so we move it to gen_write_ctrl_reg.
We do need the gen_log_reg_write_pair function, but the name is
now misleading, so we change the name go gen_write_reg_pair.
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
I noticed that analyze_packet is marking the implicit pred reads after
marking all the writes. However, the semantics of the instrucion and
packet are to do all the reads, then do the operation, then do all the
writes.
Here is the old code
static void analyze_packet(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
ctx->read_after_write = false;
ctx->has_hvx_overlap = false;
for (int i = 0; i < pkt->num_insns; i++) {
Insn *insn = &pkt->insn[i];
ctx->insn = insn;
if (opcode_analyze[insn->opcode]) {
opcode_analyze[insn->opcode](ctx);
}
mark_implicit_reg_writes(ctx);
mark_implicit_pred_writes(ctx);
mark_implicit_pred_reads(ctx);
}
ctx->need_commit = need_commit(ctx);
}
Recall that opcode_analyze[insn->opcode](ctx) will mark all the
explicit reads then all the explicit writes.
To properly handle the semantics, we'll create two new functions
mark_implicit_reads
mark_implicit_writes
Then we change gen_analyze_funcs.py to add a call to the former
after all the explicit reads and a call to the latter after all
the explicit_writes.
The reason this is an RFC patch is I can't find any instructions
where this distinction makes a difference in ctx->need_commit which
determines if the packet commit can be short-circuited. However, this
could change in the future if the architecture introduces an
instruction with an implicit read of a register that is also written
(either implicit or explicit). Then, anlayze_packet would detect
a read-after-write, and the packet would not short-circuit. The
execution would be correct, but the performance would not be optimal.
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Tested-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-Id: <20250325021440.81386-1-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Implicit writes to USR are only to specific fields of USR to indicate
side effects (e.g., saturation overflow, floating point status).
In these cases, we don't force a packet commit. This will allow more
packets to be short-circuited (avoid writing the results to temporaries).
When there is a packet commit with an implicit write to USR, we initialize
new_value_usr during gen_start_packet and write to USR in gen_reg_writes.
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Markus Armbruster
Richard Henderson
Jamin Lin
Cédric Le Goater
Yubin Zou
Patrick Williams
Taylor Simpson