riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Philippe Mathieu-Daudé	bb6af0fa51	util/cacheflush: Avoid possible redundant dcache flush on Darwin <libkern/OSCacheControl.h> describes sys_icache_invalidate() as "equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)", having kCacheFunctionPrepareForExecution defined as: /* Prepare memory for execution. This should be called * after writing machine instructions to memory, before * executing them. It syncs the dcache and icache. [...] */ Since the dcache is also sync'd, we can avoid the sys_dcache_flush() call when both rx/rw pointers are equal. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230605195911.96033-1-philmd@linaro.org>	3 years ago
Philippe Mathieu-Daudé	0baf54d005	util/cacheflush: Use declarations from <OSCacheControl.h> on Darwin Per the cache(3) man page, sys_icache_invalidate() and sys_dcache_flush() are declared in <libkern/OSCacheControl.h>. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230605175647.88395-2-philmd@linaro.org>	3 years ago
Pierrick Bouvier	b3c3260295	util/cacheflush: fix cache on windows-arm64 ctr_el0 access is privileged on this platform and fails as an illegal instruction. Windows does not offer a way to flush data cache from userspace, and only FlushInstructionCache is available in Windows API. The generic implementation of flush_idcache_range uses, __builtin___clear_cache, which already use the FlushInstructionCache function. So we rely on that. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230221153006.20300-2-pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	3 years ago
Nicholas Piggin	c79a8e840c	util/cacheflush: Optimize flushing when ppc host has coherent icache On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates that we can use a simplified 3 instruction flush sequence. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220519141131.29839-1-npiggin@gmail.com> [rth: update after merging cacheflush.c and cacheinfo.c] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org>	4 years ago
Richard Henderson	bdd50dc7d0	util/cacheflush: Merge aarch64 ctr_el0 usage Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range, use the pre-computed line sizes from the global variables. Use CONFIG_DARWIN in preference to __APPLE__. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-3-richard.henderson@linaro.org>	4 years ago
Richard Henderson	7971375287	util: Merge cacheflush.c and cacheinfo.c Combine the two files into cacheflush.c. There's a couple of bits that would be helpful to share between the two, and combining them seems better than exporting the bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-2-richard.henderson@linaro.org>	4 years ago
Peter Maydell	ad768e6f2a	include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h The qemu_icache_linesize, qemu_icache_linesize_log, qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not used in many files. Move them out of osdep.h to a new qemu/cacheinfo.h, and document them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-5-peter.maydell@linaro.org	4 years ago
Gan Qixin	acd15fc2e8	util/cacheflush: Fix error generated by clang When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following error: ../util/cacheflush.c:38:44: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths] asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); ^ ../util/cacheflush.c:38:24: note: use constraint modifier "w" asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); ^~ %w0 Modify the type of save_ctr_el0 to uint64_t to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Gan Qixin <ganqixin@huawei.com> Message-Id: <20210115075656.717957-1-ganqixin@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>	5 years ago
Richard Henderson	664a79735e	util: Specialize flush_idcache_range for aarch64 For darwin, the CTR_EL0 register is not accessible, but there are system routines that we can use. For other hosts, copy the single pointer implementation from libgcc and modify it to support the double pointer interface we require. This halves the number of cache operations required when split-rwx is enabled. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 years ago
Richard Henderson	1da8de39a3	util: Enhance flush_icache_range with separate data pointer We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 years ago
Richard Henderson	084cfca143	util: Extract flush_icache_range to cacheflush.c This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	5 years ago

11 Commits (176e3783f2ab1476cdfd18a12bd2cfbe42e6b573)