riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Richard Henderson	0ea4120e39	ppc queue for 10.2 * Firmware updates for SLOF, sam460ex u-boot * Removal of unusable e200 CPUs * Coverity fixes for fadump * Other minor fixes, cleanups for pegasos, spapr. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmkDH0MACgkQRUTplPnW j7tRjQ/+JbtHt8v4liav4EXRMvM0b8ASDQZFtltC8cg/vpgy/CbYgqcltQDKC4+F NjBwSR4mKMTLX95LQsdFCLZY6FENKCirjpsCvHDxU9Hw/UdsVA12rFd/+lgytrTe yvJzyhUAoUMSFgpYGZSRQVV+eMEMgHBZekR2RLXwEeuLf/TOAdG+giCMM92Xs7bz petdqCspKvpw8RHjb2nyIh67RQ3zYVisU9/pczoNRytjQHYgllddXRt1/DOdF/Gi zREc7qE3biDg5jYgWScByy6EwBBBPqNbvR1GLjMV2rM77785KD9GsIzKCCzg6YQY CSN/fy8V4TXVkJn8nY2s3SHvBz3szNSvx/nL8sCyKXol/5Naha5CLN0ykz5VcrIf 9gNwifW22lHbAtvbmRY9yuTrao8RoQwEZ/3o8Te3W/U9iCFLnwCmKWb/3GT6i/kw yyJlUBuW5WASf5N+G0N7IB5BAwzoQQtd0WXW1ugXAFG+Bd/nkRvVkIf9sPWUxWJ/ 0Tx+2rPZOFzju8VYO8188wh/zDLuNRTEdfo+L21GMI2OBBEUO2nIiwPTLIMrCT4e ycC7Vvyu3IahX9ojIL9g0RhPH4K4JDbQuDnszp9SBGcgJYzwLh5Hb436A30A6qJE 7r5FTCiwtG27eMKCeZU3iBGpcj+g4kWIvmYEITsyCl8CxKv5+fs= =fzVo -----END PGP SIGNATURE----- Merge tag 'pull-ppc-for-10.2-d4-20251030' of https://gitlab.com/harshpb/qemu into staging ppc queue for 10.2 * Firmware updates for SLOF, sam460ex u-boot * Removal of unusable e200 CPUs * Coverity fixes for fadump * Other minor fixes, cleanups for pegasos, spapr. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmkDH0MACgkQRUTplPnW # j7tRjQ/+JbtHt8v4liav4EXRMvM0b8ASDQZFtltC8cg/vpgy/CbYgqcltQDKC4+F # NjBwSR4mKMTLX95LQsdFCLZY6FENKCirjpsCvHDxU9Hw/UdsVA12rFd/+lgytrTe # yvJzyhUAoUMSFgpYGZSRQVV+eMEMgHBZekR2RLXwEeuLf/TOAdG+giCMM92Xs7bz # petdqCspKvpw8RHjb2nyIh67RQ3zYVisU9/pczoNRytjQHYgllddXRt1/DOdF/Gi # zREc7qE3biDg5jYgWScByy6EwBBBPqNbvR1GLjMV2rM77785KD9GsIzKCCzg6YQY # CSN/fy8V4TXVkJn8nY2s3SHvBz3szNSvx/nL8sCyKXol/5Naha5CLN0ykz5VcrIf # 9gNwifW22lHbAtvbmRY9yuTrao8RoQwEZ/3o8Te3W/U9iCFLnwCmKWb/3GT6i/kw # yyJlUBuW5WASf5N+G0N7IB5BAwzoQQtd0WXW1ugXAFG+Bd/nkRvVkIf9sPWUxWJ/ # 0Tx+2rPZOFzju8VYO8188wh/zDLuNRTEdfo+L21GMI2OBBEUO2nIiwPTLIMrCT4e # ycC7Vvyu3IahX9ojIL9g0RhPH4K4JDbQuDnszp9SBGcgJYzwLh5Hb436A30A6qJE # 7r5FTCiwtG27eMKCeZU3iBGpcj+g4kWIvmYEITsyCl8CxKv5+fs= # =fzVo # -----END PGP SIGNATURE----- # gpg: Signature made Thu 30 Oct 2025 09:18:11 AM CET # gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB # gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined] # gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB * tag 'pull-ppc-for-10.2-d4-20251030' of https://gitlab.com/harshpb/qemu: hw/ppc/pegasos: Update documentation for pegasos1 hw/ppc/pegasos2: Rename to pegasos hw/ppc/pegasos2: Add /chosen/stdin node with VOF hw/ppc: Fix memory leak in get_cpu_state_data() hw/ppc: Fix missing return on allocation failure ppc/spapr: Cleanup MSI IRQ number handling target/ppc: Remove the unusable e200 CPUs target/ppc/cpu_init: Simplify the setup of the TLBxCFG SPR registers hw/ppc/sam460ex: Update u-boot-sam460ex pseries: Update SLOF firmware image to release 20251027 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Richard Henderson	c494afbb7d	nvme queue -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmkDE7gACgkQTeGvMW1P DekCOwgAuOQKWWW/UA1MmZ4ZHs+djf4q5UDwqGDx8tra8d32mZWRHgpJ/OBBOY2z CmuHqWLgooAqfx4hsrXELdNBEe7ccNE9nvsE3GjnYWxjoe51yl2Xc0RD5CZBVrN4 RRMbBZRCewxGShyUaT31eedolWdr4zBuqkpLf9gcG8Yk7YD+xUkHUPeMXeAy+vkS pxW59AkXdjJZgBktOdV5uVj9gaCPgTcGaQNH2FYSnzHwdu5VyV8BKiiZE/fXS6FU xZvu+5p1Ro5vOdwG+iFBrbBwcGyjVOF1OfBZctyc83foyFxwzxqoqj9gy0ewuT2g HsupUiJgbkZ1Ut9fzaS5pHx3dd3dKw== =WDrH -----END PGP SIGNATURE----- Merge tag 'pull-nvme-20251030' of https://gitlab.com/birkelund/qemu into staging nvme queue # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmkDE7gACgkQTeGvMW1P # DekCOwgAuOQKWWW/UA1MmZ4ZHs+djf4q5UDwqGDx8tra8d32mZWRHgpJ/OBBOY2z # CmuHqWLgooAqfx4hsrXELdNBEe7ccNE9nvsE3GjnYWxjoe51yl2Xc0RD5CZBVrN4 # RRMbBZRCewxGShyUaT31eedolWdr4zBuqkpLf9gcG8Yk7YD+xUkHUPeMXeAy+vkS # pxW59AkXdjJZgBktOdV5uVj9gaCPgTcGaQNH2FYSnzHwdu5VyV8BKiiZE/fXS6FU # xZvu+5p1Ro5vOdwG+iFBrbBwcGyjVOF1OfBZctyc83foyFxwzxqoqj9gy0ewuT2g # HsupUiJgbkZ1Ut9fzaS5pHx3dd3dKw== # =WDrH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 30 Oct 2025 08:28:56 AM CET # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'pull-nvme-20251030' of https://gitlab.com/birkelund/qemu: hw/nvme: add atomic boundary support hw/nvme: enable ns atomic writes hw/nvme: connect SPDM over NVMe Security Send/Recv spdm: define SPDM transport enum types hw/nvme: add NVMe Admin Security SPDM support spdm: add spdm storage transport virtual header spdm-socket: add seperate send/recv functions Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Richard Henderson	050b3d3630	loongarch queue -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaQLPjQAKCRAfewwSUazn 0c6EAP4wnAifbVCAMLxvMXtacIO7LomcdGDxXtwSh8l7GXvCtwD9E8MvJhrb7gMb tty5M+P2eIzOafaRHscarWLrnI01mAY= =zfDK -----END PGP SIGNATURE----- Merge tag 'pull-loongarch-20251030' of https://github.com/bibo-mao/qemu into staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaQLPjQAKCRAfewwSUazn # 0c6EAP4wnAifbVCAMLxvMXtacIO7LomcdGDxXtwSh8l7GXvCtwD9E8MvJhrb7gMb # tty5M+P2eIzOafaRHscarWLrnI01mAY= # =zfDK # -----END PGP SIGNATURE----- # gpg: Signature made Thu 30 Oct 2025 03:38:05 AM CET # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20251030' of https://github.com/bibo-mao/qemu: target/loongarch: Add PTW feature support in KVM mode linux-headers: Update to Linux v6.18-rc3 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Richard Henderson	5a572dd2cb	linux-user: permit sendto() with NULL buf and 0 len tests/functional: Mark the MIPS replay tests as flaky tests/functional: Mark the MIPS Debian Wheezy tests as flaky accel/tcg: Introduce and use MO_ALIGN_TLB_ONLY tcg: Simplify extract2 usage in tcg_gen_shifti_i64 -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmkEou4dHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/+/gf/XVoIbDCTgwt9hIbU azcxXgc+2kKpEK08OHTMA0Vfv06elR+ls5SXJuIV/ZvhM7amjOehs6rU5bX349Yi on901/zsa1woED6c3Jhp9FdQ3edFR8T3gvFaLIlhMoTHbe+CDRNHM7iYE5ASIdYx F2exgsZoUlcu12x5InttHvanC8lumLMBntlTnBgLZKjmW2tUehlMyAMRga0gyW5j EUG4v3frKI6rNMRSK6uE62I3paLvmU4zwlieCiqMtB5gT9+LKg//1Cfn149pLryj tuQ3kQfDZ9Lr5/18QtskfiTWnFoFx4xUyOHEQHUcmLpV/hvIBMq17pL+8ftcUdTB pjvzhg== =S/88 -----END PGP SIGNATURE----- Merge tag 'pull-misc-20251031' of https://gitlab.com/rth7680/qemu into staging linux-user: permit sendto() with NULL buf and 0 len tests/functional: Mark the MIPS replay tests as flaky tests/functional: Mark the MIPS Debian Wheezy tests as flaky accel/tcg: Introduce and use MO_ALIGN_TLB_ONLY tcg: Simplify extract2 usage in tcg_gen_shifti_i64 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmkEou4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/+/gf/XVoIbDCTgwt9hIbU # azcxXgc+2kKpEK08OHTMA0Vfv06elR+ls5SXJuIV/ZvhM7amjOehs6rU5bX349Yi # on901/zsa1woED6c3Jhp9FdQ3edFR8T3gvFaLIlhMoTHbe+CDRNHM7iYE5ASIdYx # F2exgsZoUlcu12x5InttHvanC8lumLMBntlTnBgLZKjmW2tUehlMyAMRga0gyW5j # EUG4v3frKI6rNMRSK6uE62I3paLvmU4zwlieCiqMtB5gT9+LKg//1Cfn149pLryj # tuQ3kQfDZ9Lr5/18QtskfiTWnFoFx4xUyOHEQHUcmLpV/hvIBMq17pL+8ftcUdTB # pjvzhg== # =S/88 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 31 Oct 2025 12:52:14 PM CET # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-misc-20251031' of https://gitlab.com/rth7680/qemu: linux-user: permit sendto() with NULL buf and 0 len tests/functional: Mark the MIPS Debian Wheezy tests as flaky tests/functional: Mark the MIPS replay tests as flaky tcg: Simplify extract2 usage in tcg_gen_shifti_i64 accel/tcg: Introduce and use MO_ALIGN_TLB_ONLY Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Peter Maydell	0db2de22fc	linux-user: permit sendto() with NULL buf and 0 len If you pass sendto() a NULL buffer, this is usually an error (causing an EFAULT return); however if you pass a 0 length then we should not try to validate the buffer provided. Instead we skip the copying of the user data and possible processing through fd_trans_target_to_host_data, and call the host syscall with NULL, 0. (unlock_user() permits a NULL buffer pointer for "do nothing" so we don't need to special case the unlock code.) Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3102 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20251028142001.3011630-1-peter.maydell@linaro.org>	5 months ago
Philippe Mathieu-Daudé	34117f03ed	tests/functional: Mark the MIPS Debian Wheezy tests as flaky test_malta.py sometimes times out (likely hang) under GitLab CI: 1/57 qemu:func-thorough+func-mips-thorough+thorough / func-mips-malta TIMEOUT 480.11s killed by signal 15 SIGTERM console.log shows a soft lockup failure: 06:46,426: INIT: version 2.88 booting 06:46,942: [[36minfo[39;49m] Using makefile-style concurrent boot in runlevel S. 06:47,378: findfs: unable to resolve 'UUID=042f1883-e9a5-4801-bb9b-667b5c8e87ea' 06:50,448: [....] Starting the hotplug events dispatcher: udevd[?25l[?1c7[1G[[32m ok [39;49m8[?25h[?0c. 06:52,269: [....] Synthesizing the initial hotplug events...module e1000: dangerous R_MIPS_LO16 REL relocation 07:17,707: BUG: soft lockup - CPU#0 stuck for 22s! [modprobe:208] 07:17,707: Modules linked in: 07:17,707: Cpu 0 07:17,708: $ 0 : 00000000 1000a400 0000003d 87808b00 07:17,708: $ 4 : 87808b00 87808bf0 00000000 00000000 07:17,709: $ 8 : 86862100 86862100 86862100 86862100 07:17,709: $12 : 86862100 00000000 00000001 86862100 07:17,709: $16 : 87808a00 86862100 1000a401 c008fa60 07:17,709: $20 : 86862100 8041d230 00000000 ffff0000 07:17,710: $24 : 00000000 77711470 07:17,710: $28 : 87bb6000 87bb7df8 8041d230 801f7388 07:17,710: Hi : 00000000 07:17,710: Lo : 00000000 07:17,711: epc : 801f7308 kfree+0x104/0x19c 07:17,711: Not tainted 07:17,711: ra : 801f7388 kfree+0x184/0x19c 07:17,712: Status: 1000a403 KERNEL EXL IE 07:17,712: Cause : 50808000 07:17,712: PrId : 00019300 (MIPS 24Kc) 07:45,707: BUG: soft lockup - CPU#0 stuck for 22s! [modprobe:208] 07:45,707: Modules linked in: Reported-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20251031094118.28440-3-philmd@linaro.org>	5 months ago
Philippe Mathieu-Daudé	1c11aa1807	tests/functional: Mark the MIPS replay tests as flaky MIPS test_replay.py often times out (likely hang) under GitLab CI: 2/21 qemu:func-thorough+func-mips64el-thorough+thorough / func-mips64el-replay TIMEOUT 180.12s killed by signal 15 SIGTERM The console.log file is empty, and recording.logs only shows: qemu-system-mips64el: terminating on signal 15 from pid 344 Since this is a long term issue affecting our CI, disable the tests. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20251031094118.28440-2-philmd@linaro.org>	5 months ago
Richard Henderson	170a39f8fb	tcg: Simplify extract2 usage in tcg_gen_shifti_i64 The else after the TCG_TARGET_HAS_extract2 test is exactly the same as what tcg_gen_extract2_i32 would emit itself. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	1 year ago
Richard Henderson	4dea00368d	accel/tcg: Introduce and use MO_ALIGN_TLB_ONLY For Arm, we need 3 cases: (1) the alignment required when accessing Normal memory, (2) the alignment required when accessing Device memory, and (3) the atomicity of the access. When we added TLB_CHECK_ALIGNED, we assumed that cases 2 and 3 were identical, and thus used memop_atomicity_bits for TLB_CHECK_ALIGNED. This is incorrect for multiple reasons, including that the atomicity of the access is adjusted depending on whether or not we are executing within a serial context. For Arm, what is true is that there is an underlying alignment requirement of the access, and for that access Normal memory will support unalignement. Introduce MO_ALIGN_TLB_ONLY to indicate that the alignment specified in MO_AMASK only applies when the TLB entry has TLB_CHECK_ALIGNED set; otherwise no alignment required. Introduce memop_tlb_alignment_bits with an additional bool argument that specifies whether TLB_CHECK_ALIGNED is set. All other usage of memop_alignment_bits assumes it is not. Remove memop_atomicity_bits as unused; it didn't properly support MO_ATOM_SUBWORD anyway. Update target/arm finalize_memop_atom to set MO_ALIGN_TLB_ONLY when strict alignment isn't otherwise required. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3171 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>	5 months ago
Richard Henderson	3728de3192	Various patches related to single binary work: - Make hw/arm/ common by adding a QOM type to machines to tag in which binary (32 or 64-bit) they can be used. Convert the Virt and SBSA-Ref machines. - Build Xen files once -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmkDbS4ACgkQ4+MsLN6t wN7LOQ/9HQSArWumcPtJNjfdKyN4BI+evdJuIsJlGnVirZzAShd/aA3emeVoIQXf kb1xAJvbL6IryasuFFrWJjLKAdTk8RgTzbDwSS07dEvNE/fVo22OarBfusrO+/fJ 6da3j08gwb0EV9m8eUbTwuRBxIF/tnPzZMzyRwx23b4wRb4jnIsshutHX9/hoZBj 8cdCJx284EZgj5gLTmk+jEyPEU+miKpnHWqpxSKZCXg7UfzXH34gOo6IBZIzylZs kJqcPXaJHF//ISMQQGzl7k1GNyr1fZZBIuCd7zdOIBntWjb45g/7lEKTGFaVrR5Y yqaUsNZNj8z3ESA4y42RUPSYAvjwGh+AKafZiHE6K7Oa/WIjeqfr33GHNSMrDYk1 UDz4o6/VhA/T7VaQjcd/IG9vYsF3jwjhbXQRa1xXKxhuIC0PzEKxpyWo3mAIEfm8 7vw90xx4no29WsUpKi6kyplJ/fq9o3h0kWpd6fYlJQsCtwVZFLT9UeBVIQHrfGec xkJx/L1OZFzym8Y4bcj0/V4zRJyvyuKK30+bFvu0fKcNR3uijKUjYcQHYg04fSG9 PgQtCgHxwdbO8vCwHf0WIVtOhqC0aOgtE10jh9HdLG07Ef5K1JBkE90XX27rCOV3 rAVo/czNnHpx2j0kRGpyRlz9M/eqOVcz4z3TFzKOFPEEumvz1MM= =Ncy4 -----END PGP SIGNATURE----- Merge tag 'single-binary-20251030' of https://github.com/philmd/qemu into staging Various patches related to single binary work: - Make hw/arm/ common by adding a QOM type to machines to tag in which binary (32 or 64-bit) they can be used. Convert the Virt and SBSA-Ref machines. - Build Xen files once # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmkDbS4ACgkQ4+MsLN6t # wN7LOQ/9HQSArWumcPtJNjfdKyN4BI+evdJuIsJlGnVirZzAShd/aA3emeVoIQXf # kb1xAJvbL6IryasuFFrWJjLKAdTk8RgTzbDwSS07dEvNE/fVo22OarBfusrO+/fJ # 6da3j08gwb0EV9m8eUbTwuRBxIF/tnPzZMzyRwx23b4wRb4jnIsshutHX9/hoZBj # 8cdCJx284EZgj5gLTmk+jEyPEU+miKpnHWqpxSKZCXg7UfzXH34gOo6IBZIzylZs # kJqcPXaJHF//ISMQQGzl7k1GNyr1fZZBIuCd7zdOIBntWjb45g/7lEKTGFaVrR5Y # yqaUsNZNj8z3ESA4y42RUPSYAvjwGh+AKafZiHE6K7Oa/WIjeqfr33GHNSMrDYk1 # UDz4o6/VhA/T7VaQjcd/IG9vYsF3jwjhbXQRa1xXKxhuIC0PzEKxpyWo3mAIEfm8 # 7vw90xx4no29WsUpKi6kyplJ/fq9o3h0kWpd6fYlJQsCtwVZFLT9UeBVIQHrfGec # xkJx/L1OZFzym8Y4bcj0/V4zRJyvyuKK30+bFvu0fKcNR3uijKUjYcQHYg04fSG9 # PgQtCgHxwdbO8vCwHf0WIVtOhqC0aOgtE10jh9HdLG07Ef5K1JBkE90XX27rCOV3 # rAVo/czNnHpx2j0kRGpyRlz9M/eqOVcz4z3TFzKOFPEEumvz1MM= # =Ncy4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 30 Oct 2025 02:50:38 PM CET # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'single-binary-20251030' of https://github.com/philmd/qemu: (23 commits) hw/riscv: Replace target_ulong uses hw/xen: Build only once hw/xen: Replace target_ulong by agnostic target_long_bits() hw/xen: Use BITS_PER_BYTE & MAKE_64BIT_MASK() in req_size_bits() hw/arm/meson: Move Xen files to arm_common_ss[] hw/arm/virt: Build only once hw/arm/virt-acpi-build: Build only once hw/arm/virt-acpi-build: Include missing 'cpu.h' header hw/arm/sbsa-ref: Build only once hw/arm/sbsa-ref: Include missing 'cpu.h' header hw/arm/virt: Get default CPU type at runtime hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() qemu/target_info: Add target_base_arm() helper qemu/target_info: Add target_aarch64() helper qemu/target_info: Add target_arm() helper hw/arm/virt: Check accelerator availability at runtime hw/arm/virt: Register valid CPU types dynamically config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) meson: Prepare to accept per-binary TargetInfo structure implementation hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Anton Johansson	dfbf777540	hw/riscv: Replace target_ulong uses Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20251027-feature-single-binary-hw-v1-v2-2-44478d589ae9@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	5 months ago
Philippe Mathieu-Daudé	ad9e070998	hw/xen: Build only once Now than hw/xen/ files don't use any target-specific code, we can build all file units once, removing the need for the xen_specific_ss[] source set. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20251022140114.72372-4-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	6e63a00522	hw/xen: Replace target_ulong by agnostic target_long_bits() Both are equivalent: target_long_bits() sizeof(target_u?long) * BITS_PER_BYTE Prefer the former which is target-agnostic. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20251022140114.72372-3-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	a1393a76ce	hw/xen: Use BITS_PER_BYTE & MAKE_64BIT_MASK() in req_size_bits() Replace magic 8 by BITS_PER_BYTE, use MAKE_64BIT_MASK() instead of open coding it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20251022140114.72372-2-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	8299515d64	hw/arm/meson: Move Xen files to arm_common_ss[] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210655.59278-1-philmd@linaro.org>	12 months ago
Philippe Mathieu-Daudé	5ec0236f63	hw/arm/virt: Build only once Previous commits removed the TARGET_AARCH64 uses in virt.c, we can now move it to arm_common_ss[] and build it once. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210934.60483-1-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	2b12ce6d39	hw/arm/virt-acpi-build: Build only once Previous commits removed the target-specificities, we can now move virt-acpi-build.c to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-9-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	fdda97b47e	hw/arm/virt-acpi-build: Include missing 'cpu.h' header "cpu.h" is indirectly pulled in by another header. Include it explicitly in order to avoid when changing default CPPFLAGS path: hw/arm/virt-acpi-build.c:903:34: error: call to undeclared function 'arm_feature'; 903 \| uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? \| ^ hw/arm/virt-acpi-build.c:903:53: error: incomplete definition of type 'ARMCPU' (aka 'struct ArchCPU') 903 \| uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? \| ~~~~~~^ include/qemu/typedefs.h:30:16: note: forward declaration of 'struct ArchCPU' 30 \| typedef struct ArchCPU ArchCPU; \| ^ hw/arm/virt-acpi-build.c:903:60: error: use of undeclared identifier 'ARM_FEATURE_PMU' 903 \| uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? \| ^ hw/arm/virt-acpi-build.c:993:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED' 993 \| case QEMU_PSCI_CONDUIT_DISABLED: \| ^ hw/arm/virt-acpi-build.c:996:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_HVC' 996 \| case QEMU_PSCI_CONDUIT_HVC: \| ^ hw/arm/virt-acpi-build.c:1000:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_SMC' 1000 \| case QEMU_PSCI_CONDUIT_SMC: \| ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-8-philmd@linaro.org>	7 months ago
Philippe Mathieu-Daudé	3b958ed662	hw/arm/sbsa-ref: Build only once Since previous commit allowed the use of accelerator definitions in common code, we can now move sbsa-ref.c to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-7-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	67b2ba55ad	hw/arm/sbsa-ref: Include missing 'cpu.h' header "cpu.h" is indirectly pulled in by another header. Include it explicitly in order to avoid when changing default CPPFLAGS path: hw/arm/sbsa-ref.c:162:25: error: use of undeclared identifier 'ARM_DEFAULT_CPUS_PER_CLUSTER' 162 \| uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; \| ^ hw/arm/sbsa-ref.c:163:12: error: call to undeclared function 'arm_build_mp_affinity' 163 \| return arm_build_mp_affinity(idx, clustersz); \| ^ hw/arm/sbsa-ref.c:746:25: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED' 746 \| sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; \| ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-6-philmd@linaro.org>	6 months ago
Philippe Mathieu-Daudé	e22ad85abd	hw/arm/virt: Get default CPU type at runtime Prefer MachineClass::get_default_cpu_type() over MachineClass::default_cpu_type to get CPU type, evaluating TCG availability at runtime calling tcg_enabled(). It's worth noting that this is a behavior change: - Previously only ./configure --disable-tcg --enable-kvm ./qemu-system-aarch64 -M virt -accel kvm would default to 'max' and ./configure --enable-tcg --enable-kvm ./qemu-system-aarch64 -M virt -accel kvm would default to 'cortex-a15'. - Afterward, -accel kvm will always default to 'max'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhang Chen <zhangckid@gmail.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-5-philmd@linaro.org>	12 months ago
Philippe Mathieu-Daudé	ebb643764b	hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Replace the target-specific TARGET_AARCH64 definition by a call to the generic target_aarch64() helper. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-4-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	43cc9efdc3	qemu/target_info: Add target_base_arm() helper Add a helper to check whether the target base architecture is ARM (either 32-bit or 64-bit). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-3-philmd@linaro.org>	11 months ago
Philippe Mathieu-Daudé	4306fc0f83	qemu/target_info: Add target_aarch64() helper Add a helper to distinct whether the binary is targetting Aarch64 or not. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-2-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	cc08d4d1c3	qemu/target_info: Add target_arm() helper Add a helper to distinct whether the binary is targetting ARM (32-bit only) or not. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210144.58108-1-philmd@linaro.org>	6 months ago
Philippe Mathieu-Daudé	9f5791334e	hw/arm/virt: Check accelerator availability at runtime It is not possible to call accelerator runtime helpers when QOM types are registered, because they depend on the parsing of the '-accel FOO' command line option, which happens after main(). Now than get_valid_cpu_types() is called after accelerator initializations, it is safe to call the accelerator helpers: main + configure_accelerators + qmp_x_exit_preconfig + qemu_init_board + machine_run_board_init + is_cpu_type_supported Replace compile-time check on CONFIG_{ACCEL} by runtime check on {accel}_enabled() helpers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021210840.60112-1-philmd@linaro.org>	12 months ago
Philippe Mathieu-Daudé	d4e3377c74	hw/arm/virt: Register valid CPU types dynamically Replace the static array returned as MachineClass::valid_cpu_types[] by a runtime one generated by MachineClass::get_valid_cpu_types() once the machine is created (its options being processed). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021211135.61179-1-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	1e18e343ce	config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Implement the TargetInfo structure for qemu-system-arm and qemu-system-aarch64 binaries. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021205741.57109-7-philmd@linaro.org>	12 months ago
Philippe Mathieu-Daudé	4dc7de81c2	meson: Prepare to accept per-binary TargetInfo structure implementation If a file defining the binary TargetInfo structure is available, link with it. Otherwise keep using the stub. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021205741.57109-6-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	38c5ab4003	hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Register machines to be able to run with the qemu-system-arm and qemu-system-aarch64 binaries, except few machines which are only available on the qemu-system-aarch64 binary: $ git grep TARGET_AARCH64 hw/arm/meson.build hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) $ git grep -W AARCH64 hw/arm/Kconfig hw/arm/Kconfig=185=config SBSA_REF hw/arm/Kconfig-186- bool hw/arm/Kconfig-187- default y hw/arm/Kconfig:188: depends on TCG && AARCH64 -- hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM hw/arm/Kconfig-414- bool hw/arm/Kconfig-415- default y if PIXMAN hw/arm/Kconfig:416: depends on TCG && AARCH64 -- hw/arm/Kconfig=435=config XLNX_VERSAL hw/arm/Kconfig-436- bool hw/arm/Kconfig-437- default y hw/arm/Kconfig:438: depends on TCG && AARCH64 -- hw/arm/Kconfig=475=config NPCM8XX hw/arm/Kconfig-476- bool hw/arm/Kconfig-477- default y hw/arm/Kconfig:478: depends on TCG && AARCH64 -- hw/arm/Kconfig=605=config FSL_IMX8MP_EVK hw/arm/Kconfig-606- bool hw/arm/Kconfig-607- default y hw/arm/Kconfig:608: depends on TCG && AARCH64 $ git grep -wW TARGET_AARCH64 hw/arm \| fgrep -4 MACHINE_TYPE_NAME ... hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64 hw/arm/aspeed.c-1940- }, { hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"), hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"), hw/arm/raspi.c:420:#ifdef TARGET_AARCH64 hw/arm/raspi.c-421- }, { hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"), hw/arm/raspi.c-429- }, { hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"), This can be verified as: $ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help) @@ -1,0 +2,3 @@ +xlnx-versal-virt AMD Versal Virtual development board (alias of amd-versal-virt) +amd-versal-virt AMD Versal Virtual development board +amd-versal2-virt AMD Versal Gen 2 Virtual development board @@ -4,0 +8,5 @@ +ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35) +ast2700-evb Aspeed AST2700 A1 EVB (Cortex-A35) (alias of ast2700a1-evb) +ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35) +ast2700fc ast2700 full core support (alias of ast2700fc) +ast2700fc ast2700 full core support @@ -20,0 +29 @@ +imx8mp-evk NXP i.MX 8M Plus EVK Board @@ -47,0 +57 @@ +npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35) @@ -60,0 +71,3 @@ +raspi3ap Raspberry Pi 3A+ (revision 1.0) +raspi3b Raspberry Pi 3B (revision 1.2) +raspi4b Raspberry Pi 4B (revision 1.5) @@ -66,0 +80 @@ +sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine @@ -99,0 +114 @@ +xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20251021205741.57109-5-philmd@linaro.org>	1 year ago
Richard Henderson	4889d96660	maintainer updates for 10.2 - clean-up remaining 32 bit armhf bits in ci - rationalise build-environment.yml for Debian and Ubuntu - generate a Debian ppc64 package list - rationalise gitlab-runner.yml for Debian and Ubuntu - new TCG plugin feature to track discontinuities - add missing CFI annotation to plugin callbacks - drop SBSA_REF from minimal Arm build - format string fix for gdbstub syscall response - simplify the gdbstub flen handling for semihosting -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmkCInQACgkQ+9DbCVqe KkSZRwf/ReHIqQMxf8TqthskX8PLGUvsvWMkJptpu0Yc4HyU6DSjdPbU4L0tOmLU ss2sb+dZncp1iRxHpqOhPJ+a987RHHzFbz2GQ/nV37D7BTwtq0iID4SxmdfiYOAm VVm/WQ0HMjIYY84rzfE6U/3H+FgL+GaPbB0WYa5CtKpMOHMl4gJgoSsxljXQrmYe BCC+Z9loVUAnKVVM5BUMP/0Agfn0CUZlUHGEn6RvmNg81dJ5DWCfO9yW1EezLZmc PhS/txAWrpTqktPxN4h+um8ILvej5FF8nnNCsxodxD1XZImWsxawxcQAcgQQJGWu dFLBMre7QSM1ddIOgdyZt+zuDcpUiA== =QEqf -----END PGP SIGNATURE----- Merge tag 'pull-10.2-maintainer-291025-1' of https://gitlab.com/stsquad/qemu into staging maintainer updates for 10.2 - clean-up remaining 32 bit armhf bits in ci - rationalise build-environment.yml for Debian and Ubuntu - generate a Debian ppc64 package list - rationalise gitlab-runner.yml for Debian and Ubuntu - new TCG plugin feature to track discontinuities - add missing CFI annotation to plugin callbacks - drop SBSA_REF from minimal Arm build - format string fix for gdbstub syscall response - simplify the gdbstub flen handling for semihosting # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmkCInQACgkQ+9DbCVqe # KkSZRwf/ReHIqQMxf8TqthskX8PLGUvsvWMkJptpu0Yc4HyU6DSjdPbU4L0tOmLU # ss2sb+dZncp1iRxHpqOhPJ+a987RHHzFbz2GQ/nV37D7BTwtq0iID4SxmdfiYOAm # VVm/WQ0HMjIYY84rzfE6U/3H+FgL+GaPbB0WYa5CtKpMOHMl4gJgoSsxljXQrmYe # BCC+Z9loVUAnKVVM5BUMP/0Agfn0CUZlUHGEn6RvmNg81dJ5DWCfO9yW1EezLZmc # PhS/txAWrpTqktPxN4h+um8ILvej5FF8nnNCsxodxD1XZImWsxawxcQAcgQQJGWu # dFLBMre7QSM1ddIOgdyZt+zuDcpUiA== # =QEqf # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 Oct 2025 03:19:32 PM CET # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-10.2-maintainer-291025-1' of https://gitlab.com/stsquad/qemu: (35 commits) semihosting: Fix GDB File-I/O FLEN gdbstub: Fix %s formatting configs: drop SBSA_REF from minimal specification plugins/core: add missing QEMU_DISABLE_CFI annotations tests: add test with interrupted memory accesses on rv64 tests: add test for double-traps on rv64 tests: add plugin asserting correctness of discon event's to_pc target/xtensa: call plugin trap callbacks target/tricore: call plugin trap callbacks target/sparc: call plugin trap callbacks target/sh4: call plugin trap callbacks target/s390x: call plugin trap callbacks target/rx: call plugin trap callbacks target/riscv: call plugin trap callbacks target/ppc: call plugin trap callbacks target/openrisc: call plugin trap callbacks target/mips: call plugin trap callbacks target/microblaze: call plugin trap callbacks target/m68k: call plugin trap callbacks target/loongarch: call plugin trap callbacks ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Richard Henderson	12688b0037	Xilinx queue -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEErET+3BT38evtv0FRKcWWeA9ryoMFAmkCDzgACgkQKcWWeA9r yoMxwAf/YRf8aNwn8+4MRAn5vuNI/Hyh75/Mu5m007fqU/gLEZxxzJQ0Jxrc5Oot tNqGBGnVsRmH7i7Kkn+Ch4GOozIEJkXmqeQ3brmCg1VvSgi2vtqvS9F3SK8U3I6j pavSC04KOtu33jlN63ObU+aAD/o5gLVwl2wAk+w0SWnnN4IhvPOilO7+ZeF5Lueh GH57sh9DRnMYJl4mOj5z5NDsgZhdnmjpvAkvWBI9cQ7uwhGXLk0lCu0+lJ25tr3T NAg6N4S94rCm0eaMKL79BHPuG59G3A5G8SOjn6pXkT2aYaaeHpqu2DcuFJsSsVxV 4CTignh5SVwICueFF4Z3RF5iZGHIDw== =ua+I -----END PGP SIGNATURE----- Merge tag 'edgar/xilinx-queue-2025-10-29.for-upstream' of https://gitlab.com/edgar.iglesias/qemu into staging Xilinx queue # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEErET+3BT38evtv0FRKcWWeA9ryoMFAmkCDzgACgkQKcWWeA9r # yoMxwAf/YRf8aNwn8+4MRAn5vuNI/Hyh75/Mu5m007fqU/gLEZxxzJQ0Jxrc5Oot # tNqGBGnVsRmH7i7Kkn+Ch4GOozIEJkXmqeQ3brmCg1VvSgi2vtqvS9F3SK8U3I6j # pavSC04KOtu33jlN63ObU+aAD/o5gLVwl2wAk+w0SWnnN4IhvPOilO7+ZeF5Lueh # GH57sh9DRnMYJl4mOj5z5NDsgZhdnmjpvAkvWBI9cQ7uwhGXLk0lCu0+lJ25tr3T # NAg6N4S94rCm0eaMKL79BHPuG59G3A5G8SOjn6pXkT2aYaaeHpqu2DcuFJsSsVxV # 4CTignh5SVwICueFF4Z3RF5iZGHIDw== # =ua+I # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 Oct 2025 01:57:28 PM CET # gpg: using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown] # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * tag 'edgar/xilinx-queue-2025-10-29.for-upstream' of https://gitlab.com/edgar.iglesias/qemu: target/microblaze: Handle signed division overflows target/microblaze: div: Break out raise_divzero() target/microblaze: Remove unused arg from check_divz() Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
Richard Henderson	0979667049	Block layer patches - Expose block limits in monitor and qemu-img info - Resize: Refresh filter node size when its child was resized - Support configuring stats-intervals in -device (instead of only -drive) - luks: Fix QMP x-blockdev-amend crash and image creation with detached-header - iotests: Several test case fixes - Code cleanups -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmkCAkIRHGt3b2xmQHJl ZGhhdC5jb20ACgkQfwmycsiPL9a3bA/+MMS9ocOyEiE4u66XbhQ4KgqxECtD/uzg 3lYQJbfVpphizq0QQn1pAno9rpjdWnkwPv9TasAEM/9R/wz/ygjmXM9GyQDvNLoB t6dTyWKpsi4lVB7FNPBNQvyz7mHqWQULrhI/mNGLsbiss32SMiE08amjOzSrFSZJ zn8TsEzDB218Bv8OBH/eI1mMvZ2gG6+yzPf7znA5nSOtJkG1kGLPInZuRgeN7e7W DUl5EeiP3sGZh4pF/IyRc8BNMsvPR7Lk31PrPEXAz+7g0y8dfPukrcR0nY6nwekT omPhbIBfDOEKpYdBxheOdh9TkT40Fo2Oc7DIhzY4at3O02BKy60kJSZaqoWj+80L A3yJ1K7wgiwqzOw0VaHU56Y5awnD5cculciwHxrfc6OHnG9cotvCSxsU2qr/UMd2 N/cPhUDKfWcilVoRNy+yYiubQsp2s4amF2uGDn/QjjZx0c3dgfXc9BCNmu9nbAMr UsmzZBH9GCpaTajVIsX8RdnaovMTxGr4UFyuSQ2jWYWp3k2BR89jkBpXReGGOYr6 SuEOOnx/E1duTZUPq1gdSkQm9uGxxq5FSGIWR+rWMdFkZS09HStmq5hcY+Zx0pSg JzDaLgPATV65y0VswFVUj6NemmNU983DwKPACwVCpemeBETtVuoU/CydzEPPwiL6 Kl5ISmjZz3I= =v2BI -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging Block layer patches - Expose block limits in monitor and qemu-img info - Resize: Refresh filter node size when its child was resized - Support configuring stats-intervals in -device (instead of only -drive) - luks: Fix QMP x-blockdev-amend crash and image creation with detached-header - iotests: Several test case fixes - Code cleanups # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCgAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmkCAkIRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9a3bA/+MMS9ocOyEiE4u66XbhQ4KgqxECtD/uzg # 3lYQJbfVpphizq0QQn1pAno9rpjdWnkwPv9TasAEM/9R/wz/ygjmXM9GyQDvNLoB # t6dTyWKpsi4lVB7FNPBNQvyz7mHqWQULrhI/mNGLsbiss32SMiE08amjOzSrFSZJ # zn8TsEzDB218Bv8OBH/eI1mMvZ2gG6+yzPf7znA5nSOtJkG1kGLPInZuRgeN7e7W # DUl5EeiP3sGZh4pF/IyRc8BNMsvPR7Lk31PrPEXAz+7g0y8dfPukrcR0nY6nwekT # omPhbIBfDOEKpYdBxheOdh9TkT40Fo2Oc7DIhzY4at3O02BKy60kJSZaqoWj+80L # A3yJ1K7wgiwqzOw0VaHU56Y5awnD5cculciwHxrfc6OHnG9cotvCSxsU2qr/UMd2 # N/cPhUDKfWcilVoRNy+yYiubQsp2s4amF2uGDn/QjjZx0c3dgfXc9BCNmu9nbAMr # UsmzZBH9GCpaTajVIsX8RdnaovMTxGr4UFyuSQ2jWYWp3k2BR89jkBpXReGGOYr6 # SuEOOnx/E1duTZUPq1gdSkQm9uGxxq5FSGIWR+rWMdFkZS09HStmq5hcY+Zx0pSg # JzDaLgPATV65y0VswFVUj6NemmNU983DwKPACwVCpemeBETtVuoU/CydzEPPwiL6 # Kl5ISmjZz3I= # =v2BI # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 Oct 2025 01:02:10 PM CET # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: qemu-img info: Add cache mode option qemu-img info: Optionally show block limits block: Expose block limits for images in QMP block: Improve comments in BlockLimits iotests: add test for resizing a 'file' node below a 'raw' node iotests: add test for resizing a node below filters block: implement 'resize' callback for child_of_bds class block: make bdrv_co_parent_cb_resize() a proper IO API function include/block/block_int-common: document when resize callback is used MAINTAINERS: Mark VHDX block driver as "Odd Fixes" block: enable stats-intervals for storage devices iotests: Adjust fuse-allow-other expected output iotests: Adjust nbd expected outputs to match current behavior block/curl.c: Fix CURLOPT_VERBOSE parameter type block/monitor: Use hmp_handle_error to report error block: fix luks 'amend' when run in coroutine block: remove 'detached-header' option from opts after use tests/qemu-iotests: Mark the 'inactive-node-nbd' as unsupported with -luks Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 months ago
BALATON Zoltan	5795c7650e	hw/ppc/pegasos: Update documentation for pegasos1 Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/f86b90f6839a0cf9426c0d89e95e6ca33704728c.1761346145.git.balaton@eik.bme.hu Message-ID: <f86b90f6839a0cf9426c0d89e95e6ca33704728c.1761346145.git.balaton@eik.bme.hu>	5 months ago
BALATON Zoltan	b943bb3ce9	hw/ppc/pegasos2: Rename to pegasos Now that we also emulate pegasos1 it is not only about pegasos2 so rename to a more generic name encompassing both. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/275cd2d5074b76b4a504a01f658e85ed7994ea3e.1761346145.git.balaton@eik.bme.hu Message-ID: <275cd2d5074b76b4a504a01f658e85ed7994ea3e.1761346145.git.balaton@eik.bme.hu>	5 months ago
BALATON Zoltan	bd7bf827bb	hw/ppc/pegasos2: Add /chosen/stdin node with VOF Some very old Linux kernels fail to start if /chosen/stdin is not found so add it to the device tree when using VOF. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/642ef77674d08ba466e7a2beb4858ab1e67776ae.1761346145.git.balaton@eik.bme.hu Message-ID: <642ef77674d08ba466e7a2beb4858ab1e67776ae.1761346145.git.balaton@eik.bme.hu>	5 months ago
Shivang Upadhyay	ec2b08c74d	hw/ppc: Fix memory leak in get_cpu_state_data() Fixes coverity (CID 1642024) Cc: Aditya Gupta <adityag@linux.ibm.com> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/CAFEAcA_Bm52bkPi9MH_uugXRR5fj48RtpbOnPNFQtbX=7Mz_yw@mail.gmail.com/ Reported-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20251028080551.92722-3-shivangu@linux.ibm.com Message-ID: <20251028080551.92722-3-shivangu@linux.ibm.com>	5 months ago
Shivang Upadhyay	4a0ebccf92	hw/ppc: Fix missing return on allocation failure Fixes coverity (CID 1642026) Cc: Aditya Gupta <adityag@linux.ibm.com> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/CAFEAcA-SPmsnU1wzsWxBcFC=ZM_DDhPEg1N4iX9Q4bL1xOnwBg@mail.gmail.com/ Reported-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20251028080551.92722-2-shivangu@linux.ibm.com Message-ID: <20251028080551.92722-2-shivangu@linux.ibm.com>	5 months ago
Yoges Vyas	552e329910	ppc/spapr: Cleanup MSI IRQ number handling Now that spapr_irq_nr_msis() returns a constant value, lets replace it with a macro. Ref: https://lore.kernel.org/qemu-devel/bf149815-9782-4964-953d-73658b1043c9@linux.ibm.com/ Suggested-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Yogesh Vyas <yvyas1991@gmail.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20251026074852.53691-1-yvyas1991@gmail.com Message-ID: <20251026074852.53691-1-yvyas1991@gmail.com>	5 months ago
Thomas Huth	984432c505	target/ppc: Remove the unusable e200 CPUs There is currently no machine in QEMU (except the "none" machine) that can be run with with one of the e200 ppc CPUs - all machines either complain about an invalid CPU type or crash QEMU immediately. Looking at the history of this CPU type, it seems like it has never been used in QEMU and only implemented as a placeholder (see e.g. the comment about unimplemented instructions in the POWERPC_FAMILY(e200) section of cpu_init.c). Being completely unused and unusable since such a long time, let's just remove it now (without deprecation phase, since there were no users of this dead code anyway). Note: The init_excp_e200() is used by the e500 CPUs, too, so we rename this function to init_excp_e500() instead of removing it. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20251024065726.738005-3-thuth@redhat.com Message-ID: <20251024065726.738005-3-thuth@redhat.com>	5 months ago
Thomas Huth	14e4390a32	target/ppc/cpu_init: Simplify the setup of the TLBxCFG SPR registers The next commit is going to remove init_proc_e200(), which is one of the two calling sites of register_BookE206_sprs(). This causes recent versions of GCC to inline the register_BookE206_sprs() function into the other only remaining calling site, init_proc_e500(), which in turn causes some false-positives compiler warnings: In file included from ../../devel/qemu/target/ppc/cpu_init.c:46: In function ‘register_BookE206_sprs’, inlined from ‘init_proc_e500’ at ../../devel/qemu/target/ppc/cpu_init.c:2910:5: ../../devel/qemu/target/ppc/cpu_init.c:897:29: error: array subscript 3 is outside array bounds of ‘uint32_t[2]’ {aka ‘unsigned int[2]’} [-Werror=array-bounds=] 897 \| tlbncfg[3]); \| ~~~~~~~^~~ ../../devel/qemu/target/ppc/spr_common.h:61:39: note: in definition of macro ‘spr_register_kvm_hv’ 61 \| KVM_ARG(one_reg_id) initial_value) \| ^~~~~~~~~~~~~ ../../devel/qemu/target/ppc/spr_common.h:77:5: note: in expansion of macro ‘spr_register_kvm’ 77 \| spr_register_kvm(env, num, name, uea_read, uea_write, \ \| ^~~~~~~~~~~~~~~~ ../../devel/qemu/target/ppc/cpu_init.c:894:9: note: in expansion of macro ‘spr_register’ 894 \| spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", \| ^~~~~~~~~~~~ ../../devel/qemu/target/ppc/cpu_init.c: In function ‘init_proc_e500’: ../../devel/qemu/target/ppc/cpu_init.c:2809:14: note: at offset 12 into object ‘tlbncfg’ of size 8 2809 \| uint32_t tlbncfg[2]; \| ^~~~~~~ cc1: all warnings being treated as errors init_proc_e500() only defines "uint32_t tlbncfg[2];", but it is OK since it also sets "env->nb_ways = 2", so the code that GCC warns about in register_BookE206_sprs() is never reached. Unfortunately, GCC is not smart enough to see this, so it emits these warnings. To fix it, let's simplify the code in register_BookE206_sprs() a little bit to set up the SPRs in a loop, so we don't reference the tlbncfg[3] entry directly anymore. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20251024065726.738005-2-thuth@redhat.com Message-ID: <20251024065726.738005-2-thuth@redhat.com>	5 months ago
BALATON Zoltan	2a62bbf4ed	hw/ppc/sam460ex: Update u-boot-sam460ex Update the sam460ex firmware to match 2015.c version from the machine vendor which fixes USB devices and some other bugs. Also cherry pick some commits from upstream U-Boot that moves licenses in a subdir and allows gitlab to correctly detect and show license information. Drop version number from the binary name to avoid needing to change it in case of future updates. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20251028151923.10DBB5972E5@zero.eik.bme.hu> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>	5 months ago
Thomas Huth	f551663d02	pseries: Update SLOF firmware image to release 20251027 - Fix some measurements in the TPM code - Fix for compiling with GCC in C23 mode - Silence some initializer-string warnings with recent GCC Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20251027074404.25758-1-thuth@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>	5 months ago
Alan Adamson	bce51b8370	hw/nvme: add atomic boundary support Add support for the namespace atomic boundary paramters: NABO, NABSN, and NABSPF. Writes that cross an atomic boundary whose size is less than or equal to values reported by AWUN/AWUPF are guaranteed to be atomic. If AWUN/AWUPF is set to zero, writes that cross an atomic boundary are not guaranteed to be atomic. The value reported by NABO field indicates the LBA on this namespace where the first atomic boundary starts. New NVMe QEMU Paramters (See NVMe Specification for details): atomic.nabo=UINT16 (default: 0) atomic.nabsn=UINT16 (default: 0) atomic.nabspf=UINT16 (default: 0) See the NVMe Specification for more information. Signed-off-by: Alan Adamson <alan.adamson@oracle.com> Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	10 months ago
Alan Adamson	3b41acc962	hw/nvme: enable ns atomic writes Add support for the namespace atomic paramters: NAWUN and NAWUN. Namespace Atomic Compare and Write Unit (NACWU) is not currently supported. Writes that adhere to the NACWU and NAWUPF parameters are guaranteed to be atomic. New NVMe QEMU Paramters (See NVMe Specification for details): atomic.nawun=UINT16 (default: 0) atomic.nawupf=UINT16 (default: 0) atomic.nsfeat (default off) - Set Namespace Supported Atomic Boundary & Power (NSABP) bit in Namespace Features (NSFEAT) in the Identify Namespace Data Structure See the NVMe Specification for more information. Signed-off-by: Alan Adamson <alan.adamson@oracle.com> Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	10 months ago
Wilfred Mallawa	7f2eeccb4b	hw/nvme: connect SPDM over NVMe Security Send/Recv This patch extends the existing support we have for NVMe with only DoE to also add support to SPDM over the NVMe Security Send/Recv commands. With the new definition of the `spdm-trans` argument, users can specify `spdm_trans=nvme` or `spdm_trans=doe`. This allows us to select the SPDM transport respectively. SPDM over the NVMe Security Send/Recv commands are defined in the DMTF DSP0286. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> [k.jensen: fix declaration in case statement; fix quotes in docs] Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	6 months ago
Wilfred Mallawa	3d8412c2fb	spdm: define SPDM transport enum types SPDM maybe used over different transports. This patch specifies the trasnport types as an enum with a qdev property definition such that a user input transport type (string) can be mapped directly into the respective SPDM transportenum for internal use. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	6 months ago
Wilfred Mallawa	e5534abeb4	hw/nvme: add NVMe Admin Security SPDM support Adds the NVMe Admin Security Send/Receive command support with support for DMTFs SPDM. The transport binding for SPDM is defined in the DMTF DSP0286. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	6 months ago
Wilfred Mallawa	64a9336a41	spdm: add spdm storage transport virtual header This header contains the transport encoding for an SPDM message that uses the SPDM over Storage transport as defined by the DMTF DSP0286. Note that in the StorageSpdmTransportHeader structure, security_protocol field is defined in the SCSI Primary Commands 5 (SPC-5) specification. The NVMe specification also refers to the SPC-5 for this definition. The security_protocol_specific field is defined in DSP0286 and is referred to as SP Specific for NVMe and ATA. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	6 months ago
Wilfred Mallawa	169e8d0c4b	spdm-socket: add seperate send/recv functions This is to support uni-directional transports such as SPDM over Storage. As specified by the DMTF DSP0286. Also update spdm_socket_rsp() to use the new send()/receive() functions. For the case of spdm_socket_receive(), this allows us to do error checking in one place with the addition of spdm_socket_command_valid(). Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>	6 months ago

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