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${ noResults }
1812 Commits (master)
| Author | SHA1 | Message | Date |
|---|---|---|---|
|
|
9eef3854d3 |
tests/qtest: Do not use versioned pc-q35-5.0 machine anymore
As of QEMU v10.2.0, the v5.0.0 machines are not usable anymore. Use the latest x86 q35 machine instead, otherwise we get: $ qemu-system-x86_64 -M pc-q35-5.0 qemu-system-x86_64: unsupported machine type: "pc-q35-5.0" Use -machine help to list supported machines See commit |
3 months ago |
|
|
11e06ae0b5 |
tests/qtest/migration: Pass MigrateStart into cancel tests
Pass the "args" parameter to the cancel tests so they can access the config object which will be part of this struct. Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251215220041.12657-27-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
3 months ago |
|
|
6fea394aa6 |
tests/qtest/migration: Pass MigrateCommon into test functions
With the upcoming addition of the config QDict, the tests will need a better way of managing the memory of the test data than putting the test arguments on the stack of the test functions. The config QDict will need to be merged into the arguments of migrate_qmp* functions, which causes a refcount increment, so the test functions would need to allocate and deref the config QDict themselves. A better approach is to already pass the arguments into the test functions and do the memory management in the existing wrapper. There is already migration_test_destroy(), which is called for every test. Do the following: - merge the two existing wrappers, migration_test_wrapper() and migration_test_wrapper_full(). The latter was pioneer in passing data into the tests, but now all tests will receive data, so we don't need it anymore. The usage of migration_test_wrapper_full() was in passing a slightly different test name string into the cancel tests, so still keep the migration_test_add_suffix() function. - add (char *name, MigrateCommon *args) to the signature of all test functions. - alter any code to stop allocating args on the stack and instead use the object that came as parameter. - pass args around as needed. - while here, order args (MigrateCommon) before args->start (MigrateStart) and put a blank like in between. No functional change. Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251215220041.12657-26-farosas@suse.de [peterx: fix a conflict with newly added mapped-ram+ignore-share test] Signed-off-by: Peter Xu <peterx@redhat.com> |
3 months ago |
|
|
df9c38b19a |
tests/qtest/migration: Add a NULL parameters test for TLS
Make sure the TLS options handling is working correctly with a NULL parameter. This is relevant due to the usage of StrOrNull for the tls-creds, tls-authz and tls-hostname options. With this, all manners of passing TLS options are somehow covered by the tests, we should not need to do manual testing when touching TLS options code. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20251215220041.12657-5-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
3 months ago |
|
|
b043f6df27 |
migration: fix parsing snapshots with x-ignore-shared flag
Snapshots made with mapped-ram and x-ignore-shared flags are not parsed properly. The ignore-shared feature adds and extra field in the stream, which needs to be consumed on the destination side. Even though mapped-ram has a fixed header format, the ignore-shared is part of the "generic" stream infomation so the mapped-ram code is currently skipping that be64 read which incorrectly offsets every subsequent read from the stream. The current ignore-shared handling can simply be moved earlier in the code to encompass mapped-ram as well since the ignore-shared doubleword is the first one read when parsing the ramblock section of the stream. Co-authored-by: Peter Xu <peterx@redhat.com> Signed-off-by: Pawel Zmarzly <pzmarzly0@gmail.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251126121233.542473-1-pzmarzly0@gmail.com [peterx: enhance commit log per fabiano] Signed-off-by: Peter Xu <peterx@redhat.com> |
4 months ago |
|
|
bd3ba0d342 |
hw/nvme: Validate PMR memory size
Per the PCI spec 3.0, in section 6.2.5.1, "Address Maps": A 32-bit register can be implemented to support a single memory size that is a power of 2 from 16 bytes to 2 GB. Add a check in nvme_init_pmr(), returning an error if the PMR region size is too small; and update the QTest. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com> |
4 months ago |
|
|
6aef825073 |
tests/migration-test: Use MEM_TYPE_MEMFD for memory_backend
The only two users of memory_backend as of now (cpr-exec, cpr-transfer) uses memfd as backend, now we fully support it. We can move memory_backend usage to mem_type and drop it. Reviewed-by: Juraj Marcin <jmarcin@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251117223908.415965-5-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> |
4 months ago |
|
|
c2f2470e31 |
tests/migration-test: Add MEM_TYPE_SHMEM
Add memfd support for mem_type. Will be used to replace memory_backend. Reviewed-by: Juraj Marcin <jmarcin@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251117223908.415965-4-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> |
4 months ago |
|
|
b1d67d86db |
tests/migration-test: Merge shmem_opts into memory_backend
The two parameters are more or less duplicated in migrate_args(). They all describe the memory type. When one is used, the other is not. mem_type currently uses numa parameter to specify the memory backend, while memory_backend (the two users of such uses "-machine memory-backend=ID"). This patch merges the use of the two variables so that we always generate a memory object string and put it into "memory_backend" variable. Now we can drop shmem_opts parameter in the function. Meanwhile we always use a memory-backend-* no matter which mem type is used. This brings mem_type to be aligned with memory_backend usage, then we stick with this as this is flexible enough. This paves way that we merge mem_type and memory_backend in MigrateStart. Reviewed-by: Juraj Marcin <jmarcin@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251117223908.415965-3-peterx@redhat.com [peterx: move MEM_TYPE_ANON case upper, per juraj] Signed-off-by: Peter Xu <peterx@redhat.com> |
4 months ago |
|
|
b187a183b1 |
tests/migration-test: Introduce MemType
Some migration tests need to be run with shmem, the rest by default use anonymous memory. Introduce MemType and replace use_shmem with such a enumeration. This prepares for a 3rd type of memory to be tested for migration. Careful readers may also already notice that MigrateStart has another field called memory_backend, which makes the whole "memory type" definition convoluted. That'll be merged into MemType soon in a follow up patch. When doing this, introduce some migrate_mem_type_*() helpers to do the work for each memory type. Reviewed-by: Juraj Marcin <jmarcin@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20251117223908.415965-2-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> |
4 months ago |
|
|
168558ed7b |
tests: Clean up includes
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git tests tests with one hand-edit to remove a now-empty #ifndef WIN32...#endif from tests/qtest/dbus-display-test.c . All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-id: 20251104160943.751997-10-peter.maydell@linaro.org |
5 months ago |
|
|
ccf166d89d |
tests/qtest/bios-tables-test: Update DSDT blobs after GPEX _DSM change
Update the reference DSDT blobs after GPEX _DSM change. This affects the
aarch64 'virt', riscv64 "virt", loongarch64 "virt" and the x86 'microvm'
machines.
DSDT diff is the same for all the machines/tests:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20230628 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT, Fri Oct 10 11:18:21 2025
+ * Disassembly of /tmp/aml-E6V9D3, Fri Oct 10 11:18:21 2025
*
* Original Table Header:
* Signature "DSDT"
* Length 0x000014D9 (5337)
* Revision 0x02
- * Checksum 0xA4
+ * Checksum 0xA5
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1822,33 +1822,33 @@
Else
{
CDW1 |= 0x04
}
Return (Arg3)
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x00 // .
})
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20251022080639.243965-4-skolothumtho@nvidia.com>
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5 months ago |
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3e6ad83f20 |
tests/qtest/bios-tables-test: Prepare for _DSM change in the DSDT table
Subsequent patch will fix the GPEX _DSM method. Add the affected DSDT blobs to allowed-diff list for bios-table tests. Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20251022080639.243965-2-skolothumtho@nvidia.com> |
5 months ago |
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7b842fe354 |
migration: Introduce POSTCOPY_DEVICE state
Currently, when postcopy starts, the source VM starts switchover and sends a package containing the state of all non-postcopiable devices. When the destination loads this package, the switchover is complete and the destination VM starts. However, if the device state load fails or the destination side crashes, the source side is already in POSTCOPY_ACTIVE state and cannot be recovered, even when it has the most up-to-date machine state as the destination has not yet started. This patch introduces a new POSTCOPY_DEVICE state which is active while the destination machine is loading the device state, is not yet running, and the source side can be resumed in case of a migration failure. Return-path is required for this state to function, otherwise it will be skipped in favor of POSTCOPY_ACTIVE. To transition from POSTCOPY_DEVICE to POSTCOPY_ACTIVE, the source side uses a PONG message that is a response to a PING message processed just before the POSTCOPY_RUN command that starts the destination VM. Thus, this feature is effective even if the destination side does not yet support this new state. Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Link: https://lore.kernel.org/r/20251103183301.3840862-9-jmarcin@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> |
5 months ago |
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b433ca56e1 |
tests/qtest: Use exit-with-parent=on in qtest invocations
Previously libqtest.c set PR_SET_PDEATHSIG (or the equivalent on FreeBSD) after forking the qemu subprocess. However we can get the same behaviour now by using the new -run-with exit-with-parent=on flag, on platforms that support it. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> |
6 months ago |
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e9d02b5931 |
qtest/am53c974-test: add additional test for cmdfifo overflow
Based upon the qtest reproducer posted to Gitlab issue #3082 at https://gitlab.com/qemu-project/qemu/-/issues/3082. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250925122846.527615-3-mark.cave-ayland@ilande.co.uk Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
6 months ago |
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1b21518f73 |
char: rename CharBackend->CharFrontend
The actual backend is "Chardev", CharBackend is the frontend side of it (whatever talks to the backend), let's rename it for readability. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Link: https://lore.kernel.org/r/20251022074612.1258413-1-marcandre.lureau@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
5 months ago |
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1b2fda5916 |
hw/uefi: add query-firmware-log monitor command
Starting with the edk2-stable202508 tag OVMF (and ArmVirt too) have optional support for logging to a memory buffer. There is guest side support -- for example in linux kernels v6.17+ -- to read that buffer. But that might not helpful if your guest stops booting early enough that guest tooling can not be used yet. So host side support to read that log buffer is a useful thing to have. This patch implements the query-firmware-log qmp monitor command to read the firmware log. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20251017115006.2696991-2-kraxel@redhat.com> |
5 months ago |
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0305ee8275 |
tests/qtest/ds1338: Reuse from_bcd()
from_bcd() is a public API function which can be unit-tested. Reuse it to avoid code duplication. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20251019210303.104718-11-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 months ago |
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fa42484ee1 |
hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model
The ast2600-evb machine model is using the "mx66u51235f" flash model, which has issues with recent Linux kernels (6.15+) when reading SFDP data. Change the flash model to "w25q512jv", which is the model present on some ast2600a3 EVB board and is known to work correctly with recent kernels. Adjust the corresponding qtest to reflect the new JEDEC ID of the w25q512jv flash. Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20251016212437.1046135-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com> |
5 months ago |
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1306584925 |
tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
- Added qtests to test gpio-set property for ASPEED. - Added function to get uint in qdict. Signed-off-by: Felix Wu <flwu@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20251015011830.1688468-3-lixiaoyan@google.com Signed-off-by: Cédric Le Goater <clg@redhat.com> |
6 months ago |
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68e8df8cfa |
tests/data/acpi/loongarch64: Update expected DSDT.*
DSDT diffs from "iasl -d":
@@ -11,7 +11,7 @@
* Signature "DSDT"
* Length 0x000011FB (4603)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x5D
+ * Checksum 0x5B
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
@@ -1426,11 +1426,11 @@
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
- 0x100E001F, // Address Base
+ 0x100E0020, // Address Base
0x0000000C, // Address Length
)
})
- OperationRegion (PRST, SystemMemory, 0x100E001F, 0x0C)
+ OperationRegion (PRST, SystemMemory, 0x100E0020, 0x0C)
Field (PRST, ByteAcc, NoLock, WriteAsZeros)
{
Offset (0x04),
Signed-off-by: Huacai Chen <chenhuacai@kernel.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20250923143542.2391576-4-chenhuacai@kernel.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
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6 months ago |
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cdcb1d39eb |
bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.*
Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: <maobibo@loongson.cn> Message-ID: <20250923143542.2391576-2-chenhuacai@kernel.org> Signed-off-by: Song Gao <gaosong@loongson.cn> |
6 months ago |
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acaa3be3f7 |
tests/virtio-scsi: add a virtio_error() IOThread test
Now that virtio_error() calls should work in an IOThread, add a virtio-scsi IOThread test cases that triggers virtio_error(). Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250922220149.498967-6-stefanha@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
6 months ago |
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e06d96d5a9 |
tests/libqos: extract qvirtqueue_set_avail_idx()
Setting the vring's avail.idx can be useful for low-level VIRTIO tests, especially for testing error scenarios with invalid vrings. Extract it into a new function so that the next commit can add a test that uses this new test API. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250922220149.498967-5-stefanha@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
6 months ago |
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237ca3d578 |
tests/acpi: virt: update HEST and DSDT tables
The following changes for DSDT affecting all files
under tests/data/acpi/aarch64/virt/DSDT* :
-"tests/data/acpi/aarch64/virt/DSDT",
-"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
-"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex",
-"tests/data/acpi/aarch64/virt/DSDT.memhp",
-"tests/data/acpi/aarch64/virt/DSDT.pxb",
-"tests/data/acpi/aarch64/virt/DSDT.topology",
-"tests/data/acpi/aarch64/virt/DSDT.viot",
-"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev",
-"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy",
--- /tmp/DSDT_old.dsl 2025-09-05 15:03:18.964968499 +0200
+++ /tmp/DSDT.dsl 2025-09-05 15:03:18.966968470 +0200
@@ -1886,6 +1886,11 @@
{
Notify (PWRB, 0x80) // Status Change
}
+
+ If (((Local0 & 0x20) == 0x20))
+ {
+ Notify (GEDD, 0x80) // Status Change
+ }
}
}
@@ -1894,6 +1899,12 @@
Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
+
+ Device (GEDD)
+ {
+ Name (_HID, "PNP0C33" /* Error Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
}
Scope (\_SB.PCI0)
Additionally, HEST changes:
-"tests/data/acpi/aarch64/virt/HEST",
--- /tmp/HEST_old.dsl 2025-09-05 15:03:19.078653625 +0200
+++ /tmp/HEST.dsl 2025-09-05 15:03:19.079511472 +0200
@@ -3,7 +3,7 @@
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
- * Disassembly of /tmp/HEST_old
+ * Disassembly of /tmp/HEST
*
* ACPI Data Table [HEST]
*
@@ -11,16 +11,16 @@
*/
[000h 0000 004h] Signature : "HEST" [Hardware Error Source Table]
-[004h 0004 004h] Table Length : 00000084
+[004h 0004 004h] Table Length : 000000E0
[008h 0008 001h] Revision : 01
-[009h 0009 001h] Checksum : E2
+[009h 0009 001h] Checksum : 6C
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
-[024h 0036 004h] Error Source Count : 00000001
+[024h 0036 004h] Error Source Count : 00000002
[028h 0040 002h] Subtable Type : 000A [Generic Hardware Error Source V2]
[02Ah 0042 002h] Source Id : 0000
@@ -55,19 +55,62 @@
[069h 0105 001h] Bit Width : 40
[06Ah 0106 001h] Bit Offset : 00
[06Bh 0107 001h] Encoded Access Width : 04 [QWord Access:64]
-[06Ch 0108 008h] Address : 0000000043DA0008
+[06Ch 0108 008h] Address : 0000000043DA0010
[074h 0116 008h] Read Ack Preserve : FFFFFFFFFFFFFFFE
[07Ch 0124 008h] Read Ack Write : 0000000000000001
-Raw Table Data: Length 132 (0x84)
+[084h 0132 002h] Subtable Type : 000A [Generic Hardware Error Source V2]
+[086h 0134 002h] Source Id : 0001
+[088h 0136 002h] Related Source Id : FFFF
+[08Ah 0138 001h] Reserved : 00
+[08Bh 0139 001h] Enabled : 01
+[08Ch 0140 004h] Records To Preallocate : 00000001
+[090h 0144 004h] Max Sections Per Record : 00000001
+[094h 0148 004h] Max Raw Data Length : 00000400
+
+[098h 0152 00Ch] Error Status Address : [Generic Address Structure]
+[098h 0152 001h] Space ID : 00 [SystemMemory]
+[099h 0153 001h] Bit Width : 40
+[09Ah 0154 001h] Bit Offset : 00
+[09Bh 0155 001h] Encoded Access Width : 04 [QWord Access:64]
+[09Ch 0156 008h] Address : 0000000043DA0008
+
+[0A4h 0164 01Ch] Notify : [Hardware Error Notification Structure]
+[0A4h 0164 001h] Notify Type : 07 [GPIO]
+[0A5h 0165 001h] Notify Length : 1C
+[0A6h 0166 002h] Configuration Write Enable : 0000
+[0A8h 0168 004h] PollInterval : 00000000
+[0ACh 0172 004h] Vector : 00000000
+[0B0h 0176 004h] Polling Threshold Value : 00000000
+[0B4h 0180 004h] Polling Threshold Window : 00000000
+[0B8h 0184 004h] Error Threshold Value : 00000000
+[0BCh 0188 004h] Error Threshold Window : 00000000
+
+[0C0h 0192 004h] Error Status Block Length : 00000400
+[0C4h 0196 00Ch] Read Ack Register : [Generic Address Structure]
+[0C4h 0196 001h] Space ID : 00 [SystemMemory]
+[0C5h 0197 001h] Bit Width : 40
+[0C6h 0198 001h] Bit Offset : 00
+[0C7h 0199 001h] Encoded Access Width : 04 [QWord Access:64]
+[0C8h 0200 008h] Address : 0000000043DA0018
- 0000: 48 45 53 54 84 00 00 00 01 E2 42 4F 43 48 53 20 // HEST......BOCHS
+[0D0h 0208 008h] Read Ack Preserve : FFFFFFFFFFFFFFFE
+[0D8h 0216 008h] Read Ack Write : 0000000000000001
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 48 45 53 54 E0 00 00 00 01 6C 42 4F 43 48 53 20 // HEST.....lBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 01 00 00 00 0A 00 00 00 FF FF 00 01 // ................
+ 0020: 01 00 00 00 02 00 00 00 0A 00 00 00 FF FF 00 01 // ................
0030: 01 00 00 00 01 00 00 00 00 04 00 00 00 40 00 04 // .............@..
0040: 00 00 DA 43 00 00 00 00 08 1C 00 00 00 00 00 00 // ...C............
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0060: 00 00 00 00 00 04 00 00 00 40 00 04 08 00 DA 43 // .........@.....C
+ 0060: 00 00 00 00 00 04 00 00 00 40 00 04 10 00 DA 43 // .........@.....C
0070: 00 00 00 00 FE FF FF FF FF FF FF FF 01 00 00 00 // ................
- 0080: 00 00 00 00 // ....
+ 0080: 00 00 00 00 0A 00 01 00 FF FF 00 01 01 00 00 00 // ................
+ 0090: 01 00 00 00 00 04 00 00 00 40 00 04 08 00 DA 43 // .........@.....C
+ 00A0: 00 00 00 00 07 1C 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 04 00 00 00 40 00 04 18 00 DA 43 00 00 00 00 // .....@.....C....
+ 00D0: FE FF FF FF FF FF FF FF 01 00 00 00 00 00 00 00 // ................
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <2253eb50df797ab320b4ca610bd22a38e5cfd17a.1758610789.git.mchehab+huawei@kernel.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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6 months ago |
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79b10b6639 |
tests/acpi: virt: allow acpi table changes at DSDT and HEST tables
We'll be adding a new GED device for HEST GPIO notification and increasing the number of entries at the HEST table. Blocklist testing HEST and DSDT tables until such changes are completed. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <7fca7eb9b801f1b196210f66538234b94bd31c23.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
6 months ago |
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383c722483 |
vhost-user-test: remove trailing newlines in g_test_message() calls
Fixes:
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6 months ago |
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27cffe1635 |
migration-test: test cpr-exec
Add a test for the cpr-exec migration mode. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Link: https://lore.kernel.org/r/1759332851-370353-20-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
6 months ago |
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ca5be51a51 |
migration-test: strv parameter
Define migrate_set_parameter_strv. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-19-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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aca1533cd8 |
migration-test: migrate_args
Define the subroutine migrate_args to return the arguments that are used to exec the source or target qemu process. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-18-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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bdd739a42c |
migration-test: misc exports
Export misc definitions needed by the cpr-exec test. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-17-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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c454a8d254 |
migration-test: shm path accessor
Define an accessor for the shm path. It will be referenced from multiple sites in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-16-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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0a3aeedb39 |
migration-test: only_source option
Add the only_source option, analogous to only_target. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-15-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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5419f36e9e |
tests/qtest: qtest_init_after_exec
Define a function to create a QTestState object representing the state of QEMU after old QEMU exec's new QEMU. This is needed for testing the cpr-exec migration mode. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-14-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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e9fbd9e6b1 |
tests/qtest: qtest_qemu_spawn_func
Allow the qtest_qemu_spawn caller to pass the function to be called to perform the spawn. The opaque argument is needed by a new spawn function in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-13-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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bf64633510 |
tests/qtest: qtest_create_test_state
Refactor qtest_spawn_qemu and create a subroutine to create a QTestState object, to be used in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-12-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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b4a21e4574 |
tests/qtest: qtest_qemu_args
Define an accessor that returns all the arguments used to exec QEMU. Collect the arguments that were passed to qtest_spawn_qemu, plus the trace arguments that were composed inside qtest_spawn_qemu, and move them to a new function qtest_qemu_args. This will be needed to test the cpr-exec migration mode. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-11-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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8e9f9981d6 |
tests/qtest: export qtest_qemu_binary
Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-10-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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e16d7a7321 |
tests/qtest: optimize qtest_get_machines
qtest_get_machines returns the machines supported by the QEMU binary described by an environment variable and caches the result. If the next call to qtest_get_machines passes the same variable name, the cached result is returned, but if the name changes, the caching is defeated. To make caching more effective, remember the path of the QEMU binary instead. Different env vars, eg QTEST_QEMU_BINARY_SRC and QTEST_QEMU_BINARY_DST, usually resolve to the same path. Before the optimization, the test /x86_64/migration/precopy/unix/plain exec's QEMU and calls query-machines 3 times. After optimization, that only happens once. This does not significantly speed up the tests, but it reduces QTEST_LOG output, and launches fewer QEMU instances, making it easier to debug problems. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <87h5ymdzrf.fsf@pond.sub.org> Link: https://lore.kernel.org/qemu-devel/1758290310-349623-1-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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bfa07595eb |
tests/qtest/migration: Fix cpr-tests in case the machine is not available
When QEMU has been compiled with "--without-default-devices", the migration cpr-tests are currently failing since the first test leaves a socket file behind that avoids that the second test can be initialized correctly. Make sure that we delete the socket file in case that the migrate_start() failed due to the missing machine. Signed-off-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250930090932.235151-1-thuth@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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030cd88556 |
tests/qtest: Add missing checks for the availability of machines
When QEMU has been compiled with "--without-default-devices", the machines might not be available in the binary. Let's properly check for the machines before running the tests to avoid that they are failing in this case. Signed-off-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250930090444.234431-1-thuth@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 months ago |
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6f607941b1 |
treewide: use qemu_set_blocking instead of g_unix_set_fd_nonblocking
Instead of open-coded g_unix_set_fd_nonblocking() calls, use QEMU wrapper qemu_set_blocking(). Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> [DB: fix missing closing ) in tap-bsd.c, remove now unused GError var] Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> |
7 months ago |
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d35146a660 |
qtest/bios-tables-test: Update tables for smmuv3 tests
For the legacy smmuv3 test case, generated IORT has a single SMMUv3 node,
a Root Complex(RC) node and 1 ITS node.
RC node features 4 ID mappings, of which 2 points to SMMU node and the
remaining ones points to ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU0} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
...
[030h 0048 1] Type : 00
[031h 0049 2] Length : 0018
[033h 0051 1] Revision : 01
[034h 0052 4] Identifier : 00000000
[038h 0056 4] Mapping Count : 00000000
[03Ch 0060 4] Mapping Offset : 00000000
[040h 0064 4] ItsCount : 00000001
[044h 0068 4] Identifiers : 00000000
[048h 0072 1] Type : 04
[049h 0073 2] Length : 0058
[04Bh 0075 1] Revision : 04
[04Ch 0076 4] Identifier : 00000001
[050h 0080 4] Mapping Count : 00000001
[054h 0084 4] Mapping Offset : 00000044
[058h 0088 8] Base Address : 0000000009050000
[060h 0096 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
[064h 0100 4] Reserved : 00000000
[068h 0104 8] VATOS Address : 0000000000000000
[070h 0112 4] Model : 00000000
[074h 0116 4] Event GSIV : 0000006A
[078h 0120 4] PRI GSIV : 0000006B
[07Ch 0124 4] GERR GSIV : 0000006D
[080h 0128 4] Sync GSIV : 0000006C
[084h 0132 4] Proximity Domain : 00000000
[088h 0136 4] Device ID Mapping Index : 00000000
[08Ch 0140 4] Input base : 00000000
[090h 0144 4] ID Count : 0000FFFF
[094h 0148 4] Output Base : 00000000
[098h 0152 4] Output Reference : 00000030
[09Ch 0156 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0A0h 0160 1] Type : 02
[0A1h 0161 2] Length : 0074
[0A3h 0163 1] Revision : 03
[0A4h 0164 4] Identifier : 00000002
[0A8h 0168 4] Mapping Count : 00000004
[0ACh 0172 4] Mapping Offset : 00000024
[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties]
[0B0h 0176 4] Cache Coherency : 00000001
[0B4h 0180 1] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
[0B5h 0181 2] Reserved : 0000
[0B7h 0183 1] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
[0B8h 0184 4] ATS Attribute : 00000000
[0BCh 0188 4] PCI Segment Number : 00000000
[0C0h 0192 1] Memory Size Limit : 40
[0C1h 0193 2] PASID Capabilities : 0000
[0C3h 0195 1] Reserved : 00
[0C4h 0196 4] Input base : 00000000
[0C8h 0200 4] ID Count : 000001FF
[0CCh 0204 4] Output Base : 00000000
[0D0h 0208 4] Output Reference : 00000048
[0D4h 0212 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0D8h 0216 4] Input base : 00001000
[0DCh 0220 4] ID Count : 000000FF
[0E0h 0224 4] Output Base : 00001000
[0E4h 0228 4] Output Reference : 00000048
[0E8h 0232 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0ECh 0236 4] Input base : 00000200
[0F0h 0240 4] ID Count : 00000DFF
[0F4h 0244 4] Output Base : 00000200
[0F8h 0248 4] Output Reference : 00000030
[0FCh 0252 4] Flags (decoded below) : 00000000
Single Mapping : 0
[100h 0256 4] Input base : 00001100
[104h 0260 4] ID Count : 0000EEFF
[108h 0264 4] Output Base : 00001100
[10Ch 0268 4] Output Reference : 00000030
[110h 0272 4] Flags (decoded below) : 00000000
Single Mapping : 0
For the smmuv3-dev test case, IORT has 2 SMMUV3 nodes,
1 RC node and 1 ITS node.
RC node features 4 ID mappings. 2 of them target the 2
SMMU nodes while the others targets the ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU1} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
...
[030h 0048 1] Type : 00
[031h 0049 2] Length : 0018
[033h 0051 1] Revision : 01
[034h 0052 4] Identifier : 00000000
[038h 0056 4] Mapping Count : 00000000
[03Ch 0060 4] Mapping Offset : 00000000
[040h 0064 4] ItsCount : 00000001
[044h 0068 4] Identifiers : 00000000
[048h 0072 1] Type : 04
[049h 0073 2] Length : 0058
[04Bh 0075 1] Revision : 04
[04Ch 0076 4] Identifier : 00000001
[050h 0080 4] Mapping Count : 00000001
[054h 0084 4] Mapping Offset : 00000044
[058h 0088 8] Base Address : 000000000C000000
[060h 0096 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
[064h 0100 4] Reserved : 00000000
[068h 0104 8] VATOS Address : 0000000000000000
[070h 0112 4] Model : 00000000
[074h 0116 4] Event GSIV : 00000090
[078h 0120 4] PRI GSIV : 00000091
[07Ch 0124 4] GERR GSIV : 00000093
[080h 0128 4] Sync GSIV : 00000092
[084h 0132 4] Proximity Domain : 00000000
[088h 0136 4] Device ID Mapping Index : 00000000
[08Ch 0140 4] Input base : 00000000
[090h 0144 4] ID Count : 0000FFFF
[094h 0148 4] Output Base : 00000000
[098h 0152 4] Output Reference : 00000030
[09Ch 0156 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0A0h 0160 1] Type : 04
[0A1h 0161 2] Length : 0058
[0A3h 0163 1] Revision : 04
[0A4h 0164 4] Identifier : 00000002
[0A8h 0168 4] Mapping Count : 00000001
[0ACh 0172 4] Mapping Offset : 00000044
[0B0h 0176 8] Base Address : 000000000C020000
[0B8h 0184 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
[0BCh 0188 4] Reserved : 00000000
[0C0h 0192 8] VATOS Address : 0000000000000000
[0C8h 0200 4] Model : 00000000
[0CCh 0204 4] Event GSIV : 00000094
[0D0h 0208 4] PRI GSIV : 00000095
[0D4h 0212 4] GERR GSIV : 00000097
[0D8h 0216 4] Sync GSIV : 00000096
[0DCh 0220 4] Proximity Domain : 00000000
[0E0h 0224 4] Device ID Mapping Index : 00000000
[0E4h 0228 4] Input base : 00000000
[0E8h 0232 4] ID Count : 0000FFFF
[0ECh 0236 4] Output Base : 00000000
[0F0h 0240 4] Output Reference : 00000030
[0F4h 0244 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0F8h 0248 1] Type : 02
[0F9h 0249 2] Length : 0074
[0FBh 0251 1] Revision : 03
[0FCh 0252 4] Identifier : 00000003
[100h 0256 4] Mapping Count : 00000004
[104h 0260 4] Mapping Offset : 00000024
[108h 0264 8] Memory Properties : [IORT Memory Access Properties]
[108h 0264 4] Cache Coherency : 00000001
[10Ch 0268 1] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
[10Dh 0269 2] Reserved : 0000
[10Fh 0271 1] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
[110h 0272 4] ATS Attribute : 00000000
[114h 0276 4] PCI Segment Number : 00000000
[118h 0280 1] Memory Size Limit : 40
[119h 0281 2] PASID Capabilities : 0000
[11Bh 0283 1] Reserved : 00
[11Ch 0284 4] Input base : 00000000
[120h 0288 4] ID Count : 000001FF
[124h 0292 4] Output Base : 00000000
[128h 0296 4] Output Reference : 00000048
[12Ch 0300 4] Flags (decoded below) : 00000000
Single Mapping : 0
[130h 0304 4] Input base : 00001000
[134h 0308 4] ID Count : 000000FF
[138h 0312 4] Output Base : 00001000
[13Ch 0316 4] Output Reference : 000000A0
[140h 0320 4] Flags (decoded below) : 00000000
Single Mapping : 0
[144h 0324 4] Input base : 00000200
[148h 0328 4] ID Count : 00000DFF
[14Ch 0332 4] Output Base : 00000200
[150h 0336 4] Output Reference : 00000030
[154h 0340 4] Flags (decoded below) : 00000000
Single Mapping : 0
[158h 0344 4] Input base : 00001100
[15Ch 0348 4] ID Count : 0000EEFF
[160h 0352 4] Output Base : 00001100
[164h 0356 4] Output Reference : 00000030
[168h 0360 4] Flags (decoded below) : 00000000
Single Mapping : 0
Note: DSDT changes are not described here as it is not impacted by the
way the SMMUv3 is instantiated.
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Reviewed-by: Donald Dutile <ddutile@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Message-id: 20250829082543.7680-12-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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7 months ago |
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3f8cd046c1 |
qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device
For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
one of which has bypass_iommu enabled. The generated IORT table contains
a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node.
RC node features 4 ID mappings, of which 2 points to SMMU node and the
remaining ones points to ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU0} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
For the -device arm-smmuv3,... test, the configuration also includes three
Root Complexes, with two connected to separate SMMUv3 devices.
The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node.
RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while
the others targets the ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU1} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Reviewed-by: Donald Dutile <ddutile@redhat.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Message-id: 20250829082543.7680-11-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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7 months ago |
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c69520c13d |
bios-tables-test: Allow for smmuv3 test data.
The tests to be added exercise both legacy(iommu=smmuv3) and new -device arm-smmuv3,.. cases. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-10-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 months ago |
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c9a1ea9c52 |
Revert "tests/qtest: use qos_printf instead of g_test_message"
This reverts commit
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8 months ago |
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c4c3ee8c1d |
qtest/qom-test: Don't bother to execute QMP command quit
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250725135034.2280477-5-armbru@redhat.com> Reviewed-by: Steve Sistare <steven.sistare@oracle.com> |
8 months ago |
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67a392f7cf |
qtest/qom-test: Traverse entire QOM tree
This test traverses the QOM sub-tree rooted at /machine. Traverse the entire tree instead. The x86_64 test runs some 40 additional QMP commands, and stays under 5s for me. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250725135034.2280477-4-armbru@redhat.com> Reviewed-by: Steve Sistare <steven.sistare@oracle.com> |
8 months ago |
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a60e1544b5 |
qtest/qom-test: Shallow testing of qom-list / qom-get
This test traverses the QOM sub-tree rooted at /machine with a
combination of qom-list and qom-get. In my x86_64 testing, it runs
almost 12000 QMP commands in 34 seconds. With -m slow, we test more
machines, and it takes almost 84000 commands in almost four minutes.
Since commit
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8 months ago |