riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Lukas Straub	161e603975	colo: Reuse the return path from migration on primary and secondary side Use the return-path capability with colo and reuse the opened return path file on both primary and secondary side. This fixes a crash in colo where migration_cancel() races with colo closing s->rp_state.from_dst_file. Signed-off-by: Lukas Straub <lukasstraub2@web.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260302-colo_unit_test_multifd-v11-21-d653fb3b1d80@web.de Signed-off-by: Fabiano Rosas <farosas@suse.de>	4 weeks ago
Lukas Straub	c972c3bdb2	migration-test: Add COLO migration unit test Add a COLO migration test for COLO migration and failover. Reviewed-by: Fabiano Rosas <farosas@suse.de> Tested-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Lukas Straub <lukasstraub2@web.de> Link: https://lore.kernel.org/qemu-devel/20260302-colo_unit_test_multifd-v11-13-d653fb3b1d80@web.de [remove license boilerplate] Signed-off-by: Fabiano Rosas <farosas@suse.de>	4 weeks ago
Prasad Pandit	93c8a97f99	migration: introduce MIGRATION_STATUS_FAILING When migration connection is broken, the QEMU and libvirtd(8) process on the source side receive TCP connection reset notification. QEMU sets the migration status to FAILED and proceeds to migration_cleanup(). Meanwhile, Libvirtd(8) sends a QMP command to migrate_set_capabilities(). The migration_cleanup() and qmp_migrate_set_capabilities() calls race with each other. When the latter is invoked first, since the migration is not running (FAILED), migration capabilities are reset to false, so during migration_cleanup() the QEMU process crashes with assertion failure. Introduce a new migration status FAILING and use it as an interim status when an error occurs. Once migration_cleanup() is done, it sets the migration status to FAILED. This helps to avoid the above race condition and ensuing failure. Interim status FAILING is set wherever the execution moves towards migration_cleanup(): - postcopy_start() - migration_thread() - migration_cleanup() - multifd_send_setup() - bg_migration_thread() - migration_completion() - migration_detect_error() - bg_migration_completion() - multifd_send_error_propagate() - migration_connect_error_propagate() The migration status finally moves to FAILED and reports an appropriate error to the user. Interim status FAILING is _NOT_ set in the following routines because they do not follow the migration_cleanup() path to the FAILED state: - cpr_exec_cb() - qemu_savevm_state() - postcopy_listen_thread() - process_incoming_migration_co() - multifd_recv_terminate_threads() - migration_channel_process_incoming() Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Prasad Pandit <pjp@fedoraproject.org> Link: https://lore.kernel.org/qemu-devel/20260224102547.226087-1-ppandit@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>	1 month ago
Anton Johansson	dd6bee2707	hppa: Introduce HPPACPUDef Restructures the CPU class heirarchy to clarify model names and allow for per-model configuration options via HPPACPUDef. 32-bit HPPA is assumed to run a PA-7300LC, and 64-bit assumed to run a PA-8700. A new PA-8500 model is added, which will later be used by the A400 machine. All CPU models are made into children of the now abstract TYPE_HPPA_CPU base class. Two fields are added to HPPACPUDef describing the size of the physical address space, and whether or not the CPU uses the PA-RISC 2.0 architecture. The latter was previously a field in CPUHPPAState. phys_addr_bits is currently set but unused, and will be used in the following commit. Likewise, PA-8700 is moved to use 44 bit physical addresses in a followup commit to not break bisection. References to "hppa/hppa64" models in test cases are also updated. Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260305-hppa-c3600-v6-1-d51526e5269c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	4 weeks ago
Fabiano Rosas	93ed7d3303	tests/qtest/qos-test: Plug a couple of leaks The walk_path() function of qos-test.c, which walks the graph and adds tests to the test suite uses GLib's g_test_add_data_func_full() function: g_test_add_data_func_full (const char *testpath, gpointer test_data, GTestDataFunc test_func, GDestroyNotify data_free_func) Despite GLib's documentation stating that @data_free_func is a destructor for @test_data, this is not the case. The destructor is supposed to be paired with a constructor, which GLib only accepts via g_test_create_case(). Providing externally allocated data plus a destructor function only works if the test is guaranteed to execute, otherwise the test_data is never deallocated. Due to how subprocessess are implemented in qos-test, each test gets added twice and an extra test gets added per subprocess. In a regular run, the extra subprocess will not be executed and in a single test run (-p), none of the other tests will be executed (+1 per subprocess), leaking 'path_vec' and 'subprocess_path'. Fix this by storing all the path vectors in a list and freeing them all at the end of the program (including subprocess invocations) and moving the allocation of 'subprocess_path' into run_one_subprocess(). While here add some documentation explaining why the graph needs to be walked twice and tests re-added. Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260302092225.4088227-10-peter.maydell@linaro.org [PMM: rebased; rewrote the comment in main() a bit to account for the if (g_test_subprocess()) block it was previously inside no longer being present. ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	3 weeks ago
Fabiano Rosas	56603f5d12	tests/qtest/test-x86-cpuid-compat: Free allocated memory Free the test arguments after test execution. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260302092225.4088227-9-peter.maydell@linaro.org	3 weeks ago
Peter Maydell	7220c1a0ee	tests/qtest/iommu-smmuv3-test: Free QPCIDevice The QPCIDevice we get via qpci_device_foreach() is allocated memory, and we need to g_free() it after use. This fixes asan leaks like this: Direct leak of 64 byte(s) in 1 object(s) allocated from: #0 0x622a5f16913d in calloc (/home/pm215/qemu/build/arm-clang/tests/qtest/iommu-smmuv3-test+0x1d413d) (BuildId: bc598be1f4ad6d1a9a600c55aeef36108bdb6a04) #1 0x73ee41c0f771 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x63771) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x622a5f1d4cec in qpci_device_find /home/pm215/qemu/build/arm-clang/../../tests/qtest/libqos/pci.c:82:11 #3 0x622a5f1d4cec in qpci_device_foreach /home/pm215/qemu/build/arm-clang/../../tests/qtest/libqos/pci.c:34:19 #4 0x622a5f23cc73 in setup_qtest_pci_device /home/pm215/qemu/build/arm-clang/../../tests/qtest/iommu-smmuv3-test.c:45:5 #5 0x622a5f23cc73 in run_smmuv3_translation /home/pm215/qemu/build/arm-clang/../../tests/qtest/iommu-smmuv3-test.c:74:11 Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260302092225.4088227-5-peter.maydell@linaro.org	3 weeks ago
Thomas Huth	3d07240f81	tests/qtest/test-x86-cpuid-compat: Remove the test with the i440fx-2.9 machine The machine has been removed, so the related test can now be removed, too. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20260225092024.794595-17-thuth@redhat.com>	1 month ago
Thomas Huth	b63b340430	tests/qtest: Remove the microblazeel target from the qtests The "petalogix-ml605" boot-serial-test can be run with the "microblaze" target. The remaining tests can simply be dropped now that we are going to remove the "microblazeel" target. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20260226084608.11251-3-thuth@redhat.com>	1 month ago
Alexander Graf	0e7f6f6359	hw/nitro: Add nitro machine Add a machine model to spawn a Nitro Enclave. Unlike the existing -M nitro-enclave, this machine model works exclusively with the -accel nitro accelerator to drive real Nitro Enclave creation. It supports memory allocation, number of CPU selection, both x86_64 as well as aarch64, implements the Enclave heartbeat logic and debug serial console. To use it, create an EIF file and run $ qemu-system-x86_64 -accel nitro,debug-mode=on -M nitro -nographic \ -kernel test.eif or $ qemu-system-aarch64 -accel nitro,debug-mode=on -M nitro -nographic \ -kernel test.eif Signed-off-by: Alexander Graf <graf@amazon.com> Link: https://lore.kernel.org/r/20260225220807.33092-9-graf@amazon.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	1 month ago
Jonathan Cameron	26cd3f8d96	tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS With the addition of back invalidate support in the CXL emulation relax the restriction on the CXL Fixed Memory Window Structures so all advertised ranges continue to support being used with all features that QEMU emulates. [064h 0100 001h] Subtable Type : 01 [CXL Fixed Memory Window Structure] [065h 0101 001h] Reserved : 00 [066h 0102 002h] Length : 0028 [068h 0104 004h] Reserved : 00000000 [06Ch 0108 008h] Window base address : 0000000110000000 [074h 0116 008h] Window size : 0000000100000000 [07Ch 0124 001h] Interleave Members : 00 [07Dh 0125 001h] Interleave Arithmetic : 00 [07Eh 0126 002h] Reserved : 0000 [080h 0128 004h] Granularity : 00000005 [084h 0132 002h] Restrictions : 002F # Changed from 000F [086h 0134 002h] QtgId : 0000 [088h 0136 004h] First Target : 0000000C Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260204170936.43959-6-Jonathan.Cameron@huawei.com>	2 months ago
Jonathan Cameron	de6eb44095	tests/bios-tables-test: Excluded CEDT.cxl for BI restriction relaxation. The next patch will relax restrictions on the fixed memory window to allow use with back invalidate capable devices. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260204170936.43959-4-Jonathan.Cameron@huawei.com>	2 months ago
Peter Maydell	fd5ecd187b	tests/qtest/migration/tls-tests.c: Don't use tls_psk end hook for no_tls tests If you run the TLS tests under a clang undefined-behaviour sanitizer build it will fall over like this: ../../tests/unit/crypto-tls-psk-helpers.c:53:12: runtime error: null pointer passed as argument 1, which is declared to never be null /usr/include/unistd.h:858:48: note: nonnull attribute specified here #0 0x62bd810762ee in test_tls_psk_cleanup /home/pm215/qemu/build/clang/../../tests/unit/crypto-tls-psk-helpers.c:53:5 #1 0x62bd81073f89 in migrate_hook_end_tls_psk /home/pm215/qemu/build/clang/../../tests/qtest/migration/tls-tests.c:101:5 #2 0x62bd81062ef0 in test_precopy_common /home/pm215/qemu/build/clang/../../tests/qtest/migration/framework.c:947:9 This happens because test_precopy_tcp_no_tls() uses a custom start_hook that only sets a couple of parameters, but reuses the tsk_psk end_hook. However, the end_hook runs cleanup that assumes that the data was set up by migrate_hook_start_tls_psk_common(). In particular, it will unconditionally call test_tls_psk_cleanup(data->pskfile), and test_tls_psk_cleanup() will unconditionally unlink() the filename it is passed, which is undefined behaviour if you pass it a NULL pointer. Instead of creating a TestMigrateTLSPSKData struct which we never set any fields in and requiring the migrate_hook_end_tls_psk() hook to cope with that, don't allocate the struct in the start_hook. Then there is nothing we need to clean up, and we can set the end_hook to NULL (which the test framework will interpret as "don't call any end_hook"). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260212114747.1103466-1-peter.maydell@linaro.org [no need to copy stable] Signed-off-by: Fabiano Rosas <farosas@suse.de>	2 months ago
Chao Liu	a8f98ffd7b	tests/qtest: Add RISC-V IOMMU bare-metal test Add a qtest suite for the RISC-V IOMMU PCI device on the virt machine. The test exercises bare, S-stage, G-stage, and nested translation paths using iommu-testdev and the qos-riscv-iommu helpers. The test validates: - Device context (DC) configuration - SV39 page table walks for S-stage translation - SV39x4 page table walks for G-stage translation - Nested translation combining both stages - FCTL register constraints This provides regression coverage for the RISC-V IOMMU implementation without requiring a full guest OS boot. Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Tao Tang <tangtao1634@phytium.com.cn> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/35f046c8d21aa6d5f9a531258762e01be198d8cf.1770127918.git.chao.liu.zevorn@gmail.com Signed-off-by: Fabiano Rosas <farosas@suse.de>	2 months ago
Chao Liu	9d8ffbfc1d	tests/qtest/libqos: Add RISC-V IOMMU helper library Introduce a libqos helper module for RISC-V IOMMU testing with iommu-testdev. The helper provides routines to: - Build device contexts (DC) and 3-level page tables for SV39/SV39x4 - Program command queue (CQ), fault queue (FQ), and DDTP registers following the RISC-V IOMMU specification - Execute DMA translations and verify results The current implementation supports SV39 for S-stage and SV39x4 for G-stage translation. Support for SV48/SV48x4/SV57/SV57x4 can be added in future patches. Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Tao Tang <tangtao1634@phytium.com.cn> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/a2edf8c44f0bce26dccb91a7d13edb58be50c1a3.1770127918.git.chao.liu.zevorn@gmail.com Signed-off-by: Fabiano Rosas <farosas@suse.de>	2 months ago
Jamin Lin	7c79c954aa	tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE tests Update AST2700 HACE qtests to use the "ast2700-evb" machine alias instead of a specific silicon revision. The AST2700 A1 and A2 revisions are compatible for the HACE model, so the tests do not depend on a particular EVB revision. Using the "ast2700-evb" alias ensures the tests always run the latest supported AST2700 silicon revision. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	2 months ago
Mohamed Mediouni	72a231af4c	qtest: hw/arm: virt: add new test case for GICv3 + GICv2m Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	2e1bb23b44	tests: data: update AArch64 ACPI tables After the previous commit introducing GICv3 + GICv2m configurations, update the AArch64 ACPI tables for the GICv2 case. Changes to the ACPI tables: tests/data/acpi/aarch64/virt/IORT.dsl: @@ -11,68 +11,49 @@ / [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 00000080 +[004h 0004 004h] Table Length : 00000054 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : B1 +[009h 0009 001h] Checksum : 3C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000002 +[024h 0036 004h] Node Count : 00000001 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 02 +[031h 0049 002h] Length : 0024 +[033h 0051 001h] Revision : 03 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 -[03Ch 0060 004h] Mapping Offset : 00000000 +[03Ch 0060 004h] Mapping Offset : 00000024 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 02 -[049h 0073 002h] Length : 0038 -[04Bh 0075 001h] Revision : 03 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000024 - -[058h 0088 008h] Memory Properties : [IORT Memory Access Properties] -[058h 0088 004h] Cache Coherency : 00000001 -[05Ch 0092 001h] Hints (decoded below) : 00 +[040h 0064 008h] Memory Properties : [IORT Memory Access Properties] +[040h 0064 004h] Cache Coherency : 00000001 +[044h 0068 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[05Dh 0093 002h] Reserved : 0000 -[05Fh 0095 001h] Memory Flags (decoded below) : 03 +[045h 0069 002h] Reserved : 0000 +[047h 0071 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[060h 0096 004h] ATS Attribute : 00000000 -[064h 0100 004h] PCI Segment Number : 00000000 -[068h 0104 001h] Memory Size Limit : 40 -[069h 0105 002h] PASID Capabilities : 0000 -[06Bh 0107 001h] Reserved : 00 +[048h 0072 004h] ATS Attribute : 00000000 +[04Ch 0076 004h] PCI Segment Number : 00000000 +[050h 0080 001h] Memory Size Limit : 40 +[051h 0081 002h] PASID Capabilities : 0000 +[053h 0083 001h] Reserved : 00 -[06Ch 0108 004h] Input base : 00000000 -[070h 0112 004h] ID Count : 0000FFFF -[074h 0116 004h] Output Base : 00000000 -[078h 0120 004h] Output Reference : 00000030 -[07Ch 0124 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 84 (0x54) -Raw Table Data: Length 128 (0x80) - - 0000: 49 4F 52 54 80 00 00 00 05 B1 42 4F 43 48 53 20 // IORT......BOCHS + 0000: 49 4F 52 54 54 00 00 00 05 3C 42 4F 43 48 53 20 // IORTT....<BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 02 38 00 03 01 00 00 00 // .........8...... - 0050: 01 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... - 0060: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... - 0070: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0020: 01 00 00 00 01 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 02 24 00 03 00 00 00 00 00 00 00 00 24 00 00 00 // .$..........$... + 0040: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ + 0050: 40 00 00 00 // @... tests/data/acpi/aarch64/virt/IORT.smmuv3-dev.dsl: @@ -11,164 +11,120 @@ / [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 0000016C +[004h 0004 004h] Table Length : 00000104 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : C8 +[009h 0009 001h] Checksum : 49 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000004 +[024h 0036 004h] Node Count : 00000003 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0044 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 000000000C000000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 000000000C000000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 00000090 -[078h 0120 004h] PRI GSIV : 00000091 -[07Ch 0124 004h] GERR GSIV : 00000093 -[080h 0128 004h] Sync GSIV : 00000092 -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 00000090 +[060h 0096 004h] PRI GSIV : 00000091 +[064h 0100 004h] GERR GSIV : 00000093 +[068h 0104 004h] Sync GSIV : 00000092 +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[074h 0116 001h] Type : 04 +[075h 0117 002h] Length : 0044 +[077h 0119 001h] Revision : 04 +[078h 0120 004h] Identifier : 00000001 +[07Ch 0124 004h] Mapping Count : 00000000 +[080h 0128 004h] Mapping Offset : 00000000 -[0A0h 0160 001h] Type : 04 -[0A1h 0161 002h] Length : 0058 -[0A3h 0163 001h] Revision : 04 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000001 -[0ACh 0172 004h] Mapping Offset : 00000044 - -[0B0h 0176 008h] Base Address : 000000000C020000 -[0B8h 0184 004h] Flags (decoded below) : 00000001 +[084h 0132 008h] Base Address : 000000000C020000 +[08Ch 0140 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[0BCh 0188 004h] Reserved : 00000000 -[0C0h 0192 008h] VATOS Address : 0000000000000000 -[0C8h 0200 004h] Model : 00000000 -[0CCh 0204 004h] Event GSIV : 00000094 -[0D0h 0208 004h] PRI GSIV : 00000095 -[0D4h 0212 004h] GERR GSIV : 00000097 -[0D8h 0216 004h] Sync GSIV : 00000096 -[0DCh 0220 004h] Proximity Domain : 00000000 -[0E0h 0224 004h] Device ID Mapping Index : 00000000 +[090h 0144 004h] Reserved : 00000000 +[094h 0148 008h] VATOS Address : 0000000000000000 +[09Ch 0156 004h] Model : 00000000 +[0A0h 0160 004h] Event GSIV : 00000094 +[0A4h 0164 004h] PRI GSIV : 00000095 +[0A8h 0168 004h] GERR GSIV : 00000097 +[0ACh 0172 004h] Sync GSIV : 00000096 +[0B0h 0176 004h] Proximity Domain : 00000000 +[0B4h 0180 004h] Device ID Mapping Index : 00000000 -[0E4h 0228 004h] Input base : 00000000 -[0E8h 0232 004h] ID Count : 0000FFFF -[0ECh 0236 004h] Output Base : 00000000 -[0F0h 0240 004h] Output Reference : 00000030 -[0F4h 0244 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[0B8h 0184 001h] Type : 02 +[0B9h 0185 002h] Length : 004C +[0BBh 0187 001h] Revision : 03 +[0BCh 0188 004h] Identifier : 00000002 +[0C0h 0192 004h] Mapping Count : 00000002 +[0C4h 0196 004h] Mapping Offset : 00000024 -[0F8h 0248 001h] Type : 02 -[0F9h 0249 002h] Length : 0074 -[0FBh 0251 001h] Revision : 03 -[0FCh 0252 004h] Identifier : 00000003 -[100h 0256 004h] Mapping Count : 00000004 -[104h 0260 004h] Mapping Offset : 00000024 - -[108h 0264 008h] Memory Properties : [IORT Memory Access Properties] -[108h 0264 004h] Cache Coherency : 00000001 -[10Ch 0268 001h] Hints (decoded below) : 00 +[0C8h 0200 008h] Memory Properties : [IORT Memory Access Properties] +[0C8h 0200 004h] Cache Coherency : 00000001 +[0CCh 0204 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[10Dh 0269 002h] Reserved : 0000 -[10Fh 0271 001h] Memory Flags (decoded below) : 03 +[0CDh 0205 002h] Reserved : 0000 +[0CFh 0207 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[110h 0272 004h] ATS Attribute : 00000000 -[114h 0276 004h] PCI Segment Number : 00000000 -[118h 0280 001h] Memory Size Limit : 40 -[119h 0281 002h] PASID Capabilities : 0000 -[11Bh 0283 001h] Reserved : 00 +[0D0h 0208 004h] ATS Attribute : 00000000 +[0D4h 0212 004h] PCI Segment Number : 00000000 +[0D8h 0216 001h] Memory Size Limit : 40 +[0D9h 0217 002h] PASID Capabilities : 0000 +[0DBh 0219 001h] Reserved : 00 -[11Ch 0284 004h] Input base : 00000000 -[120h 0288 004h] ID Count : 000001FF -[124h 0292 004h] Output Base : 00000000 -[128h 0296 004h] Output Reference : 00000048 -[12Ch 0300 004h] Flags (decoded below) : 00000000 +[0DCh 0220 004h] Input base : 00000000 +[0E0h 0224 004h] ID Count : 000001FF +[0E4h 0228 004h] Output Base : 00000000 +[0E8h 0232 004h] Output Reference : 00000030 +[0ECh 0236 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[130h 0304 004h] Input base : 00001000 -[134h 0308 004h] ID Count : 000000FF -[138h 0312 004h] Output Base : 00001000 -[13Ch 0316 004h] Output Reference : 000000A0 -[140h 0320 004h] Flags (decoded below) : 00000000 +[0F0h 0240 004h] Input base : 00001000 +[0F4h 0244 004h] ID Count : 000000FF +[0F8h 0248 004h] Output Base : 00001000 +[0FCh 0252 004h] Output Reference : 00000074 +[100h 0256 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[144h 0324 004h] Input base : 00000200 -[148h 0328 004h] ID Count : 00000DFF -[14Ch 0332 004h] Output Base : 00000200 -[150h 0336 004h] Output Reference : 00000030 -[154h 0340 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 260 (0x104) -[158h 0344 004h] Input base : 00001100 -[15Ch 0348 004h] ID Count : 0000EEFF -[160h 0352 004h] Output Base : 00001100 -[164h 0356 004h] Output Reference : 00000030 -[168h 0360 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 - -Raw Table Data: Length 364 (0x16C) - - 0000: 49 4F 52 54 6C 01 00 00 05 C8 42 4F 43 48 53 20 // IORTl.....BOCHS + 0000: 49 4F 52 54 04 01 00 00 05 49 42 4F 43 48 53 20 // IORT.....IBOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 04 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 00 0C 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 90 00 00 00 91 00 00 00 93 00 00 00 // ................ - 0080: 92 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 04 58 00 04 02 00 00 00 01 00 00 00 44 00 00 00 // .X..........D... - 00B0: 00 00 02 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................ - 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 94 00 00 00 // ................ - 00D0: 95 00 00 00 97 00 00 00 96 00 00 00 00 00 00 00 // ................ - 00E0: 00 00 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 // ................ - 00F0: 30 00 00 00 00 00 00 00 02 74 00 03 03 00 00 00 // 0........t...... - 0100: 04 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... - 0110: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... - 0120: FF 01 00 00 00 00 00 00 48 00 00 00 00 00 00 00 // ........H....... - 0130: 00 10 00 00 FF 00 00 00 00 10 00 00 A0 00 00 00 // ................ - 0140: 00 00 00 00 00 02 00 00 FF 0D 00 00 00 02 00 00 // ................ - 0150: 30 00 00 00 00 00 00 00 00 11 00 00 FF EE 00 00 // 0............... - 0160: 00 11 00 00 30 00 00 00 00 00 00 00 // ....0....... + 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D.............. + 0040: 00 00 00 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 // ................ + 0060: 91 00 00 00 93 00 00 00 92 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 04 44 00 04 01 00 00 00 00 00 00 00 // .....D.......... + 0080: 00 00 00 00 00 00 02 0C 00 00 00 00 01 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 94 00 00 00 95 00 00 00 97 00 00 00 96 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 02 4C 00 03 02 00 00 00 // .........L...... + 00C0: 02 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... + 00D0: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... + 00E0: FF 01 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 00F0: 00 10 00 00 FF 00 00 00 00 10 00 00 74 00 00 00 // ............t... + 0100: 00 00 00 00 // .... tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy.dsl: @@ -11,129 +11,92 @@ */ [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 00000114 +[004h 0004 004h] Table Length : 000000C0 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : 4A +[009h 0009 001h] Checksum : 1C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000003 +[024h 0036 004h] Node Count : 00000002 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0044 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 0000000009050000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 0000000009050000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 0000006A -[078h 0120 004h] PRI GSIV : 0000006B -[07Ch 0124 004h] GERR GSIV : 0000006D -[080h 0128 004h] Sync GSIV : 0000006C -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 0000006A +[060h 0096 004h] PRI GSIV : 0000006B +[064h 0100 004h] GERR GSIV : 0000006D +[068h 0104 004h] Sync GSIV : 0000006C +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +[074h 0116 001h] Type : 02 +[075h 0117 002h] Length : 004C +[077h 0119 001h] Revision : 03 +[078h 0120 004h] Identifier : 00000001 +[07Ch 0124 004h] Mapping Count : 00000002 +[080h 0128 004h] Mapping Offset : 00000024 -[0A0h 0160 001h] Type : 02 -[0A1h 0161 002h] Length : 0074 -[0A3h 0163 001h] Revision : 03 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000004 -[0ACh 0172 004h] Mapping Offset : 00000024 - -[0B0h 0176 008h] Memory Properties : [IORT Memory Access Properties] -[0B0h 0176 004h] Cache Coherency : 00000001 -[0B4h 0180 001h] Hints (decoded below) : 00 +[084h 0132 008h] Memory Properties : [IORT Memory Access Properties] +[084h 0132 004h] Cache Coherency : 00000001 +[088h 0136 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 002h] Reserved : 0000 -[0B7h 0183 001h] Memory Flags (decoded below) : 03 +[089h 0137 002h] Reserved : 0000 +[08Bh 0139 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[0B8h 0184 004h] ATS Attribute : 00000000 -[0BCh 0188 004h] PCI Segment Number : 00000000 -[0C0h 0192 001h] Memory Size Limit : 40 -[0C1h 0193 002h] PASID Capabilities : 0000 -[0C3h 0195 001h] Reserved : 00 +[08Ch 0140 004h] ATS Attribute : 00000000 +[090h 0144 004h] PCI Segment Number : 00000000 +[094h 0148 001h] Memory Size Limit : 40 +[095h 0149 002h] PASID Capabilities : 0000 +[097h 0151 001h] Reserved : 00 -[0C4h 0196 004h] Input base : 00000000 -[0C8h 0200 004h] ID Count : 000001FF -[0CCh 0204 004h] Output Base : 00000000 -[0D0h 0208 004h] Output Reference : 00000048 -[0D4h 0212 004h] Flags (decoded below) : 00000000 +[098h 0152 004h] Input base : 00000000 +[09Ch 0156 004h] ID Count : 000001FF +[0A0h 0160 004h] Output Base : 00000000 +[0A4h 0164 004h] Output Reference : 00000030 +[0A8h 0168 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0D8h 0216 004h] Input base : 00001000 -[0DCh 0220 004h] ID Count : 000000FF -[0E0h 0224 004h] Output Base : 00001000 -[0E4h 0228 004h] Output Reference : 00000048 -[0E8h 0232 004h] Flags (decoded below) : 00000000 +[0ACh 0172 004h] Input base : 00001000 +[0B0h 0176 004h] ID Count : 000000FF +[0B4h 0180 004h] Output Base : 00001000 +[0B8h 0184 004h] Output Reference : 00000030 +[0BCh 0188 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0ECh 0236 004h] Input base : 00000200 -[0F0h 0240 004h] ID Count : 00000DFF -[0F4h 0244 004h] Output Base : 00000200 -[0F8h 0248 004h] Output Reference : 00000030 -[0FCh 0252 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 192 (0xC0) -[100h 0256 004h] Input base : 00001100 -[104h 0260 004h] ID Count : 0000EEFF -[108h 0264 004h] Output Base : 00001100 -[10Ch 0268 004h] Output Reference : 00000030 -[110h 0272 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 - -Raw Table Data: Length 276 (0x114) - - 0000: 49 4F 52 54 14 01 00 00 05 4A 42 4F 43 48 53 20 // IORT.....JBOCHS + 0000: 49 4F 52 54 C0 00 00 00 05 1C 42 4F 43 48 53 20 // IORT......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 05 09 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 6A 00 00 00 6B 00 00 00 6D 00 00 00 // ....j...k...m... - 0080: 6C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // l............... - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 02 74 00 03 02 00 00 00 04 00 00 00 24 00 00 00 // .t..........$... - 00B0: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ - 00C0: 40 00 00 00 00 00 00 00 FF 01 00 00 00 00 00 00 // @............... - 00D0: 48 00 00 00 00 00 00 00 00 10 00 00 FF 00 00 00 // H............... - 00E0: 00 10 00 00 48 00 00 00 00 00 00 00 00 02 00 00 // ....H........... - 00F0: FF 0D 00 00 00 02 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0100: 00 11 00 00 FF EE 00 00 00 11 00 00 30 00 00 00 // ............0... - 0110: 00 00 00 00 // .... + 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D.............. + 0040: 00 00 05 09 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 6A 00 00 00 // ............j... + 0060: 6B 00 00 00 6D 00 00 00 6C 00 00 00 00 00 00 00 // k...m...l....... + 0070: 00 00 00 00 02 4C 00 03 01 00 00 00 02 00 00 00 // .....L.......... + 0080: 24 00 00 00 01 00 00 00 00 00 00 03 00 00 00 00 // $............... + 0090: 00 00 00 00 40 00 00 00 00 00 00 00 FF 01 00 00 // ....@........... + 00A0: 00 00 00 00 30 00 00 00 00 00 00 00 00 10 00 00 // ....0........... + 00B0: FF 00 00 00 00 10 00 00 30 00 00 00 00 00 00 00 // ........0....... Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Mohamed Mediouni	eb1c60997c	qtest: hw/arm: virt: skip ACPI test for IORT with GICv2 Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Philippe Mathieu-Daudé	6fcfe360dc	hw/i386/pc: Remove deprecated pc-q35-2.7 and pc-i440fx-2.7 machines These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit `ce80c4fa6f` "docs: document special exception for machine type deprecation & removal") they can now be removed. Remove the qtest in test-x86-cpuid-compat.c file. Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20260108033051.777361-21-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	3 months ago
Zhao Liu	9b65a1dbc1	tests/acpi: Update DSDT tables for pc & q35 machines Now the legacy cpu hotplug way has gone away, and there's no _INIT method in DSDT table for modern cpu hotplug support. Update DSDT tables for pc machine, and_INIT methods are removed from DSDT tables: - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Link: https://lore.kernel.org/r/20260108033051.777361-8-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	3 months ago
Igor Mammedov	0a07b71f20	tests/acpi: Allow DSDT table change for x86 machines Before dropping legacy CPU hotplug code, mark and allow the affected ACPI tables, to avoid breaking ACPI table testing. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20260108033051.777361-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	3 months ago
Igor Mammedov	66cf169e29	q35: Fix migration of SMRAM state When migrating, dst QEMU by default has SMRAM unlocked, and since wmask is not migrated, the migrated value of MCH_HOST_BRIDGE_F_SMBASE in config space fall to prey of mch_update_smbase_smram() ... if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { *reg = 0x00; and is getting cleared and leads to unlocked smram on dst even if on source it's been locked. As Andrey has pointed out [1], we should derive wmask from config and not other way around. Drop offending chunk and resync wmask based on MCH_HOST_BRIDGE_F_SMBASE register value. That would preserve the register during migration and set smram regions into corresponding state. What that changes is: that it would let guest write junk values in register (with no apparent effect) until it's stumbles upon reserved 0x1 [\|] 0x2 values, at which point it would be only possible to lock register and trigger switch to SMRAM blackhole in CPU AS. While at it, fix up test by removing junk discard before negotiation hunk. PS2: Instead of adding a dedicated post_load handler for it, reuse mch_update->mch_update_smbase_smram call chain that is called on write/reset/post_load to be consistent with how we handle mch registers. PS3: for prosterity here is erro message Andrey got due to this bug: qemu: vfio_container_dma_map(0x..., 0x0, 0xa0000, 0x....) = -22 (Invalid argument) qemu: hardware error: vfio: DMA mapping failed, unable to continue 1) https://patchew.org/QEMU/20251203180851.6390-1-arbn@yandex-team.com/ Fixes: `f404220e27` ("q35: implement 128K SMRAM at default SMBASE address") Reported-by: Andrey Ryabinin <arbn@yandex-team.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Andrey Ryabinin <arbn@yandex-team.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20251211165454.288476-1-imammedo@redhat.com>	4 months ago
Ilia Levi	94e72135d4	tests/qtest/ufs-test: Add test for mcq completion queue wraparound Added a test that sends 32 NOP Out commands asynchronously. Since the CQ has 31 entries by default, this tests the scenario where CQ processing needs to wait for space to become available. Additionally, added two minor fixes to existing tests: * advance CQ head after reading from CQ * initialize command descriptor slots bitmap in ufs_init() Signed-off-by: Ilia Levi <ilia.levi@intel.com> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>	3 months ago
Shameer Kolothum	f48bddafa2	tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade Update the reference IORT blobs after revision upgrade for RMR node support. This affects the aarch64 'virt' IORT tests. IORT diff is the same for all the tests: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20230628 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * - * Disassembly of tests/data/acpi/aarch64/virt/IORT, Mon Oct 20 14:42:41 2025 + * Disassembly of /tmp/aml-B4ZRE3, Mon Oct 20 14:42:41 2025 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "IORT" [IO Remapping Table] [004h 0004 004h] Table Length : 00000080 -[008h 0008 001h] Revision : 03 -[009h 0009 001h] Checksum : B3 +[008h 0008 001h] Revision : 05 +[009h 0009 001h] Checksum : B1 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 ... Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Message-id: 20260126104342.253965-27-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Shameer Kolothum	b8e196a746	tests/qtest/bios-tables-test: Prepare for IORT revison upgrade Subsequent patch will upgrade IORT revision to 5 to add support for IORT RMR nodes. Add the affected IORT blobs to allowed-diff list for bios-table tests. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Message-id: 20260126104342.253965-25-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2 months ago
Peter Xu	f1fcc1c101	migration: Remove fd: support on files This feature was deprecated in 9.1. Remove it in this release (11.0). We also need to remove one unit test (/migration/precopy/fd/file) that covers the fd: file migration, because it'll stop working now. Reviewed-by: Prasad Pandit <ppandit@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260115225503.3083355-3-peterx@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>	2 months ago
Peter Xu	3346b16aa2	tests/migration-test: Remove postcopy_recovery_fail_stage from MigrateCommon The parameter can be instead passed into the function to avoid polluting the global address space of MigrateCommon. Reviewed-by: Prasad Pandit <ppandit@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260114153751.2427172-3-peterx@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>	3 months ago
Peter Xu	86571f5121	tests/migration-test: Remove postcopy_data from MigrateCommon Now postcopy is not the only user of start_hook / end_hook that will pass in a opaque pointer. It doesn't need to be defined in MigrateCommon as part of the framework, as all other hook users can pass hook_data around. Do it too for postcopy. Reviewed-by: Prasad Pandit <ppandit@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260114153751.2427172-2-peterx@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>	3 months ago
Jason Wang	014c06435f	tests/qtest: Add test for filter-redirector rx event opened Add a new test case 'test_redirector_rx_event_opened' to verify the handling of the CHR_EVENT_OPENED event in filter-redirector. The test simulates a scenario where the backend character device (socket) is disconnected and then reconnected. It works by: 1. Connecting to the redirector's socket (triggers CHR_EVENT_OPENED). 2. Sending a packet to verify initial connectivity. 3. Disconnecting (triggers CHR_EVENT_CLOSED). 4. Reconnecting (triggers CHR_EVENT_OPENED again). 5. Sending another packet to verify that the redirector correctly re-registers its handlers and resumes passing traffic. This ensures that the filter-redirector can recover and function correctly after a backend reconnection. Reviewed-by: Zhang Chen <zhangckid@gmail.com> Signed-off-by: Jason Wang <jasowang@redhat.com>	3 months ago
Jason Wang	414af49791	qtest: add a test to test redirector status change This patch adds a qtest to test the status change of filter-redirector. Two subtests were added: - test_redirector_status: tests dynamic on/off switching at runtime using qom-set QMP command - test_redirector_init_status_off: tests creating filter-redirector with status=off from the start via command line Both tests verify that: 1. When status is off, data from indev chardev is not received 2. When status is switched to on, data is received correctly Reviewed-by: Zhang Chen <zhangckid@gmail.com> Signed-off-by: Jason Wang <jasowang@redhat.com>	3 months ago
Jason Wang	50f6d44850	tests/qtest: add test for filter-buffer interval change Add test_change_interval_timer to verify that modifying the 'interval' property of filter-buffer at runtime takes effect immediately. The test uses socket backend and filter-redirector to verify timer behavior: - Creates filter-buffer with a very long interval (1000 seconds) - Sends a packet which gets buffered - Advances virtual clock by 1 second, verifies packet is still buffered - Changes interval to 1ms via qom-set (timer should be rescheduled) - Advances virtual clock by 2ms, verifies packet is now released - This proves the timer was rescheduled immediately when interval changed The test uses filter-redirector to observe when packets are released by filter-buffer, providing end-to-end verification of the timer rescheduling behavior. Reviewed-by: Zhang Chen <zhangckid@gmail.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Jason Wang <jasowang@redhat.com>	3 months ago
Philippe Mathieu-Daudé	e44dc42f3a	bswap: Use 'qemu/bswap.h' instead of 'qemu/host-utils.h' These files only require "qemu/bswap.h", not "qemu/host-utils.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109163730.57087-2-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	3115691855	bswap: Include missing 'qemu/bswap.h' header All these files indirectly include the "qemu/bswap.h" header. Make this inclusion explicit to avoid build errors when refactoring unrelated headers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109164742.58041-4-philmd@linaro.org>	3 months ago
Tao Tang	d8d19c31b2	tests/qtest: Add SMMUv3 bare-metal test using iommu-testdev Add a qtest suite that validates ARM SMMUv3 translation without guest firmware or OS. The tests leverage iommu-testdev to trigger DMA operations and the qos-smmuv3 library to configure IOMMU translation structures. This test suite targets the virt machine and covers: - Stage 1 only translation (VA -> PA via CD page tables) - Stage 2 only translation (IPA -> PA via STE S2 tables) - Nested translation (VA -> IPA -> PA, Stage 1 + Stage 2) - Design to extended to support multiple security spaces (Non-Secure, Secure, Root, Realm) Each test case follows this sequence: 1. Initialize SMMUv3 with appropriate command/event queues 2. Build translation tables (STE/CD/PTE) for the target scenario 3. Configure iommu-testdev with IOVA and DMA attributes via MMIO 4. Trigger DMA and validate successful translation 5. Verify data integrity through a deterministic write-read pattern This bare-metal approach provides deterministic IOMMU testing with minimal dependencies, making failures directly attributable to the SMMU translation path. Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20260119161112.3841386-9-tangtao1634@phytium.com.cn> [PMD: Cover tests/qtest/iommu-smmuv3-test.c in MAINTAINERS] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	6 months ago
Tao Tang	489812e32d	tests/qtest/libqos: Add SMMUv3 helper library Introduce qos-smmuv3, a reusable library for SMMUv3-related qtest operations. This module encapsulates common tasks like: - SMMUv3 initialization (enabling, configuring command/event queues) - Stream Table Entry (STE) and Context Descriptor (CD) setup - Multi-level page table construction (L0-L3 for 4KB granules) - Support for Stage 1, Stage 2, and nested translation modes - Could be easily extended to support multi-space testing infrastructure (Non-Secure, Secure, Root, Realm) The library provides high-level abstractions that allow test code to focus on IOMMU behavior validation rather than low-level register manipulation and page table encoding. Key features include: - Provide memory allocation for translation structures with proper alignment - Helper functions to build valid STEs/CDs for different translation scenarios - Page table walkers that handle address offset calculations per security space This infrastructure is designed to be used by iommu-testdev-based tests and future SMMUv3 test suites, reducing code duplication and improving test maintainability. Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20260119161112.3841386-8-tangtao1634@phytium.com.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	4 months ago
Tao Tang	a68650098a	tests/qtest: Add libqos iommu-testdev helpers Introduce a libqos helper module for the iommu-testdev device used by qtests. This module provides some common functions to all IOMMU test cases using iommu-testdev. Wire the new sources into tests/qtest/libqos/meson.build so they are built as part of the qtest support library. Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Message-ID: <20260119161112.3841386-7-tangtao1634@phytium.com.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>	2 months ago
Philippe Mathieu-Daudé	a49cb762eb	tests/qtest/migration: Add MigrationTestEnv::has_hvf field Allow tests to tune their parameters when running on HVF. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250128135429.8500-6-philmd@linaro.org>	1 year ago
Philippe Mathieu-Daudé	851fc792d5	tests/qtest/migration: Make 'has_dirty_ring' generic Keep accelerator knowledge limited within MigrationTestEnv, expose a generic %has_dirty_ring value, only checking for KVM when initializing it in migration_get_env(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20250128135429.8500-3-philmd@linaro.org>	1 year ago
Cédric Le Goater	aef386e0b1	tests/qtest: Fix build error Newer gcc compiler (version 16.0.0 20260103 (Red Hat 16.0.0-0) (GCC)) detects an unused variable error: ../tests/qtest/libqtest.c: In function ‘qtest_qom_has_concrete_type’: ../tests/qtest/libqtest.c:1044:9: error: variable ‘idx’ set but not used [-Werror=unused-but-set-variable=] Remove idx. Cc: Fabiano Rosas <farosas@suse.de> Cc: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/20260112123146.1010621-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	3 months ago
Zhenzhong Duan	4fda086f76	intel_iommu: Update terminology to match VTD spec VTD spec revision 3.4 released in December 2021 renamed "First-level" to "First-stage" and "Second-level" to "Second-stage". Do the same in intel_iommu code to match spec, change all existing "fl/sl/FL/SL/first level/second level/stage-1/stage-2" terminology to "fs/ss/FS/SS/first stage/second stage". Opportunistically fix a error print of "flts=on" with "x-flts=on". No functional changes intended. Suggested-by: Yi Liu <yi.l.liu@intel.com> Suggested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-4-zhenzhong.duan@intel.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	3 months ago
Philippe Mathieu-Daudé	35ddb78b65	system/ioport: Declare x86-specific I/O port in little-endian order X86 in/out port (related to ISA bus) uses little endianness: - enforce little endianness in x86 cpu_in/out() accessors, - serialize QTest in/out port accesses as little-endian. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109165058.59144-22-philmd@linaro.org>	3 months ago
Philippe Mathieu-Daudé	8afde4364d	tests/qtest: Remove unnecessary 'qemu/bswap.h' include None of these files use API declared in "qemu/bswap.h", remove the unnecessary inclusion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109164742.58041-2-philmd@linaro.org>	3 months ago
Yunpeng Yang	75c15651af	hw/ipmi/ipmi_bmc_sim: Support setting fake LAN channel config The "Set LAN Configuration Parameters" IPMI command is added to the `ipmi_bmc_sim` device to support dynamically setting fake LAN channel configurations. With the fake LAN channel enabled, inside the guest OS, tools such as `ipmitool` can be used to modify the configurations. Signed-off-by: Yunpeng Yang <yunpeng.yang@nutanix.com> Message-ID: <20260105155648.1037077-3-yunpeng.yang@nutanix.com> Signed-off-by: Corey Minyard <corey@minyard.net>	3 months ago
Yubin Zou	eb5f781add	test/qtest: Add Unit test for Aspeed SGPIO This commit introduces a new qtest for the Aspeed SGPIO controller The test covers the following: - Setting and clearing SGPIO output pins and verifying the pin state. - Setting and clearing SGPIO input pins and verifying the pin state. - Verifying that level-high interrupts are correctly triggered and cleared. Signed-off-by: Yubin Zou <yubinz@google.com> Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-6-fd5593178144@google.com Signed-off-by: Cédric Le Goater <clg@redhat.com>	3 months ago
Paolo Bonzini	a7ab886b6e	tests/meson: do not reuse migration_files variable The variable is defined in migration/meson.build, reusing it is confusing. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	4 months ago
Paolo Bonzini	7f548b8f23	include: reorganize memory API headers Move RAMBlock functions out of ram_addr.h and cpu-common.h; move memory API headers out of include/exec and into include/system. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	4 months ago
Paolo Bonzini	3e7316044d	include: move hw/registerfields.h to hw/core/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	4 months ago
Paolo Bonzini	d1000ecae2	include: move hw/qdev-core.h to hw/core/, rename Call it hw/core/qdev.h to avoid the duplication in the name. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	4 months ago
Paolo Bonzini	1942b61b74	include: move hw/boards.h to hw/core/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	4 months ago

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