riscv/qemu - qemu - Gitea: Git with a cup of tea

Commit Graph

Author	SHA1	Message	Date
Paolo Bonzini	78d45220b4	include: move hw/qdev-properties.h to hw/core/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	8 months ago
Philippe Mathieu-Daudé	12d1a768bd	qom: Have class_init() take a const data argument Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>	2 years ago
Hao Wu	cf76c4e174	hw/misc: Add nr_regs and cold_reset_values to NPCM CLK These 2 values are different between NPCM7XX and NPCM8XX CLKs. So we add them to the class and assign different values to them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-13-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Hao Wu	ca2fd966ea	hw/misc: Support 8-bytes memop in NPCM GCR module The NPCM8xx GCR device can be accessed with 64-bit memory operations. This patch supports that. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20250219184609.1839281-10-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Hao Wu	0ad46bbb56	hw/misc: Store DRAM size in NPCM8XX GCR Module NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this information directly similar to the NPCM7XX's INCTR3 register. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-9-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Hao Wu	d9ffb75f2a	hw/misc: Add support for NPCM8XX GCR Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-8-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Hao Wu	8ca2021b9d	hw/misc: Add nr_regs and cold_reset_values to NPCM GCR These 2 values are different between NPCM7XX and NPCM8XX GCRs. So we add them to the class and assign different values to them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-7-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Hao Wu	c99064e637	hw/misc: Move NPCM7XX GCR to NPCM GCR A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-6-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Hao Wu	506af2330c	hw/misc: Rename npcm7xx_gcr to npcm_gcr NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module needs to fit both. This commit changes the name of the GCR module. Future commits will add the support for NPCM8XX GCRs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-5-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	1 year ago
Richard Henderson	5fcabe628b	include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LIST Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>	2 years ago
Richard Henderson	3002997310	hw/misc: Constify all Property Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2 years ago
Peter Maydell	1e0f2b38ac	hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr The npcm7xx_clk and npcm7xx_gcr device reset methods look at the ResetType argument and only handle RESET_TYPE_COLD, producing a warning if another reset type is passed. This is different from how every other three-phase-reset method we have works, and makes it difficult to add new reset types. A better pattern is "assume that any reset type you don't know about should be handled like RESET_TYPE_COLD"; switch these devices to do that. Then adding a new reset type will only need to touch those devices where its behaviour really needs to be different from the standard cold reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-2-peter.maydell@linaro.org	2 years ago
Richard Henderson	e4ea952fb0	hw/misc: Constify VMState Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-41-richard.henderson@linaro.org>	3 years ago
Hao Wu	828d651c58	hw/*: Use type casting for SysBusDevice in NPCM7XX A device shouldn't access its parent object which is QOM internal. Instead it should use type cast for this purporse. This patch fixes this issue for all NPCM7XX Devices. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210108190945.949196-7-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	6 years ago
Havard Skinnemoen	e5a7ba8788	hw/misc: Add NPCM7xx System Global Control Registers device model Implement a device model for the System Global Control Registers in the NPCM730 and NPCM750 BMC SoCs. This is primarily used to enable SMP boot (the boot ROM spins reading the SCRPAD register) and DDR memory initialization; other registers are best effort for now. The reset values of the MDLR and PWRON registers are determined by the SoC variant (730 vs 750) and board straps respectively. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-2-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	6 years ago

9 Commits (master)