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tcg: Merge INDEX_op_xor_{i32,i64} 

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
pull/291/head
Richard Henderson 1 year ago
parent
d3e56f3824
commit
fffd3dc902
8 changed files with 21 additions and 28 deletions
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  1. 2
      docs/devel/tcg-ops.rst
  2. 3
      include/tcg/tcg-opc.h
  3. 6
      target/sh4/translate.c
  4. 18
      tcg/optimize.c
  5. 4
      tcg/tcg-op.c
  6. 9
      tcg/tcg.c
  7. 5
      tcg/tci.c
  8. 2
      tcg/tci/tcg-target.c.inc

2
docs/devel/tcg-ops.rst
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@ -311,7 +311,7 @@ Logical
- | *t0* = *t1* | *t2*
* - xor_i32/i64 *t0*, *t1*, *t2*
* - xor *t0*, *t1*, *t2*
- | *t0* = *t1* ^ *t2*

3
include/tcg/tcg-opc.h
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@ -44,6 +44,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(xor, 1, 2, 0, TCG_OPF_INT)
DEF(setcond_i32, 1, 2, 1, 0)
DEF(negsetcond_i32, 1, 2, 1, 0)
@ -66,7 +67,6 @@ DEF(rem_i32, 1, 2, 0, 0)
DEF(remu_i32, 1, 2, 0, 0)
DEF(div2_i32, 2, 3, 0, 0)
DEF(divu2_i32, 2, 3, 0, 0)
DEF(xor_i32, 1, 2, 0, 0)
/* shifts/rotates */
DEF(shl_i32, 1, 2, 0, 0)
DEF(shr_i32, 1, 2, 0, 0)
@ -124,7 +124,6 @@ DEF(rem_i64, 1, 2, 0, 0)
DEF(remu_i64, 1, 2, 0, 0)
DEF(div2_i64, 2, 3, 0, 0)
DEF(divu2_i64, 2, 3, 0, 0)
DEF(xor_i64, 1, 2, 0, 0)
/* shifts/rotates */
DEF(shl_i64, 1, 2, 0, 0)
DEF(shr_i64, 1, 2, 0, 0)

6
target/sh4/translate.c
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@ -1946,7 +1946,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
op_opc = INDEX_op_and;
goto do_reg_op;
case 0x200a: /* xor Rm,Rn */
op_opc = INDEX_op_xor_i32;
op_opc = INDEX_op_xor;
goto do_reg_op;
case 0x200b: /* or Rm,Rn */
op_opc = INDEX_op_or;
@ -1976,7 +1976,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_dst = B11_8;
op_opc = INDEX_op_xor_i32;
op_opc = INDEX_op_xor;
op_arg = tcg_constant_i32(-1);
break;
@ -2133,7 +2133,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
break;
case INDEX_op_xor_i32:
case INDEX_op_xor:
if (op_dst != st_src) {
goto fail;
}

18
tcg/optimize.c
View File

@ -441,7 +441,8 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
case INDEX_op_or_vec:
return x | y;
CASE_OP_32_64_VEC(xor):
case INDEX_op_xor:
case INDEX_op_xor_vec:
return x ^ y;
case INDEX_op_shl_i32:
@ -2289,7 +2290,7 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
break;
}
if (convert) {
TCGOpcode xor_opc, neg_opc;
TCGOpcode neg_opc;
if (!inv && !neg) {
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
@ -2298,11 +2299,9 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
switch (ctx->type) {
case TCG_TYPE_I32:
neg_opc = INDEX_op_neg_i32;
xor_opc = INDEX_op_xor_i32;
break;
case TCG_TYPE_I64:
neg_opc = INDEX_op_neg_i64;
xor_opc = INDEX_op_xor_i64;
break;
default:
g_assert_not_reached();
@ -2314,7 +2313,7 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
op->opc = INDEX_op_add;
op->args[2] = arg_new_constant(ctx, -1);
} else {
op->opc = xor_opc;
op->opc = INDEX_op_xor;
op->args[2] = arg_new_constant(ctx, 1);
}
return -1;
@ -2325,7 +2324,7 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
{
TCGOpcode xor_opc, neg_opc, shr_opc;
TCGOpcode neg_opc, shr_opc;
TCGOpcode uext_opc = 0, sext_opc = 0;
TCGCond cond = op->args[3];
TCGArg ret, src1, src2;
@ -2347,7 +2346,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
switch (ctx->type) {
case TCG_TYPE_I32:
xor_opc = INDEX_op_xor_i32;
shr_opc = INDEX_op_shr_i32;
neg_opc = INDEX_op_neg_i32;
if (TCG_TARGET_extract_valid(TCG_TYPE_I32, sh, 1)) {
@ -2358,7 +2356,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
}
break;
case TCG_TYPE_I64:
xor_opc = INDEX_op_xor_i64;
shr_opc = INDEX_op_shr_i64;
neg_opc = INDEX_op_neg_i64;
if (TCG_TARGET_extract_valid(TCG_TYPE_I64, sh, 1)) {
@ -2406,7 +2403,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
op2->args[1] = ret;
op2->args[2] = arg_new_constant(ctx, -1);
} else if (inv) {
op2 = opt_insert_after(ctx, op, xor_opc, 3);
op2 = opt_insert_after(ctx, op, INDEX_op_xor, 3);
op2->args[0] = ret;
op2->args[1] = ret;
op2->args[2] = arg_new_constant(ctx, 1);
@ -3051,7 +3048,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(sub2):
done = fold_sub2(&ctx, op);
break;
CASE_OP_32_64_VEC(xor):
case INDEX_op_xor:
case INDEX_op_xor_vec:
done = fold_xor(&ctx, op);
break;
case INDEX_op_set_label:

4
tcg/tcg-op.c
View File

@ -453,7 +453,7 @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
tcg_gen_op3_i32(INDEX_op_xor, ret, arg1, arg2);
}
void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
@ -1595,7 +1595,7 @@ void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_REG_BITS == 64) {
tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
tcg_gen_op3_i64(INDEX_op_xor, ret, arg1, arg2);
} else {
tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));

9
tcg/tcg.c
View File

@ -1009,8 +1009,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_xor_i32, TCGOutOpBinary, outop_xor),
OUTOP(INDEX_op_xor_i64, TCGOutOpBinary, outop_xor),
OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
};
#undef OUTOP
@ -2215,6 +2214,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_and:
case INDEX_op_mov:
case INDEX_op_or:
case INDEX_op_xor:
return has_type;
case INDEX_op_setcond_i32:
@ -2231,7 +2231,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i32:
case INDEX_op_neg_i32:
case INDEX_op_mul_i32:
case INDEX_op_xor_i32:
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
@ -2308,7 +2307,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i64:
case INDEX_op_neg_i64:
case INDEX_op_mul_i64:
case INDEX_op_xor_i64:
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
@ -5442,8 +5440,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_andc:
case INDEX_op_or:
case INDEX_op_orc:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_xor:
{
const TCGOutOpBinary *out =
container_of(all_outop[op->opc], TCGOutOpBinary, base);

5
tcg/tci.c
View File

@ -543,7 +543,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] | regs[r2];
break;
CASE_32_64(xor)
case INDEX_op_xor:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
@ -1083,12 +1083,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_andc:
case INDEX_op_or:
case INDEX_op_orc:
case INDEX_op_xor:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
case INDEX_op_nand_i32:

2
tcg/tci/tcg-target.c.inc
View File

@ -687,7 +687,7 @@ static const TCGOutOpBinary outop_orc = {
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, glue(INDEX_op_xor_i,TCG_TARGET_REG_BITS), a0, a1, a2);
tcg_out_op_rrr(s, INDEX_op_xor, a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {

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