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@ -1514,32 +1514,6 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, |
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tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); |
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} |
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static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) |
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{ |
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/* With MIE3, and bit 0 of m4 set, we get the complete result. */ |
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if (HAVE_FACILITY(MISC_INSN_EXT3)) { |
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if (type == TCG_TYPE_I32) { |
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tcg_out_ext32u(s, dest, src); |
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src = dest; |
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} |
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tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); |
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return; |
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} |
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/* Without MIE3, each byte gets the count of bits for the byte. */ |
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tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); |
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/* Multiply to sum each byte at the top of the word. */ |
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if (type == TCG_TYPE_I32) { |
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tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); |
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tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); |
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} else { |
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tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); |
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tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); |
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tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); |
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} |
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} |
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static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, |
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int ofs, int len, int z) |
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{ |
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@ -2268,6 +2242,37 @@ static const TCGOutOpBinary outop_clz = { |
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.out_rri = tgen_clzi, |
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}; |
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static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) |
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{ |
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/* With MIE3, and bit 0 of m4 set, we get the complete result. */ |
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if (HAVE_FACILITY(MISC_INSN_EXT3)) { |
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if (type == TCG_TYPE_I32) { |
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tcg_out_ext32u(s, dest, src); |
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src = dest; |
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} |
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tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); |
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return; |
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} |
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/* Without MIE3, each byte gets the count of bits for the byte. */ |
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tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); |
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/* Multiply to sum each byte at the top of the word. */ |
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if (type == TCG_TYPE_I32) { |
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tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); |
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tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); |
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} else { |
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tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); |
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tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); |
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tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); |
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} |
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} |
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static const TCGOutOpUnary outop_ctpop = { |
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.base.static_constraint = C_O1_I1(r, r), |
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.out_rr = tgen_ctpop, |
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}; |
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static const TCGOutOpBinary outop_ctz = { |
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.base.static_constraint = C_NotImplemented, |
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}; |
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@ -2914,13 +2919,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, |
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tgen_sextract(s, args[0], args[1], args[2], args[3]); |
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break; |
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case INDEX_op_ctpop_i32: |
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tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); |
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break; |
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case INDEX_op_ctpop_i64: |
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tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); |
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break; |
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case INDEX_op_mb: |
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/* The host memory model is quite strong, we simply need to |
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serialize the instruction stream. */ |
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@ -3429,8 +3427,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) |
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case INDEX_op_extract_i64: |
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case INDEX_op_sextract_i32: |
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case INDEX_op_sextract_i64: |
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case INDEX_op_ctpop_i32: |
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case INDEX_op_ctpop_i64: |
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return C_O1_I1(r, r); |
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case INDEX_op_qemu_ld_i32: |
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Richard Henderson
1 year ago