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@ -1234,8 +1234,8 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) |
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{ |
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uint32_t palcode; |
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int32_t disp21, disp16, disp12; |
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uint16_t fn11, fn16; |
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uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit, real_islit; |
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uint16_t fn11; |
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uint8_t opc, ra, rb, rc, fpfn, fn7, fn2, islit, real_islit; |
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uint8_t lit; |
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int ret; |
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@ -1244,7 +1244,6 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) |
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ra = (insn >> 21) & 0x1F; |
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rb = (insn >> 16) & 0x1F; |
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rc = insn & 0x1F; |
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sbz = (insn >> 13) & 0x07; |
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real_islit = islit = (insn >> 12) & 1; |
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if (rb == 31 && !islit) { |
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islit = 1; |
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@ -1255,7 +1254,6 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) |
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disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
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disp16 = (int16_t)(insn & 0x0000FFFF); |
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disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
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fn16 = insn & 0x0000FFFF; |
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fn11 = (insn >> 5) & 0x000007FF; |
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fpfn = fn11 & 0x3F; |
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fn7 = (insn >> 5) & 0x0000007F; |
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@ -1290,7 +1288,6 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) |
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if (ctx->mem_idx & 1) |
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goto invalid_opc; |
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gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); |
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ret = 3; |
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} |
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#endif |
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/* Invalid PAL call */ |
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@ -3140,8 +3137,8 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
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env->ipr[IPR_EXC_MASK] = 0; |
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#else |
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{ |
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uint64_t hwpcb; |
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hwpcb = env->ipr[IPR_PCBB]; |
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// uint64_t hwpcb;
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// hwpcb = env->ipr[IPR_PCBB];
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env->ipr[IPR_ASN] = 0; |
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env->ipr[IPR_ASTEN] = 0; |
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env->ipr[IPR_ASTSR] = 0; |
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