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Change terminology to match the KVM one, as APIC is x86-specific. And move out whpx_irqchip_in_kernel() to make it usable from common code even when not compiling with WHPX support. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Mohamed Mediouni
2 months ago
committed by
Peter Maydell
Peter Maydell
14 changed files with 270 additions and 23 deletions
@ -0,0 +1,237 @@ |
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/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/*
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* ARM Generic Interrupt Controller using HVF platform support |
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* |
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* Copyright (c) 2025 Mohamed Mediouni |
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* Based on vGICv3 KVM code by Pavel Fedin |
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* |
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*/ |
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#include "qemu/osdep.h" |
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#include "qapi/error.h" |
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#include "hw/intc/arm_gicv3_common.h" |
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#include "qemu/error-report.h" |
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#include "qemu/module.h" |
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#include "system/runstate.h" |
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#include "system/whpx.h" |
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#include "system/whpx-internal.h" |
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#include "gicv3_internal.h" |
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#include "vgic_common.h" |
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#include "migration/blocker.h" |
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#include "qom/object.h" |
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#include "target/arm/cpregs.h" |
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#include "hw/arm/bsa.h" |
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#include <winhvplatform.h> |
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#include <winhvplatformdefs.h> |
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#include <winnt.h> |
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struct WHPXARMGICv3Class { |
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ARMGICv3CommonClass parent_class; |
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DeviceRealize parent_realize; |
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ResettablePhases parent_phases; |
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}; |
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OBJECT_DECLARE_TYPE(GICv3State, WHPXARMGICv3Class, WHPX_GICV3) |
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/* TODO: Implement GIC state save-restore */ |
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static void whpx_gicv3_check(GICv3State *s) |
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{ |
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} |
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static void whpx_gicv3_put(GICv3State *s) |
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{ |
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whpx_gicv3_check(s); |
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} |
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static void whpx_gicv3_get(GICv3State *s) |
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{ |
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} |
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static void whpx_gicv3_set_irq(void *opaque, int irq, int level) |
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{ |
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struct whpx_state *whpx = &whpx_global; |
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GICv3State *s = opaque; |
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WHV_INTERRUPT_CONTROL interrupt_control = { |
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.InterruptControl.InterruptType = WHvArm64InterruptTypeFixed, |
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.RequestedVector = GIC_INTERNAL + irq, |
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.InterruptControl.Asserted = level |
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}; |
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if (irq > s->num_irq) { |
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return; |
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} |
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whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control, |
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sizeof(interrupt_control)); |
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} |
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static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
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{ |
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GICv3CPUState *c; |
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c = env->gicv3state; |
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c->icc_pmr_el1 = 0; |
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/*
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* Architecturally the reset value of the ICC_BPR registers |
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* is UNKNOWN. We set them all to 0 here; when the kernel |
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* uses these values to program the ICH_VMCR_EL2 fields that |
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* determine the guest-visible ICC_BPR register values, the |
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* hardware's "writing a value less than the minimum sets |
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* the field to the minimum value" behaviour will result in |
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* them effectively resetting to the correct minimum value |
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* for the host GIC. |
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*/ |
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c->icc_bpr[GICV3_G0] = 0; |
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c->icc_bpr[GICV3_G1] = 0; |
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c->icc_bpr[GICV3_G1NS] = 0; |
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c->icc_sre_el1 = 0x7; |
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memset(c->icc_apr, 0, sizeof(c->icc_apr)); |
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memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); |
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} |
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static void whpx_gicv3_reset_hold(Object *obj, ResetType type) |
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{ |
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GICv3State *s = ARM_GICV3_COMMON(obj); |
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WHPXARMGICv3Class *kgc = WHPX_GICV3_GET_CLASS(s); |
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if (kgc->parent_phases.hold) { |
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kgc->parent_phases.hold(obj, type); |
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} |
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whpx_gicv3_put(s); |
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} |
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/*
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* CPU interface registers of GIC needs to be reset on CPU reset. |
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* For the calling arm_gicv3_icc_reset() on CPU reset, we register |
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* below ARMCPRegInfo. As we reset the whole cpu interface under single |
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* register reset, we define only one register of CPU interface instead |
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* of defining all the registers. |
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*/ |
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static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { |
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{ .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, |
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, |
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/*
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* If ARM_CP_NOP is used, resetfn is not called, |
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* So ARM_CP_NO_RAW is appropriate type. |
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*/ |
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.type = ARM_CP_NO_RAW, |
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.access = PL1_RW, |
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.readfn = arm_cp_read_zero, |
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.writefn = arm_cp_write_ignore, |
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/*
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* We hang the whole cpu interface reset routine off here |
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* rather than parcelling it out into one little function |
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* per register |
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*/ |
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.resetfn = whpx_gicv3_icc_reset, |
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}, |
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}; |
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static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE val) |
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{ |
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struct whpx_state *whpx = &whpx_global; |
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HRESULT hr; |
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hr = whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, cpu->cpu_index, |
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®, 1, &val); |
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if (FAILED(hr)) { |
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error_report("WHPX: Failed to set register %08x, hr=%08lx", reg, hr); |
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} |
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} |
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static void whpx_gicv3_realize(DeviceState *dev, Error **errp) |
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{ |
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ERRP_GUARD(); |
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GICv3State *s = WHPX_GICV3(dev); |
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WHPXARMGICv3Class *kgc = WHPX_GICV3_GET_CLASS(s); |
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int i; |
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kgc->parent_realize(dev, errp); |
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if (*errp) { |
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return; |
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} |
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if (s->revision != 3) { |
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error_setg(errp, "unsupported GIC revision %d for platform GIC", |
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s->revision); |
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return; |
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} |
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if (s->security_extn) { |
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error_setg(errp, "the platform vGICv3 does not implement the " |
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"security extensions"); |
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return; |
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} |
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if (s->nmi_support) { |
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error_setg(errp, "NMI is not supported with the platform GIC"); |
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return; |
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} |
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if (s->nb_redist_regions > 1) { |
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error_setg(errp, "Multiple VGICv3 redistributor regions are not " |
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"supported by WHPX"); |
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error_append_hint(errp, "A maximum of %d VCPUs can be used", |
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s->redist_region_count[0]); |
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return; |
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} |
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gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL); |
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for (i = 0; i < s->num_cpu; i++) { |
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CPUState *cpu_state = qemu_get_cpu(i); |
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ARMCPU *cpu = ARM_CPU(cpu_state); |
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WHV_REGISTER_VALUE val = {.Reg64 = 0x080A0000 + (GICV3_REDIST_SIZE * i)}; |
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whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val); |
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define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); |
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} |
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if (s->maint_irq) { |
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error_setg(errp, "Nested virtualisation not currently supported by WHPX."); |
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return; |
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} |
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error_setg(&s->migration_blocker, |
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"Live migration disabled because GIC state save/restore not supported on WHPX"); |
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if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { |
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error_report_err(*errp); |
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} |
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} |
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static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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ResettableClass *rc = RESETTABLE_CLASS(klass); |
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ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); |
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WHPXARMGICv3Class *kgc = WHPX_GICV3_CLASS(klass); |
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agcc->pre_save = whpx_gicv3_get; |
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agcc->post_load = whpx_gicv3_put; |
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device_class_set_parent_realize(dc, whpx_gicv3_realize, |
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&kgc->parent_realize); |
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resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NULL, |
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&kgc->parent_phases); |
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} |
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static const TypeInfo whpx_arm_gicv3_info = { |
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.name = TYPE_WHPX_GICV3, |
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.parent = TYPE_ARM_GICV3_COMMON, |
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.instance_size = sizeof(GICv3State), |
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.class_init = whpx_gicv3_class_init, |
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.class_size = sizeof(WHPXARMGICv3Class), |
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}; |
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static void whpx_gicv3_register_types(void) |
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{ |
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type_register_static(&whpx_arm_gicv3_info); |
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} |
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type_init(whpx_gicv3_register_types) |
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