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trivial: Simplify the spots that use TARGET_BIG_ENDIAN as a numeric value 

TARGET_BIG_ENDIAN is *always* defined, either as 0 for little endian
targets or as 1 for big endian targets. So we can use this as a value
directly in places that need such a 0 or 1 for some reason, instead
of taking a detour through an additional local variable or something
similar.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
pull/251/head
Thomas Huth 3 years ago
committed by Michael Tokarev
parent
d417e2214d
commit
ded625e7aa
9 changed files with 18 additions and 75 deletions
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  1. 6
      cpu.c
  2. 9
      hw/microblaze/boot.c
  3. 10
      hw/mips/jazz.c
  4. 21
      hw/mips/malta.c
  5. 9
      hw/mips/mipssim.c
  6. 9
      hw/nios2/boot.c
  7. 7
      hw/xtensa/sim.c
  8. 10
      hw/xtensa/xtfpga.c
  9. 12
      target/arm/cpu.h

6
cpu.c
View File

@ -420,11 +420,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
bool target_words_bigendian(void) bool target_words_bigendian(void)
{ {
#if TARGET_BIG_ENDIAN return TARGET_BIG_ENDIAN;
return true;
#else
return false;
#endif
} }
const char *target_name(void) const char *target_name(void)

9
hw/microblaze/boot.c
View File

@ -140,22 +140,17 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
int kernel_size; int kernel_size;
uint64_t entry, high; uint64_t entry, high;
uint32_t base32; uint32_t base32;
int big_endian = 0;
#if TARGET_BIG_ENDIAN
big_endian = 1;
#endif
/* Boots a kernel elf binary. */ /* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
&entry, NULL, &high, NULL, &entry, NULL, &high, NULL,
big_endian, EM_MICROBLAZE, 0, 0); TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0);
base32 = entry; base32 = entry;
if (base32 == 0xc0000000) { if (base32 == 0xc0000000) {
kernel_size = load_elf(kernel_filename, NULL, kernel_size = load_elf(kernel_filename, NULL,
translate_kernel_address, NULL, translate_kernel_address, NULL,
&entry, NULL, NULL, NULL, &entry, NULL, NULL, NULL,
big_endian, EM_MICROBLAZE, 0, 0); TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0);
} }
/* Always boot into physical ram. */ /* Always boot into physical ram. */
boot_info.bootstrap_pc = (uint32_t)entry; boot_info.bootstrap_pc = (uint32_t)entry;

10
hw/mips/jazz.c
View File

@ -125,7 +125,7 @@ static void mips_jazz_init(MachineState *machine,
{ {
MemoryRegion *address_space = get_system_memory(); MemoryRegion *address_space = get_system_memory();
char *filename; char *filename;
int bios_size, n, big_endian; int bios_size, n;
Clock *cpuclk; Clock *cpuclk;
MIPSCPU *cpu; MIPSCPU *cpu;
MIPSCPUClass *mcc; MIPSCPUClass *mcc;
@ -157,12 +157,6 @@ static void mips_jazz_init(MachineState *machine,
[JAZZ_PICA61] = {33333333, 4}, [JAZZ_PICA61] = {33333333, 4},
}; };
#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
#endif
if (machine->ram_size > 256 * MiB) { if (machine->ram_size > 256 * MiB) {
error_report("RAM size more than 256Mb is not supported"); error_report("RAM size more than 256Mb is not supported");
exit(EXIT_FAILURE); exit(EXIT_FAILURE);
@ -301,7 +295,7 @@ static void mips_jazz_init(MachineState *machine,
dev = qdev_new("dp8393x"); dev = qdev_new("dp8393x");
qdev_set_nic_properties(dev, nd); qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2); qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_bit(dev, "big_endian", big_endian > 0); qdev_prop_set_bit(dev, "big_endian", TARGET_BIG_ENDIAN);
object_property_set_link(OBJECT(dev), "dma_mr", object_property_set_link(OBJECT(dev), "dma_mr",
OBJECT(rc4030_dma_mr), &error_abort); OBJECT(rc4030_dma_mr), &error_abort);
sysbus = SYS_BUS_DEVICE(dev); sysbus = SYS_BUS_DEVICE(dev);

21
hw/mips/malta.c
View File

@ -870,7 +870,6 @@ static uint64_t load_kernel(void)
uint64_t kernel_entry, kernel_high, initrd_size; uint64_t kernel_entry, kernel_high, initrd_size;
long kernel_size; long kernel_size;
ram_addr_t initrd_offset; ram_addr_t initrd_offset;
int big_endian;
uint32_t *prom_buf; uint32_t *prom_buf;
long prom_size; long prom_size;
int prom_index = 0; int prom_index = 0;
@ -878,16 +877,10 @@ static uint64_t load_kernel(void)
char rng_seed_hex[sizeof(rng_seed) * 2 + 1]; char rng_seed_hex[sizeof(rng_seed) * 2 + 1];
size_t rng_seed_prom_offset; size_t rng_seed_prom_offset;
#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
#endif
kernel_size = load_elf(loaderparams.kernel_filename, NULL, kernel_size = load_elf(loaderparams.kernel_filename, NULL,
cpu_mips_kseg0_to_phys, NULL, cpu_mips_kseg0_to_phys, NULL,
&kernel_entry, NULL, &kernel_entry, NULL,
&kernel_high, NULL, big_endian, EM_MIPS, &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS,
1, 0); 1, 0);
if (kernel_size < 0) { if (kernel_size < 0) {
error_report("could not load kernel '%s': %s", error_report("could not load kernel '%s': %s",
@ -1107,7 +1100,6 @@ void mips_malta_init(MachineState *machine)
I2CBus *smbus; I2CBus *smbus;
DriveInfo *dinfo; DriveInfo *dinfo;
int fl_idx = 0; int fl_idx = 0;
int be;
MaltaState *s; MaltaState *s;
PCIDevice *piix4; PCIDevice *piix4;
DeviceState *dev; DeviceState *dev;
@ -1144,12 +1136,6 @@ void mips_malta_init(MachineState *machine)
ram_low_postio); ram_low_postio);
} }
#if TARGET_BIG_ENDIAN
be = 1;
#else
be = 0;
#endif
/* FPGA */ /* FPGA */
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
@ -1161,7 +1147,8 @@ void mips_malta_init(MachineState *machine)
FLASH_SIZE, FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
65536, 65536,
4, 0x0000, 0x0000, 0x0000, 0x0000, be); 4, 0x0000, 0x0000, 0x0000, 0x0000,
TARGET_BIG_ENDIAN);
bios = pflash_cfi01_get_memory(fl); bios = pflash_cfi01_get_memory(fl);
fl_idx++; fl_idx++;
if (kernel_filename) { if (kernel_filename) {
@ -1245,7 +1232,7 @@ void mips_malta_init(MachineState *machine)
/* Northbridge */ /* Northbridge */
dev = qdev_new("gt64120"); dev = qdev_new("gt64120");
qdev_prop_set_bit(dev, "cpu-little-endian", !be); qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);

9
hw/mips/mipssim.c
View File

@ -62,18 +62,11 @@ static uint64_t load_kernel(void)
uint64_t entry, kernel_high, initrd_size; uint64_t entry, kernel_high, initrd_size;
long kernel_size; long kernel_size;
ram_addr_t initrd_offset; ram_addr_t initrd_offset;
int big_endian;
#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
#endif
kernel_size = load_elf(loaderparams.kernel_filename, NULL, kernel_size = load_elf(loaderparams.kernel_filename, NULL,
cpu_mips_kseg0_to_phys, NULL, cpu_mips_kseg0_to_phys, NULL,
&entry, NULL, &entry, NULL,
&kernel_high, NULL, big_endian, &kernel_high, NULL, TARGET_BIG_ENDIAN,
EM_MIPS, 1, 0); EM_MIPS, 1, 0);
if (kernel_size < 0) { if (kernel_size < 0) {
error_report("could not load kernel '%s': %s", error_report("could not load kernel '%s': %s",

9
hw/nios2/boot.c
View File

@ -148,16 +148,11 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
if (kernel_filename) { if (kernel_filename) {
int kernel_size, fdt_size; int kernel_size, fdt_size;
uint64_t entry, high; uint64_t entry, high;
int big_endian = 0;
#if TARGET_BIG_ENDIAN
big_endian = 1;
#endif
/* Boots a kernel elf binary. */ /* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
&entry, NULL, &high, NULL, &entry, NULL, &high, NULL,
big_endian, EM_ALTERA_NIOS2, 0, 0); TARGET_BIG_ENDIAN, EM_ALTERA_NIOS2, 0, 0);
if ((uint32_t)entry == 0xc0000000) { if ((uint32_t)entry == 0xc0000000) {
/* /*
* The Nios II processor reference guide documents that the * The Nios II processor reference guide documents that the
@ -168,7 +163,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
kernel_size = load_elf(kernel_filename, NULL, kernel_size = load_elf(kernel_filename, NULL,
translate_kernel_address, NULL, translate_kernel_address, NULL,
&entry, NULL, NULL, NULL, &entry, NULL, NULL, NULL,
big_endian, EM_ALTERA_NIOS2, 0, 0); TARGET_BIG_ENDIAN, EM_ALTERA_NIOS2, 0, 0);
boot_info.bootstrap_pc = ddr_base + 0xc0000000 + boot_info.bootstrap_pc = ddr_base + 0xc0000000 +
(entry & 0x07ffffff); (entry & 0x07ffffff);
} else { } else {

7
hw/xtensa/sim.c
View File

@ -96,16 +96,11 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine)
void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine) void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine)
{ {
const char *kernel_filename = machine->kernel_filename; const char *kernel_filename = machine->kernel_filename;
#if TARGET_BIG_ENDIAN
int big_endian = true;
#else
int big_endian = false;
#endif
if (kernel_filename) { if (kernel_filename) {
uint64_t elf_entry; uint64_t elf_entry;
int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
&elf_entry, NULL, NULL, NULL, big_endian, &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN,
EM_XTENSA, 0, 0); EM_XTENSA, 0, 0);
if (success > 0) { if (success > 0) {

10
hw/xtensa/xtfpga.c
View File

@ -219,11 +219,6 @@ static const MemoryRegionOps xtfpga_io_ops = {
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
{ {
#if TARGET_BIG_ENDIAN
int be = 1;
#else
int be = 0;
#endif
MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_memory = get_system_memory();
XtensaCPU *cpu = NULL; XtensaCPU *cpu = NULL;
CPUXtensaState *env = NULL; CPUXtensaState *env = NULL;
@ -316,7 +311,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) { if (dinfo) {
flash = xtfpga_flash_init(system_io, board, dinfo, be); flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN);
} }
/* Use presence of kernel file name as 'boot from SRAM' switch. */ /* Use presence of kernel file name as 'boot from SRAM' switch. */
@ -412,7 +407,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
uint64_t elf_entry; uint64_t elf_entry;
int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
&elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN,
EM_XTENSA, 0, 0);
if (success > 0) { if (success > 0) {
entry_point = elf_entry; entry_point = elf_entry;
} else { } else {

12
target/arm/cpu.h
View File

@ -3208,11 +3208,7 @@ static inline bool bswap_code(bool sctlr_b)
* The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
* would also end up as a mixed-endian mode with BE code, LE data. * would also end up as a mixed-endian mode with BE code, LE data.
*/ */
return return TARGET_BIG_ENDIAN ^ sctlr_b;
#if TARGET_BIG_ENDIAN
1 ^
#endif
sctlr_b;
#else #else
/* All code access in ARM is little endian, and there are no loaders /* All code access in ARM is little endian, and there are no loaders
* doing swaps that need to be reversed * doing swaps that need to be reversed
@ -3224,11 +3220,7 @@ static inline bool bswap_code(bool sctlr_b)
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
static inline bool arm_cpu_bswap_data(CPUARMState *env) static inline bool arm_cpu_bswap_data(CPUARMState *env)
{ {
return return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env);
#if TARGET_BIG_ENDIAN
1 ^
#endif
arm_cpu_data_is_big_endian(env);
} }
#endif #endif

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