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@ -52,7 +52,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) |
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); |
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); |
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RISCVCPU *cpu = RISCV_CPU(cs); |
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RISCVCPU *cpu = RISCV_CPU(cs); |
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CPURISCVState *env = &cpu->env; |
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CPURISCVState *env = &cpu->env; |
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target_ulong tmp; |
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uint64_t tmp; |
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if (n < 32) { |
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if (n < 32) { |
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tmp = env->gpr[n]; |
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tmp = env->gpr[n]; |
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@ -80,7 +80,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
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RISCVCPU *cpu = RISCV_CPU(cs); |
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RISCVCPU *cpu = RISCV_CPU(cs); |
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CPURISCVState *env = &cpu->env; |
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CPURISCVState *env = &cpu->env; |
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int length = 0; |
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int length = 0; |
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target_ulong tmp; |
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uint64_t tmp; |
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switch (mcc->def->misa_mxl_max) { |
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switch (mcc->def->misa_mxl_max) { |
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case MXL_RV32: |
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case MXL_RV32: |
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@ -194,7 +194,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n) |
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const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8; |
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const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8; |
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if (n < CSR_TABLE_SIZE) { |
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if (n < CSR_TABLE_SIZE) { |
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target_ulong val = ldn_p(mem_buf, regsz); |
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uint64_t val = ldn_p(mem_buf, regsz); |
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int result; |
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int result; |
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result = riscv_csrrw_debug(env, n, NULL, val, -1); |
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result = riscv_csrrw_debug(env, n, NULL, val, -1); |
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@ -215,7 +215,7 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n) |
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CPURISCVState *env = &cpu->env; |
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CPURISCVState *env = &cpu->env; |
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/* Per RiscV debug spec v1.0.0 rc4 */ |
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/* Per RiscV debug spec v1.0.0 rc4 */ |
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target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0; |
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uint32_t vbit = (env->virt_enabled) ? BIT(2) : 0; |
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return gdb_get_regl(buf, env->priv | vbit); |
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return gdb_get_regl(buf, env->priv | vbit); |
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#endif |
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#endif |
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