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-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJZSBP2AAoJEK0ScMxN0CebnyMH/1ZiDhYiqCD7PYfk4/Y7Db+h MNKNozrWKyChWQp1RzwWqcBaIzbuMZkDYn8dfS419PNtFRNoYtHjhYvjSTfcrxS0 U8dGOoqQUHCr/jlyIDUE4y5+aFA9R/1Ih5IQv+QCi5QNXcfeST8zcYF+ImuikP6C 7heIc7dE9kXdA8ycWJ39kYErHK9qEJbvDx6dxMPmb4cM36U239Zb9so985TXULlQ LoHrDpOCBzCbsICBE8iP2RKDvcwENIx21Dwv+9gW/NqR+nRdKcxhTjKEodkS8gl/ UxMxM/TjIPQOLLUhdck5DFgIgBgQWHRqPMJKqt466I0JlXvSpifmWxckWzslXLc= =R+em -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170619' into staging Queued TCG patches # gpg: Signature made Mon 19 Jun 2017 19:12:06 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170619: target/arm: Exit after clearing aarch64 interrupt mask target/s390x: Exit after changing PSW mask target/alpha: Use tcg_gen_lookup_and_goto_ptr tcg: Increase hit rate of lookup_tb_ptr tcg/arm: Use ldr (literal) for goto_tb tcg/arm: Try pc-relative addresses for movi tcg/arm: Remove limit on code buffer size tcg/arm: Use indirect branch for goto_tb tcg/aarch64: Use ADR in tcg_out_movi translate-all: consolidate tb init in tb_gen_code tcg: allocate TB structs before the corresponding translated code util: add cacheinfo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>pull/53/head
Peter Maydell
9 years ago
15 changed files with 345 additions and 152 deletions
@ -0,0 +1,185 @@ |
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/*
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* cacheinfo.c - helpers to query the host about its caches |
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* |
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* Copyright (C) 2017, Emilio G. Cota <cota@braap.org> |
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* License: GNU GPL, version 2 or later. |
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* See the COPYING file in the top-level directory. |
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*/ |
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|
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#include "qemu/osdep.h" |
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int qemu_icache_linesize = 0; |
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int qemu_dcache_linesize = 0; |
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/*
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* Operating system specific detection mechanisms. |
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*/ |
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#if defined(_AIX) |
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# include <sys/systemcfg.h> |
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static void sys_cache_info(int *isize, int *dsize) |
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{ |
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*isize = _system_configuration.icache_line; |
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*dsize = _system_configuration.dcache_line; |
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} |
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#elif defined(_WIN32) |
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static void sys_cache_info(int *isize, int *dsize) |
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{ |
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SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf; |
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DWORD size = 0; |
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BOOL success; |
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size_t i, n; |
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/* Check for the required buffer size first. Note that if the zero
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size we use for the probe results in success, then there is no |
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data available; fail in that case. */ |
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success = GetLogicalProcessorInformation(0, &size); |
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if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) { |
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return; |
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} |
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n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); |
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size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); |
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buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n); |
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if (!GetLogicalProcessorInformation(buf, &size)) { |
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goto fail; |
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} |
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for (i = 0; i < n; i++) { |
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if (buf[i].Relationship == RelationCache |
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&& buf[i].Cache.Level == 1) { |
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switch (buf[i].Cache.Type) { |
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case CacheUnified: |
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*isize = *dsize = buf[i].Cache.LineSize; |
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break; |
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case CacheInstruction: |
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*isize = buf[i].Cache.LineSize; |
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break; |
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case CacheData: |
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*dsize = buf[i].Cache.LineSize; |
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break; |
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default: |
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break; |
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} |
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} |
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} |
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fail: |
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g_free(buf); |
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} |
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|
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#elif defined(__APPLE__) \ |
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|| defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
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# include <sys/sysctl.h> |
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# if defined(__APPLE__) |
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# define SYSCTL_CACHELINE_NAME "hw.cachelinesize" |
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# else |
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# define SYSCTL_CACHELINE_NAME "machdep.cacheline_size" |
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# endif |
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static void sys_cache_info(int *isize, int *dsize) |
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{ |
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/* There's only a single sysctl for both I/D cache line sizes. */ |
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long size; |
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size_t len = sizeof(size); |
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if (!sysctlbyname(SYSCTL_CACHELINE_NAME, &size, &len, NULL, 0)) { |
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*isize = *dsize = size; |
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} |
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} |
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#else |
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/* POSIX */ |
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static void sys_cache_info(int *isize, int *dsize) |
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{ |
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# ifdef _SC_LEVEL1_ICACHE_LINESIZE |
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*isize = sysconf(_SC_LEVEL1_ICACHE_LINESIZE); |
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# endif |
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# ifdef _SC_LEVEL1_DCACHE_LINESIZE |
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*dsize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); |
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# endif |
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} |
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#endif /* sys_cache_info */ |
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/*
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* Architecture (+ OS) specific detection mechanisms. |
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*/ |
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#if defined(__aarch64__) |
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static void arch_cache_info(int *isize, int *dsize) |
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{ |
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if (*isize == 0 || *dsize == 0) { |
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unsigned ctr; |
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/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
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but (at least under Linux) these are marked protected by the |
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kernel. However, CTR_EL0 contains the minimum linesize in the |
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entire hierarchy, and is used by userspace cache flushing. */ |
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asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); |
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if (*isize == 0) { |
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*isize = 4 << (ctr & 0xf); |
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} |
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if (*dsize == 0) { |
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*dsize = 4 << ((ctr >> 16) & 0xf); |
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} |
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} |
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} |
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#elif defined(_ARCH_PPC) && defined(__linux__) |
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static void arch_cache_info(int *isize, int *dsize) |
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{ |
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if (*isize == 0) { |
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*isize = qemu_getauxval(AT_ICACHEBSIZE); |
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} |
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if (*dsize == 0) { |
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*dsize = qemu_getauxval(AT_DCACHEBSIZE); |
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} |
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} |
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#else |
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static void arch_cache_info(int *isize, int *dsize) { } |
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#endif /* arch_cache_info */ |
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/*
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* ... and if all else fails ... |
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*/ |
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static void fallback_cache_info(int *isize, int *dsize) |
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{ |
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/* If we can only find one of the two, assume they're the same. */ |
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if (*isize) { |
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if (*dsize) { |
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/* Success! */ |
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} else { |
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*dsize = *isize; |
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} |
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} else if (*dsize) { |
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*isize = *dsize; |
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} else { |
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#if defined(_ARCH_PPC) |
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/* For PPC, we're going to use the icache size computed for
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flush_icache_range. Which means that we must use the |
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architecture minimum. */ |
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*isize = *dsize = 16; |
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#else |
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/* Otherwise, 64 bytes is not uncommon. */ |
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*isize = *dsize = 64; |
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#endif |
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} |
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} |
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static void __attribute__((constructor)) init_cache_info(void) |
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{ |
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int isize = 0, dsize = 0; |
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sys_cache_info(&isize, &dsize); |
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arch_cache_info(&isize, &dsize); |
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fallback_cache_info(&isize, &dsize); |
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qemu_icache_linesize = isize; |
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qemu_dcache_linesize = dsize; |
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} |
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