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Instead of doing the full real to 64 bit dance we are attempting to leverage Xen's PVH boot spec to go from 32 bit to 64 bit. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>pull/81/head
Alex Bennée
7 years ago
3 changed files with 311 additions and 0 deletions
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/* |
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* x86_64 boot and support code |
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* |
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* Copyright 2019 Linaro |
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* |
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* This work is licensed under the terms of the GNU GPL, version 3 or later. |
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* See the COPYING file in the top-level directory. |
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* |
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* Unlike the i386 version we instead use Xen's PVHVM booting header |
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* which should drop us automatically into 32 bit mode ready to go. I've |
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* nabbed bits of the Linux kernel setup to achieve this. |
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* |
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* SPDX-License-Identifier: GPL-3.0-or-later |
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*/ |
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.section .head |
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#define ELFNOTE_START(name, type, flags) \ |
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.pushsection .note.name, flags,@note ; \ |
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.balign 4 ; \ |
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.long 2f - 1f /* namesz */ ; \ |
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.long 4484f - 3f /* descsz */ ; \ |
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.long type ; \ |
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1:.asciz #name ; \ |
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2:.balign 4 ; \ |
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3: |
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#define ELFNOTE_END \ |
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4484:.balign 4 ; \ |
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.popsection ; |
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#define ELFNOTE(name, type, desc) \ |
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ELFNOTE_START(name, type, "") \ |
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desc ; \ |
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ELFNOTE_END |
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#define XEN_ELFNOTE_ENTRY 1 |
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#define XEN_ELFNOTE_HYPERCALL_PAGE 2 |
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#define XEN_ELFNOTE_VIRT_BASE 3 |
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#define XEN_ELFNOTE_PADDR_OFFSET 4 |
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#define XEN_ELFNOTE_PHYS32_ENTRY 18 |
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#define __ASM_FORM(x) x |
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#define __ASM_FORM_RAW(x) x |
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#define __ASM_FORM_COMMA(x) x, |
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#define __ASM_SEL(a,b) __ASM_FORM(b) |
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#define __ASM_SEL_RAW(a,b) __ASM_FORM_RAW(b) |
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#define _ASM_PTR __ASM_SEL(.long, .quad) |
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ELFNOTE(Xen, XEN_ELFNOTE_VIRT_BASE, _ASM_PTR 0x100000) |
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ELFNOTE(Xen, XEN_ELFNOTE_ENTRY, _ASM_PTR _start) |
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ELFNOTE(Xen, XEN_ELFNOTE_PHYS32_ENTRY, _ASM_PTR _start) /* entry == virtbase */ |
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ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, _ASM_PTR 0) |
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/* |
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* Entry point for PVH guests. |
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* |
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* Xen ABI specifies the following register state when we come here: |
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* |
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* - `ebx`: contains the physical memory address where the loader has placed |
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* the boot start info structure. |
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* - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared. |
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* - `cr4`: all bits are cleared. |
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* - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’ |
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* and a limit of ‘0xFFFFFFFF’. The selector value is unspecified. |
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* - `ds`, `es`: must be a 32-bit read/write data segment with a base of |
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* ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all |
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* unspecified. |
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* - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit |
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* of '0x67'. |
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* - `eflags`: bit 17 (VM) must be cleared. Bit 9 (IF) must be cleared. |
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* Bit 8 (TF) must be cleared. Other bits are all unspecified. |
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* |
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* All other processor registers and flag bits are unspecified. The OS is in |
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* charge of setting up it's own stack, GDT and IDT. |
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*/ |
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.code32 |
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.section .text |
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.global _start |
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_start: |
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cld |
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lgdt gdtr |
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ljmp $0x8,$.Lloadcs |
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.Lloadcs: |
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mov $0x10,%eax |
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mov %eax,%ds |
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mov %eax,%es |
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mov %eax,%fs |
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mov %eax,%gs |
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mov %eax,%ss |
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/* Enable PAE mode (bit 5). */ |
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mov %cr4, %eax |
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btsl $5, %eax |
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mov %eax, %cr4 |
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#define MSR_EFER 0xc0000080 /* extended feature register */ |
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/* Enable Long mode. */ |
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mov $MSR_EFER, %ecx |
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rdmsr |
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btsl $8, %eax |
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wrmsr |
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/* Enable paging */ |
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mov $.Lpml4, %ecx |
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mov %ecx, %cr3 |
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mov %cr0, %eax |
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btsl $31, %eax |
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mov %eax, %cr0 |
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/* Jump to 64-bit mode. */ |
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lgdt gdtr64 |
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ljmp $0x8,$.Lenter64 |
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.code64 |
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.section .text |
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.Lenter64: |
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// Setup stack ASAP |
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movq $stack_end,%rsp |
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/* don't worry about stack frame, assume everthing is garbage when we return */ |
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call main |
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/* output any non-zero result in eax to isa-debug-exit device */ |
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test %al, %al |
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jz 1f |
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out %ax, $0xf4 |
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1: /* QEMU ACPI poweroff */ |
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mov $0x604,%edx |
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mov $0x2000,%eax |
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out %ax,%dx |
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hlt |
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jmp 1b |
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/* |
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* Helper Functions |
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* |
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* x86_64 calling convention is rdi, rsi, rdx, rcx, r8, r9 |
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*/ |
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/* Output a single character to serial port */ |
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.global __sys_outc |
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__sys_outc: |
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pushq %rax |
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mov %rax, %rdx |
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out %al,$0xE9 |
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popq %rax |
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ret |
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/* Interrupt Descriptor Table */ |
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.section .data |
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.align 16 |
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idt_00: .int 0, 0 |
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idt_01: .int 0, 0 |
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idt_02: .int 0, 0 |
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idt_03: .int 0, 0 |
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idt_04: .int 0, 0 |
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idt_05: .int 0, 0 |
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idt_06: .int 0, 0 /* intr_6_opcode, Invalid Opcode */ |
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idt_07: .int 0, 0 |
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idt_08: .int 0, 0 |
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idt_09: .int 0, 0 |
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idt_0A: .int 0, 0 |
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idt_0B: .int 0, 0 |
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idt_0C: .int 0, 0 |
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idt_0D: .int 0, 0 |
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idt_0E: .int 0, 0 |
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idt_0F: .int 0, 0 |
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idt_10: .int 0, 0 |
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idt_11: .int 0, 0 |
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idt_12: .int 0, 0 |
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idt_13: .int 0, 0 |
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idt_14: .int 0, 0 |
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idt_15: .int 0, 0 |
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idt_16: .int 0, 0 |
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idt_17: .int 0, 0 |
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idt_18: .int 0, 0 |
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idt_19: .int 0, 0 |
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idt_1A: .int 0, 0 |
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idt_1B: .int 0, 0 |
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idt_1C: .int 0, 0 |
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idt_1D: .int 0, 0 |
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idt_1E: .int 0, 0 |
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idt_1F: .int 0, 0 |
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/* |
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* Global Descriptor Table (GDT) |
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* |
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* This describes various memory areas (segments) through |
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* segment descriptors. In 32 bit mode each segment each |
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* segement is associated with segment registers which are |
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* implicitly (or explicitly) referenced depending on the |
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* instruction. However in 64 bit mode selectors are flat and |
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* segmented addressing isn't used. |
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*/ |
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gdt: |
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.short 0 |
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gdtr: |
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.short gdt_en - gdt - 1 |
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.int gdt |
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// Code cs: |
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.short 0xFFFF |
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.short 0 |
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.byte 0 |
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.byte 0x9b |
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.byte 0xCF |
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.byte 0 |
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// Data ds:, ss:, es:, fs:, and gs: |
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.short 0xFFFF |
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.short 0 |
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.byte 0 |
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.byte 0x93 |
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.byte 0xCF |
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.byte 0 |
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gdt_en: |
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gdt64: |
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.short 0 |
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gdtr64: |
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.short gdt64_en - gdt64 - 1 |
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.int gdt64 |
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// Code |
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.short 0xFFFF |
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.short 0 |
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.byte 0 |
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.byte 0x9b |
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.byte 0xAF |
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.byte 0 |
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// Data |
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.short 0xFFFF |
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.short 0 |
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.byte 0 |
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.byte 0x93 |
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.byte 0xCF |
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.byte 0 |
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gdt64_en: |
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.section .bss |
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.align 16 |
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stack: .space 65536 |
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stack_end: |
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.section .data |
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.align 4096 |
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.Lpd: |
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i = 0 |
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.rept 512 * 4 |
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.quad 0x1e7 | (i << 21) |
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i = i + 1 |
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.endr |
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.align 4096 |
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.Lpdp: |
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.quad .Lpd + 7 + 0 * 4096 /* 0-1 GB */ |
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.quad .Lpd + 7 + 1 * 4096 /* 1-2 GB */ |
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.quad .Lpd + 7 + 2 * 4096 /* 2-3 GB */ |
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.quad .Lpd + 7 + 3 * 4096 /* 3-4 GB */ |
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.align 4096 |
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.Lpml4: |
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.quad .Lpdp + 7 /* 0-512 GB */ |
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@ -0,0 +1,33 @@ |
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PHDRS { |
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text PT_LOAD FLAGS(5); /* R_E */ |
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note PT_NOTE FLAGS(0); /* ___ */ |
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} |
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SECTIONS { |
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. = 0x100000; |
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.text : { |
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__load_st = .; |
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*(.head) |
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*(.text) |
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} :text |
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.rodata : { |
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*(.rodata) |
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} :text |
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/* Keep build ID and PVH notes in same section */ |
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.notes : { |
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*(.note.*) |
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} :note |
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.data : { |
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*(.data) |
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__load_en = .; |
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} :text |
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.bss : { |
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*(.bss) |
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__bss_en = .; |
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} |
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} |
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