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hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() 

Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.

If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit
should be set or clear according to the Non-maskable property. And the RPR
priority should also update the NMI bit according to the APR priority NMI bit.

By the way, add gicv3_icv_nmiar1_read trace event.

If the hpp irq is a NMI, the icv iar read should return 1022 and trap for
NMI again

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: use cs->nmi_support instead of cs->gic->nmi_support]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
pull/265/head
Peter Maydell 2 years ago
parent
28cca59c46
commit
d2c0c6aab6
3 changed files with 98 additions and 12 deletions
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  1. 105
      hw/intc/arm_gicv3_cpuif.c
  2. 4
      hw/intc/gicv3_internal.h
  3. 1
      hw/intc/trace-events

105
hw/intc/arm_gicv3_cpuif.c
View File

@ -158,6 +158,10 @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
int i;
int aprmax = ich_num_aprs(cs);
if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) {
return 0x0;
}
for (i = 0; i < aprmax; i++) {
uint32_t apr = cs->ich_apr[GICV3_G0][i] |
cs->ich_apr[GICV3_G1NS][i];
@ -192,6 +196,7 @@ static int hppvi_index(GICv3CPUState *cs)
* correct behaviour.
*/
int prio = 0xff;
bool nmi = false;
if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
/* Both groups disabled, definitely nothing to do */
@ -200,6 +205,7 @@ static int hppvi_index(GICv3CPUState *cs)
for (i = 0; i < cs->num_list_regs; i++) {
uint64_t lr = cs->ich_lr_el2[i];
bool thisnmi;
int thisprio;
if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) {
@ -218,10 +224,12 @@ static int hppvi_index(GICv3CPUState *cs)
}
}
thisnmi = lr & ICH_LR_EL2_NMI;
thisprio = ich_lr_prio(lr);
if (thisprio < prio) {
if ((thisprio < prio) || ((thisprio == prio) && (thisnmi & (!nmi)))) {
prio = thisprio;
nmi = thisnmi;
idx = i;
}
}
@ -290,6 +298,7 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
* equivalent of these checks.
*/
int grp;
bool is_nmi;
uint32_t mask, prio, rprio, vpmr;
if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) {
@ -302,10 +311,11 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
*/
prio = ich_lr_prio(lr);
is_nmi = lr & ICH_LR_EL2_NMI;
vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
ICH_VMCR_EL2_VPMR_LENGTH);
if (prio >= vpmr) {
if (!is_nmi && prio >= vpmr) {
/* Priority mask masks this interrupt */
return false;
}
@ -327,6 +337,11 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
return true;
}
if ((prio & mask) == (rprio & mask) && is_nmi &&
!(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) {
return true;
}
return false;
}
@ -551,7 +566,11 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
if (cs->nmi_support) {
cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI);
} else {
cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
}
gicv3_cpuif_virt_irq_fiq_update(cs);
return;
@ -698,7 +717,11 @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int prio = ich_highest_active_virt_prio(cs);
uint64_t prio = ich_highest_active_virt_prio(cs);
if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) {
prio |= ICV_RPR_EL1_NMI;
}
trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio);
return prio;
@ -737,13 +760,19 @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp)
*/
uint32_t mask = icv_gprio_mask(cs, grp);
int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask;
bool nmi = cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI;
int aprbit = prio >> (8 - cs->vprebits);
int regno = aprbit / 32;
int regbit = aprbit % 32;
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT;
cs->ich_apr[grp][regno] |= (1 << regbit);
if (nmi) {
cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI;
} else {
cs->ich_apr[grp][regno] |= (1 << regbit);
}
}
static void icv_activate_vlpi(GICv3CPUState *cs)
@ -764,6 +793,7 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
int idx = hppvi_index(cs);
uint64_t intid = INTID_SPURIOUS;
int el = arm_current_el(env);
if (idx == HPPVI_INDEX_VLPI) {
if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) {
@ -773,11 +803,16 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
} else if (idx >= 0) {
uint64_t lr = cs->ich_lr_el2[idx];
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI;
if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
intid = ich_lr_vintid(lr);
if (!gicv3_intid_is_special(intid)) {
icv_activate_irq(cs, idx, grp);
if (!nmi) {
icv_activate_irq(cs, idx, grp);
} else {
intid = INTID_NMI;
}
} else {
/* Interrupt goes from Pending to Invalid */
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
@ -798,8 +833,37 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* todo */
GICv3CPUState *cs = icc_cs_from_env(env);
int idx = hppvi_index(cs);
uint64_t intid = INTID_SPURIOUS;
if (idx >= 0 && idx != HPPVI_INDEX_VLPI) {
uint64_t lr = cs->ich_lr_el2[idx];
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
if ((thisgrp == GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) {
intid = ich_lr_vintid(lr);
if (!gicv3_intid_is_special(intid)) {
if (lr & ICH_LR_EL2_NMI) {
icv_activate_irq(cs, idx, GICV3_G1NS);
} else {
intid = INTID_SPURIOUS;
}
} else {
/* Interrupt goes from Pending to Invalid */
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
/*
* We will now return the (bogus) ID from the list register,
* as per the pseudocode.
*/
}
}
}
trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid);
gicv3_cpuif_virt_update(cs);
return intid;
}
@ -1424,7 +1488,7 @@ static void icv_increment_eoicount(GICv3CPUState *cs)
ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1);
}
static int icv_drop_prio(GICv3CPUState *cs)
static int icv_drop_prio(GICv3CPUState *cs, bool *nmi)
{
/* Drop the priority of the currently active virtual interrupt
* (favouring group 0 if there is a set active bit at
@ -1446,6 +1510,12 @@ static int icv_drop_prio(GICv3CPUState *cs)
continue;
}
if (i == 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) {
*papr1 &= (~ICV_AP1R_EL1_NMI);
*nmi = true;
return 0xff;
}
/* We can't just use the bit-twiddling hack icc_drop_prio() does
* because we need to return the bit number we cleared so
* it can be compared against the list register's priority field.
@ -1505,6 +1575,7 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
int irq = value & 0xffffff;
int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
int idx, dropprio;
bool nmi = false;
trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
gicv3_redist_affid(cs), value);
@ -1517,8 +1588,8 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
* error checks" (because that lets us avoid scanning the AP
* registers twice).
*/
dropprio = icv_drop_prio(cs);
if (dropprio == 0xff) {
dropprio = icv_drop_prio(cs, &nmi);
if (dropprio == 0xff && !nmi) {
/* No active interrupt. It is CONSTRAINED UNPREDICTABLE
* whether the list registers are checked in this
* situation; we choose not to.
@ -1540,8 +1611,9 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t lr = cs->ich_lr_el2[idx];
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp);
bool thisnmi = lr & ICH_LR_EL2_NMI;
if (thisgrp == grp && lr_gprio == dropprio) {
if (thisgrp == grp && (lr_gprio == dropprio || (thisnmi & nmi))) {
if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) {
/*
* Priority drop and deactivate not split: deactivate irq now.
@ -2627,7 +2699,11 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
if (cs->nmi_support) {
cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI);
} else {
cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
}
gicv3_cpuif_virt_irq_fiq_update(cs);
}
@ -2744,6 +2820,11 @@ static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri,
8 - cs->vpribits, 0);
}
/* Enforce RES0 bit in NMI field when FEAT_GICv3_NMI is not implemented */
if (!cs->nmi_support) {
value &= ~ICH_LR_EL2_NMI;
}
cs->ich_lr_el2[regno] = value;
gicv3_cpuif_virt_update(cs);
}

4
hw/intc/gicv3_internal.h
View File

@ -246,6 +246,7 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
#define ICH_LR_EL2_PRIORITY_SHIFT 48
#define ICH_LR_EL2_PRIORITY_LENGTH 8
#define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
#define ICH_LR_EL2_NMI (1ULL << 59)
#define ICH_LR_EL2_GROUP (1ULL << 60)
#define ICH_LR_EL2_HW (1ULL << 61)
#define ICH_LR_EL2_STATE_SHIFT 62
@ -277,6 +278,9 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
#define ICH_VTR_EL2_PREBITS_SHIFT 26
#define ICH_VTR_EL2_PRIBITS_SHIFT 29
#define ICV_AP1R_EL1_NMI (1ULL << 63)
#define ICV_RPR_EL1_NMI (1ULL << 63)
/* ITS Registers */
FIELD(GITS_BASER, SIZE, 0, 8)

1
hw/intc/trace-events
View File

@ -152,6 +152,7 @@ gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu 0x%x valu
gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64
gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64
gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64
gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64
gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64
gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d"
gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d"

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