Browse Source
Applying the concept used for the *PICs once again: establish a base class for the i8254 that can be used both by the current user space emulation and the upcoming KVM in-kernel version. We share most of the public interface of the i8254, specifically to the pcspk, vmstate, reset and certain init parts. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>stable-1.1
Jan Kiszka
15 years ago
committed by
Avi Kivity
Avi Kivity
4 changed files with 424 additions and 239 deletions
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/*
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* QEMU 8253/8254 - common bits of emulated and KVM kernel model |
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* |
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* Copyright (c) 2003-2004 Fabrice Bellard |
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* Copyright (c) 2012 Jan Kiszka, Siemens AG |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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#include "hw.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "qemu-timer.h" |
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#include "i8254.h" |
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#include "i8254_internal.h" |
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/* val must be 0 or 1 */ |
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void pit_set_gate(ISADevice *dev, int channel, int val) |
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{ |
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PITCommonState *pit = PIT_COMMON(dev); |
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PITChannelState *s = &pit->channels[channel]; |
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PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); |
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c->set_channel_gate(pit, s, val); |
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} |
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/* get pit output bit */ |
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int pit_get_out(PITChannelState *s, int64_t current_time) |
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{ |
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uint64_t d; |
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int out; |
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
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get_ticks_per_sec()); |
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switch (s->mode) { |
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default: |
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case 0: |
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out = (d >= s->count); |
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break; |
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case 1: |
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out = (d < s->count); |
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break; |
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case 2: |
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if ((d % s->count) == 0 && d != 0) { |
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out = 1; |
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} else { |
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out = 0; |
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} |
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break; |
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case 3: |
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out = (d % s->count) < ((s->count + 1) >> 1); |
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break; |
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case 4: |
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case 5: |
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out = (d == s->count); |
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break; |
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} |
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return out; |
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} |
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/* return -1 if no transition will occur. */ |
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int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time) |
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{ |
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uint64_t d, next_time, base; |
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int period2; |
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
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get_ticks_per_sec()); |
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switch (s->mode) { |
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default: |
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case 0: |
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case 1: |
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if (d < s->count) { |
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next_time = s->count; |
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} else { |
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return -1; |
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} |
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break; |
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case 2: |
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base = (d / s->count) * s->count; |
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if ((d - base) == 0 && d != 0) { |
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next_time = base + s->count; |
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} else { |
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next_time = base + s->count + 1; |
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} |
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break; |
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case 3: |
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base = (d / s->count) * s->count; |
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period2 = ((s->count + 1) >> 1); |
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if ((d - base) < period2) { |
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next_time = base + period2; |
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} else { |
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next_time = base + s->count; |
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} |
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break; |
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case 4: |
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case 5: |
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if (d < s->count) { |
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next_time = s->count; |
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} else if (d == s->count) { |
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next_time = s->count + 1; |
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} else { |
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return -1; |
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} |
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break; |
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} |
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/* convert to timer units */ |
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next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(), |
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PIT_FREQ); |
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/* fix potential rounding problems */ |
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/* XXX: better solution: use a clock at PIT_FREQ Hz */ |
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if (next_time <= current_time) { |
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next_time = current_time + 1; |
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} |
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return next_time; |
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} |
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void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc, |
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PITChannelInfo *info) |
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{ |
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info->gate = sc->gate; |
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info->mode = sc->mode; |
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info->initial_count = sc->count; |
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info->out = pit_get_out(sc, qemu_get_clock_ns(vm_clock)); |
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} |
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void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info) |
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{ |
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PITCommonState *pit = PIT_COMMON(dev); |
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PITChannelState *s = &pit->channels[channel]; |
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PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); |
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c->get_channel_info(pit, s, info); |
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} |
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void pit_reset_common(PITCommonState *pit) |
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{ |
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PITChannelState *s; |
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int i; |
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for (i = 0; i < 3; i++) { |
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s = &pit->channels[i]; |
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s->mode = 3; |
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s->gate = (i != 2); |
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s->count_load_time = qemu_get_clock_ns(vm_clock); |
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s->count = 0x10000; |
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if (i == 0 && !s->irq_disabled) { |
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s->next_transition_time = |
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pit_get_next_transition_time(s, s->count_load_time); |
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} |
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} |
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} |
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static int pit_init_common(ISADevice *dev) |
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{ |
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PITCommonState *pit = PIT_COMMON(dev); |
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PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); |
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int ret; |
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ret = c->init(pit); |
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if (ret < 0) { |
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return ret; |
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} |
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isa_register_ioport(dev, &pit->ioports, pit->iobase); |
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qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2); |
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return 0; |
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} |
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static const VMStateDescription vmstate_pit_channel = { |
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.name = "pit channel", |
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.version_id = 2, |
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.minimum_version_id = 2, |
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.minimum_version_id_old = 2, |
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.fields = (VMStateField[]) { |
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VMSTATE_INT32(count, PITChannelState), |
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VMSTATE_UINT16(latched_count, PITChannelState), |
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VMSTATE_UINT8(count_latched, PITChannelState), |
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VMSTATE_UINT8(status_latched, PITChannelState), |
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VMSTATE_UINT8(status, PITChannelState), |
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VMSTATE_UINT8(read_state, PITChannelState), |
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VMSTATE_UINT8(write_state, PITChannelState), |
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VMSTATE_UINT8(write_latch, PITChannelState), |
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VMSTATE_UINT8(rw_mode, PITChannelState), |
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VMSTATE_UINT8(mode, PITChannelState), |
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VMSTATE_UINT8(bcd, PITChannelState), |
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VMSTATE_UINT8(gate, PITChannelState), |
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VMSTATE_INT64(count_load_time, PITChannelState), |
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VMSTATE_INT64(next_transition_time, PITChannelState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int pit_load_old(QEMUFile *f, void *opaque, int version_id) |
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{ |
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PITCommonState *pit = opaque; |
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PITChannelState *s; |
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int i; |
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if (version_id != 1) { |
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return -EINVAL; |
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} |
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for (i = 0; i < 3; i++) { |
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s = &pit->channels[i]; |
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s->count = qemu_get_be32(f); |
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qemu_get_be16s(f, &s->latched_count); |
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qemu_get_8s(f, &s->count_latched); |
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qemu_get_8s(f, &s->status_latched); |
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qemu_get_8s(f, &s->status); |
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qemu_get_8s(f, &s->read_state); |
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qemu_get_8s(f, &s->write_state); |
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qemu_get_8s(f, &s->write_latch); |
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qemu_get_8s(f, &s->rw_mode); |
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qemu_get_8s(f, &s->mode); |
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qemu_get_8s(f, &s->bcd); |
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qemu_get_8s(f, &s->gate); |
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s->count_load_time = qemu_get_be64(f); |
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s->irq_disabled = 0; |
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if (s->irq_timer) { |
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s->next_transition_time = qemu_get_be64(f); |
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qemu_get_timer(f, s->irq_timer); |
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} |
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} |
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return 0; |
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} |
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static void pit_dispatch_pre_save(void *opaque) |
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{ |
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PITCommonState *s = opaque; |
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PITCommonClass *c = PIT_COMMON_GET_CLASS(s); |
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if (c->pre_save) { |
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c->pre_save(s); |
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} |
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} |
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static int pit_dispatch_post_load(void *opaque, int version_id) |
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{ |
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PITCommonState *s = opaque; |
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PITCommonClass *c = PIT_COMMON_GET_CLASS(s); |
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if (c->post_load) { |
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c->post_load(s); |
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} |
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return 0; |
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} |
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static const VMStateDescription vmstate_pit_common = { |
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.name = "i8254", |
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.version_id = 3, |
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.minimum_version_id = 2, |
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.minimum_version_id_old = 1, |
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.load_state_old = pit_load_old, |
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.pre_save = pit_dispatch_pre_save, |
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.post_load = pit_dispatch_post_load, |
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3), |
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VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2, |
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vmstate_pit_channel, PITChannelState), |
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VMSTATE_TIMER(channels[0].irq_timer, PITCommonState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void pit_common_class_init(ObjectClass *klass, void *data) |
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{ |
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ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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ic->init = pit_init_common; |
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dc->vmsd = &vmstate_pit_common; |
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dc->no_user = 1; |
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} |
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static TypeInfo pit_common_type = { |
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.name = TYPE_PIT_COMMON, |
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.parent = TYPE_ISA_DEVICE, |
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.instance_size = sizeof(PITCommonState), |
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.class_size = sizeof(PITCommonClass), |
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.class_init = pit_common_class_init, |
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.abstract = true, |
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}; |
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static void register_devices(void) |
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{ |
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type_register_static(&pit_common_type); |
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} |
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type_init(register_devices); |
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@ -0,0 +1,85 @@ |
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/*
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* QEMU 8253/8254 - internal interfaces |
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* |
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* Copyright (c) 2011 Jan Kiszka, Siemens AG |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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#ifndef QEMU_I8254_INTERNAL_H |
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#define QEMU_I8254_INTERNAL_H |
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#include "hw.h" |
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#include "pc.h" |
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#include "isa.h" |
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typedef struct PITChannelState { |
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int count; /* can be 65536 */ |
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uint16_t latched_count; |
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uint8_t count_latched; |
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uint8_t status_latched; |
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uint8_t status; |
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uint8_t read_state; |
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uint8_t write_state; |
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uint8_t write_latch; |
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uint8_t rw_mode; |
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uint8_t mode; |
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uint8_t bcd; /* not supported */ |
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uint8_t gate; /* timer start */ |
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int64_t count_load_time; |
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/* irq handling */ |
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int64_t next_transition_time; |
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QEMUTimer *irq_timer; |
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qemu_irq irq; |
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uint32_t irq_disabled; |
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} PITChannelState; |
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typedef struct PITCommonState { |
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ISADevice dev; |
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MemoryRegion ioports; |
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uint32_t iobase; |
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PITChannelState channels[3]; |
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} PITCommonState; |
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#define TYPE_PIT_COMMON "pit-common" |
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#define PIT_COMMON(obj) \ |
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OBJECT_CHECK(PITCommonState, (obj), TYPE_PIT_COMMON) |
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#define PIT_COMMON_CLASS(klass) \ |
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OBJECT_CLASS_CHECK(PITCommonClass, (klass), TYPE_PIT_COMMON) |
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#define PIT_COMMON_GET_CLASS(obj) \ |
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OBJECT_GET_CLASS(PITCommonClass, (obj), TYPE_PIT_COMMON) |
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typedef struct PITCommonClass { |
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ISADeviceClass parent_class; |
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int (*init)(PITCommonState *s); |
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void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val); |
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void (*get_channel_info)(PITCommonState *s, PITChannelState *sc, |
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PITChannelInfo *info); |
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void (*pre_save)(PITCommonState *s); |
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void (*post_load)(PITCommonState *s); |
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} PITCommonClass; |
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int pit_get_out(PITChannelState *s, int64_t current_time); |
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int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time); |
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void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc, |
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PITChannelInfo *info); |
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void pit_reset_common(PITCommonState *s); |
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#endif /* !QEMU_I8254_INTERNAL_H */ |
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