Browse Source
intel_iommu:
SVM support
vhost:
support for indirect descriptors in shadow virtqueue
vhost-user:
vhost-user-spi support
vhost-user-blk inflight migration support
vhost-user-blk inflight migration support
misc fixes in pci, vhost, virtio, acpi, cxl
cleanups in acpi/ghes
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pci,pc: features, fixes
intel_iommu:
SVM support
vhost:
support for indirect descriptors in shadow virtqueue
vhost-user:
vhost-user-spi support
vhost-user-blk inflight migration support
vhost-user-blk inflight migration support
misc fixes in pci, vhost, virtio, acpi, cxl
cleanups in acpi/ghes
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# gpg: Signature made Thu Feb 5 10:07:12 2026 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
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# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
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# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (38 commits)
hw/cxl: Take into account how many media operations are requested for param check
hw/cxl: Check for overflow on santize media as both base and offset 64bit.
vhost-user-blk: support inter-host inflight migration
vhost: add vmstate for inflight region with inner buffer
vmstate: introduce VMSTATE_VBUFFER_UINT64
vhost-user: introduce protocol feature for skip drain on GET_VRING_BASE
vhost-user.rst: specify vhost-user back-end action on GET_VRING_BASE
virtio-gpu: use consistent error checking for virtio_gpu_create_mapping_iov
virtio-gpu: fix error handling in virgl_cmd_resource_create_blob
virtio-pmem: ignore empty queue notifications
virtio-gpu-virgl: correct parent for blob memory region
MAINTAINERS: Update VIOT maintainer
cryptodev-builtin: Limit the maximum size
hw/virtio/virtio-crypto: verify asym request size
virtio-spi: Add vhost-user-spi device support
standard-headers: Update virtio_spi.h from Linux v6.18-rc3
q35: Fix migration of SMRAM state
pcie_sriov: Fix PCI_SRIOV_* accesses in pcie_sriov_pf_exit()
virtio: Fix crash when sriov-pf is set for non-PCI-Express device
virtio-dmabuf: Ensure UUID persistence for hash table insertion
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
pull/319/head
Peter Maydell
2 months ago
57 changed files with 791 additions and 208 deletions
@ -0,0 +1,69 @@ |
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/*
|
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* Vhost-user spi virtio device PCI glue |
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* |
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* Copyright (C) 2025 Qualcomm Innovation Center, Inc. All Rights Reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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|
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#include "qemu/osdep.h" |
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#include "hw/core/qdev-properties.h" |
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#include "hw/virtio/vhost-user-spi.h" |
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#include "hw/virtio/virtio-pci.h" |
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|
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struct VHostUserSPIPCI { |
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VirtIOPCIProxy parent_obj; |
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VHostUserSPI vdev; |
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}; |
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|
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typedef struct VHostUserSPIPCI VHostUserSPIPCI; |
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|
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#define TYPE_VHOST_USER_SPI_PCI "vhost-user-spi-pci-base" |
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|
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DECLARE_INSTANCE_CHECKER(VHostUserSPIPCI, VHOST_USER_SPI_PCI, |
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TYPE_VHOST_USER_SPI_PCI) |
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|
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static void vhost_user_spi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) |
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{ |
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VHostUserSPIPCI *dev = VHOST_USER_SPI_PCI(vpci_dev); |
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DeviceState *vdev = DEVICE(&dev->vdev); |
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|
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vpci_dev->nvectors = 1; |
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qdev_realize(vdev, BUS(&vpci_dev->bus), errp); |
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} |
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|
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static void vhost_user_spi_pci_class_init(ObjectClass *klass, const void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); |
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PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); |
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k->realize = vhost_user_spi_pci_realize; |
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
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pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; |
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pcidev_k->device_id = 0; /* Set by virtio-pci based on virtio id */ |
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pcidev_k->revision = 0x00; |
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pcidev_k->class_id = PCI_CLASS_COMMUNICATION_OTHER; |
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} |
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|
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static void vhost_user_spi_pci_instance_init(Object *obj) |
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{ |
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VHostUserSPIPCI *dev = VHOST_USER_SPI_PCI(obj); |
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|
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virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev), |
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TYPE_VHOST_USER_SPI); |
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} |
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|
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static const VirtioPCIDeviceTypeInfo vhost_user_spi_pci_info = { |
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.base_name = TYPE_VHOST_USER_SPI_PCI, |
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.non_transitional_name = "vhost-user-spi-pci", |
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.instance_size = sizeof(VHostUserSPIPCI), |
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.instance_init = vhost_user_spi_pci_instance_init, |
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.class_init = vhost_user_spi_pci_class_init, |
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}; |
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|
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static void vhost_user_spi_pci_register(void) |
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{ |
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virtio_pci_types_register(&vhost_user_spi_pci_info); |
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} |
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|
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type_init(vhost_user_spi_pci_register); |
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@ -0,0 +1,65 @@ |
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/*
|
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* Vhost-user spi virtio device |
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* |
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* Copyright (C) 2025 Qualcomm Innovation Center, Inc. All Rights Reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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|
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#include "qemu/osdep.h" |
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#include "qapi/error.h" |
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#include "hw/core/qdev-properties.h" |
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#include "hw/virtio/virtio-bus.h" |
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#include "hw/virtio/vhost-user-spi.h" |
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#include "qemu/error-report.h" |
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#include "standard-headers/linux/virtio_ids.h" |
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#include "standard-headers/linux/virtio_spi.h" |
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|
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static const Property vspi_properties[] = { |
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DEFINE_PROP_CHR("chardev", VHostUserBase, chardev), |
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}; |
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|
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static void vspi_realize(DeviceState *dev, Error **errp) |
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{ |
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VHostUserBase *vub = VHOST_USER_BASE(dev); |
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VHostUserBaseClass *vubc = VHOST_USER_BASE_GET_CLASS(dev); |
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|
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/* Fixed for SPI */ |
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vub->virtio_id = VIRTIO_ID_SPI; |
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vub->num_vqs = 1; |
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vub->vq_size = 4; |
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vub->config_size = sizeof(struct virtio_spi_config); |
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|
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vubc->parent_realize(dev, errp); |
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} |
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|
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static const VMStateDescription vu_spi_vmstate = { |
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.name = "vhost-user-spi", |
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.unmigratable = 1, |
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}; |
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|
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static void vu_spi_class_init(ObjectClass *klass, const void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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VHostUserBaseClass *vubc = VHOST_USER_BASE_CLASS(klass); |
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|
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dc->vmsd = &vu_spi_vmstate; |
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device_class_set_props(dc, vspi_properties); |
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device_class_set_parent_realize(dc, vspi_realize, |
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&vubc->parent_realize); |
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
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} |
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|
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static const TypeInfo vu_spi_info = { |
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.name = TYPE_VHOST_USER_SPI, |
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.parent = TYPE_VHOST_USER_BASE, |
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.instance_size = sizeof(VHostUserSPI), |
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.class_init = vu_spi_class_init, |
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}; |
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|
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static void vu_spi_register_types(void) |
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{ |
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type_register_static(&vu_spi_info); |
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} |
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|
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type_init(vu_spi_register_types) |
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@ -0,0 +1,25 @@ |
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/*
|
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* Vhost-user spi virtio device |
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* |
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* Copyright (C) 2025 Qualcomm Innovation Center, Inc. All Rights Reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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|
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#ifndef QEMU_VHOST_USER_SPI_H |
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#define QEMU_VHOST_USER_SPI_H |
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|
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#include "hw/virtio/virtio.h" |
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#include "hw/virtio/vhost.h" |
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#include "hw/virtio/vhost-user.h" |
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#include "hw/virtio/vhost-user-base.h" |
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|
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#define TYPE_VHOST_USER_SPI "vhost-user-spi-device" |
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OBJECT_DECLARE_SIMPLE_TYPE(VHostUserSPI, VHOST_USER_SPI) |
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|
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struct VHostUserSPI { |
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VHostUserBase parent_obj; |
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}; |
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|
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#endif /* QEMU_VHOST_USER_SPI_H */ |
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@ -0,0 +1,181 @@ |
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/* SPDX-License-Identifier: BSD-3-Clause */ |
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/*
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* Copyright (C) 2023 OpenSynergy GmbH |
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* Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. |
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*/ |
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#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H |
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#define _LINUX_VIRTIO_VIRTIO_SPI_H |
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#include "standard-headers/linux/types.h" |
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#include "standard-headers/linux/virtio_config.h" |
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#include "standard-headers/linux/virtio_ids.h" |
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#include "standard-headers/linux/virtio_types.h" |
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|
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/* Sample data on trailing clock edge */ |
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#define VIRTIO_SPI_CPHA _BITUL(0) |
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/* Clock is high when IDLE */ |
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#define VIRTIO_SPI_CPOL _BITUL(1) |
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/* Chip Select is active high */ |
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#define VIRTIO_SPI_CS_HIGH _BITUL(2) |
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/* Transmit LSB first */ |
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#define VIRTIO_SPI_MODE_LSB_FIRST _BITUL(3) |
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/* Loopback mode */ |
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#define VIRTIO_SPI_MODE_LOOP _BITUL(4) |
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|
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/**
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* struct virtio_spi_config - All config fields are read-only for the |
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* Virtio SPI driver |
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* @cs_max_number: maximum number of chipselect the host SPI controller |
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* supports. |
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* @cs_change_supported: indicates if the host SPI controller supports to toggle |
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* chipselect after each transfer in one message: |
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* 0: unsupported, chipselect will be kept in active state throughout the |
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* message transaction; |
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* 1: supported. |
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* Note: Message here contains a sequence of SPI transfers. |
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* @tx_nbits_supported: indicates the supported number of bit for writing: |
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* bit 0: DUAL (2-bit transfer), 1 for supported |
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* bit 1: QUAD (4-bit transfer), 1 for supported |
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* bit 2: OCTAL (8-bit transfer), 1 for supported |
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* other bits are reserved as 0, 1-bit transfer is always supported. |
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* @rx_nbits_supported: indicates the supported number of bit for reading: |
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* bit 0: DUAL (2-bit transfer), 1 for supported |
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* bit 1: QUAD (4-bit transfer), 1 for supported |
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* bit 2: OCTAL (8-bit transfer), 1 for supported |
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* other bits are reserved as 0, 1-bit transfer is always supported. |
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* @bits_per_word_mask: mask indicating which values of bits_per_word are |
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* supported. If not set, no limitation for bits_per_word. |
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* @mode_func_supported: indicates the following features are supported or not: |
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* bit 0-1: CPHA feature |
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* 0b00: invalid, should support as least one CPHA setting |
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* 0b01: supports CPHA=0 only |
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* 0b10: supports CPHA=1 only |
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* 0b11: supports CPHA=0 and CPHA=1. |
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* bit 2-3: CPOL feature |
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* 0b00: invalid, should support as least one CPOL setting |
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* 0b01: supports CPOL=0 only |
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* 0b10: supports CPOL=1 only |
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* 0b11: supports CPOL=0 and CPOL=1. |
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* bit 4: chipselect active high feature, 0 for unsupported and 1 for |
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* supported, chipselect active low is supported by default. |
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* bit 5: LSB first feature, 0 for unsupported and 1 for supported, |
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* MSB first is supported by default. |
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* bit 6: loopback mode feature, 0 for unsupported and 1 for supported, |
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* normal mode is supported by default. |
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* @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no |
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* limitation for transfer speed. |
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* @max_word_delay_ns: the maximum word delay supported, in nanoseconds. |
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* A value of 0 indicates that word delay is unsupported. |
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* Each transfer may consist of a sequence of words. |
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* @max_cs_setup_ns: the maximum delay supported after chipselect is asserted, |
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* in ns unit, 0 means delay is not supported to introduce after chipselect is |
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* asserted. |
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* @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted, |
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* in ns unit, 0 means delay is not supported to introduce before chipselect |
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* is deasserted. |
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* @max_cs_incative_ns: maximum delay supported after chipselect is deasserted, |
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* in ns unit, 0 means delay is not supported to introduce after chipselect is |
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* deasserted. |
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*/ |
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struct virtio_spi_config { |
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uint8_t cs_max_number; |
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uint8_t cs_change_supported; |
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#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL _BITUL(0) |
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#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD _BITUL(1) |
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#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL _BITUL(2) |
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uint8_t tx_nbits_supported; |
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uint8_t rx_nbits_supported; |
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uint32_t bits_per_word_mask; |
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#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 _BITUL(0) |
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#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 _BITUL(1) |
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#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 _BITUL(2) |
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#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 _BITUL(3) |
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#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH _BITUL(4) |
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#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST _BITUL(5) |
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#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK _BITUL(6) |
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uint32_t mode_func_supported; |
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uint32_t max_freq_hz; |
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uint32_t max_word_delay_ns; |
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uint32_t max_cs_setup_ns; |
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uint32_t max_cs_hold_ns; |
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uint32_t max_cs_inactive_ns; |
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}; |
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|
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/**
|
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* struct spi_transfer_head - virtio SPI transfer descriptor |
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* @chip_select_id: chipselect index the SPI transfer used. |
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* @bits_per_word: the number of bits in each SPI transfer word. |
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* @cs_change: whether to deselect device after finishing this transfer |
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* before starting the next transfer, 0 means cs keep asserted and |
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* 1 means cs deasserted then asserted again. |
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* @tx_nbits: bus width for write transfer. |
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* 0,1: bus width is 1, also known as SINGLE |
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* 2 : bus width is 2, also known as DUAL |
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* 4 : bus width is 4, also known as QUAD |
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* 8 : bus width is 8, also known as OCTAL |
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* other values are invalid. |
|||
* @rx_nbits: bus width for read transfer. |
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* 0,1: bus width is 1, also known as SINGLE |
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* 2 : bus width is 2, also known as DUAL |
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* 4 : bus width is 4, also known as QUAD |
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* 8 : bus width is 8, also known as OCTAL |
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* other values are invalid. |
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* @reserved: for future use. |
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* @mode: SPI transfer mode. |
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* bit 0: CPHA, determines the timing (i.e. phase) of the data |
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* bits relative to the clock pulses.For CPHA=0, the |
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* "out" side changes the data on the trailing edge of the |
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* preceding clock cycle, while the "in" side captures the data |
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* on (or shortly after) the leading edge of the clock cycle. |
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* For CPHA=1, the "out" side changes the data on the leading |
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* edge of the current clock cycle, while the "in" side |
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* captures the data on (or shortly after) the trailing edge of |
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* the clock cycle. |
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* bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a |
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* clock which idles at 0, and each cycle consists of a pulse |
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* of 1. CPOL=1 is a clock which idles at 1, and each cycle |
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* consists of a pulse of 0. |
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* bit 2: CS_HIGH, if 1, chip select active high, else active low. |
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* bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB |
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* first, else LSB first. |
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* bit 4: LOOP, loopback mode. |
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* @freq: the transfer speed in Hz. |
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* @word_delay_ns: delay to be inserted between consecutive words of a |
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* transfer, in ns unit. |
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* @cs_setup_ns: delay to be introduced after CS is asserted, in ns |
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* unit. |
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* @cs_delay_hold_ns: delay to be introduced before CS is deasserted |
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* for each transfer, in ns unit. |
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* @cs_change_delay_inactive_ns: delay to be introduced after CS is |
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* deasserted and before next asserted, in ns unit. |
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*/ |
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struct spi_transfer_head { |
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uint8_t chip_select_id; |
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uint8_t bits_per_word; |
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uint8_t cs_change; |
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uint8_t tx_nbits; |
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uint8_t rx_nbits; |
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uint8_t reserved[3]; |
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uint32_t mode; |
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uint32_t freq; |
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uint32_t word_delay_ns; |
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uint32_t cs_setup_ns; |
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uint32_t cs_delay_hold_ns; |
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uint32_t cs_change_delay_inactive_ns; |
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}; |
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|
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/**
|
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* struct spi_transfer_result - virtio SPI transfer result |
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* @result: Transfer result code. |
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* VIRTIO_SPI_TRANS_OK: Transfer successful. |
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* VIRTIO_SPI_PARAM_ERR: Parameter error. |
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* VIRTIO_SPI_TRANS_ERR: Transfer error. |
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*/ |
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struct spi_transfer_result { |
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#define VIRTIO_SPI_TRANS_OK 0 |
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#define VIRTIO_SPI_PARAM_ERR 1 |
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#define VIRTIO_SPI_TRANS_ERR 2 |
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uint8_t result; |
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}; |
|||
|
|||
#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */ |
|||
Loading…
Reference in new issue