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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3269 c046a42c-6fe2-441c-8c8c-71466251a162stable-0.10
ths
19 years ago
6 changed files with 336 additions and 196 deletions
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/*
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* SuperH Timer modules. |
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* |
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* Copyright (c) 2007 Magnus Damm |
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* Based on arm_timer.c by Paul Brook |
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* Copyright (c) 2005-2006 CodeSourcery. |
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* |
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* This code is licenced under the GPL. |
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*/ |
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#include "vl.h" |
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//#define DEBUG_TIMER
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#define TIMER_TCR_TPSC (7 << 0) |
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#define TIMER_TCR_CKEG (3 << 3) |
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#define TIMER_TCR_UNIE (1 << 5) |
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#define TIMER_TCR_ICPE (3 << 6) |
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#define TIMER_TCR_UNF (1 << 8) |
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#define TIMER_TCR_ICPF (1 << 9) |
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#define TIMER_TCR_RESERVED (0x3f << 10) |
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#define TIMER_FEAT_CAPT (1 << 0) |
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#define TIMER_FEAT_EXTCLK (1 << 1) |
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typedef struct { |
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ptimer_state *timer; |
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uint32_t tcnt; |
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uint32_t tcor; |
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uint32_t tcr; |
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uint32_t tcpr; |
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int freq; |
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int int_level; |
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int feat; |
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int enabled; |
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qemu_irq irq; |
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} sh_timer_state; |
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/* Check all active timers, and schedule the next timer interrupt. */ |
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static void sh_timer_update(sh_timer_state *s) |
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{ |
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#if 0 /* not yet */
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/* Update interrupts. */ |
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if (s->int_level && (s->tcr & TIMER_TCR_UNIE)) { |
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qemu_irq_raise(s->irq); |
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} else { |
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qemu_irq_lower(s->irq); |
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} |
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#endif |
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} |
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uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) |
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{ |
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sh_timer_state *s = (sh_timer_state *)opaque; |
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switch (offset >> 2) { |
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case 0: |
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return s->tcor; |
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case 1: |
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return ptimer_get_count(s->timer); |
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case 2: |
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return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); |
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case 3: |
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if (s->feat & TIMER_FEAT_CAPT) |
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return s->tcpr; |
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default: |
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cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n", |
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(int)offset); |
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return 0; |
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} |
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} |
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static void sh_timer_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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sh_timer_state *s = (sh_timer_state *)opaque; |
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int freq; |
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switch (offset >> 2) { |
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case 0: |
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s->tcor = value; |
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ptimer_set_limit(s->timer, s->tcor, 0); |
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break; |
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case 1: |
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s->tcnt = value; |
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ptimer_set_count(s->timer, s->tcnt); |
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break; |
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case 2: |
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if (s->enabled) { |
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/* Pause the timer if it is running. This may cause some
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inaccuracy dure to rounding, but avoids a whole lot of other |
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messyness. */ |
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ptimer_stop(s->timer); |
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} |
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freq = s->freq; |
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/* ??? Need to recalculate expiry time after changing divisor. */ |
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switch (value & TIMER_TCR_TPSC) { |
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case 0: freq >>= 2; break; |
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case 1: freq >>= 4; break; |
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case 2: freq >>= 6; break; |
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case 3: freq >>= 8; break; |
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case 4: freq >>= 10; break; |
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case 6: |
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case 7: if (s->feat & TIMER_FEAT_EXTCLK) break; |
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default: cpu_abort (cpu_single_env, |
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"sh_timer_write: Reserved TPSC value\n"); break; |
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} |
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switch ((value & TIMER_TCR_CKEG) >> 3) { |
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case 0: break; |
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case 1: |
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case 2: |
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case 3: if (s->feat & TIMER_FEAT_EXTCLK) break; |
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default: cpu_abort (cpu_single_env, |
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"sh_timer_write: Reserved CKEG value\n"); break; |
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} |
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switch ((value & TIMER_TCR_ICPE) >> 6) { |
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case 0: break; |
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case 2: |
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case 3: if (s->feat & TIMER_FEAT_CAPT) break; |
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default: cpu_abort (cpu_single_env, |
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"sh_timer_write: Reserved ICPE value\n"); break; |
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} |
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if ((value & TIMER_TCR_UNF) == 0) |
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s->int_level = 0; |
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value &= ~TIMER_TCR_UNF; |
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) |
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cpu_abort (cpu_single_env, |
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"sh_timer_write: Reserved ICPF value\n"); |
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value &= ~TIMER_TCR_ICPF; /* capture not supported */ |
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if (value & TIMER_TCR_RESERVED) |
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cpu_abort (cpu_single_env, |
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"sh_timer_write: Reserved TCR bits set\n"); |
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s->tcr = value; |
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ptimer_set_limit(s->timer, s->tcor, 0); |
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ptimer_set_freq(s->timer, freq); |
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if (s->enabled) { |
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/* Restart the timer if still enabled. */ |
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ptimer_run(s->timer, 0); |
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} |
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break; |
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case 3: |
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if (s->feat & TIMER_FEAT_CAPT) { |
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s->tcpr = value; |
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break; |
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} |
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default: |
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cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n", |
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(int)offset); |
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} |
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sh_timer_update(s); |
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} |
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static void sh_timer_start_stop(void *opaque, int enable) |
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{ |
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sh_timer_state *s = (sh_timer_state *)opaque; |
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#ifdef DEBUG_TIMER |
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printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); |
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#endif |
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if (s->enabled && !enable) { |
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ptimer_stop(s->timer); |
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} |
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if (!s->enabled && enable) { |
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ptimer_run(s->timer, 0); |
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} |
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s->enabled = !!enable; |
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#ifdef DEBUG_TIMER |
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printf("sh_timer_start_stop done %d\n", s->enabled); |
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#endif |
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} |
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static void sh_timer_tick(void *opaque) |
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{ |
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sh_timer_state *s = (sh_timer_state *)opaque; |
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s->int_level = s->enabled; |
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sh_timer_update(s); |
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} |
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static void *sh_timer_init(uint32_t freq, int feat) |
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{ |
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sh_timer_state *s; |
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QEMUBH *bh; |
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s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state)); |
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s->freq = freq; |
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s->feat = feat; |
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s->tcor = 0xffffffff; |
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s->tcnt = 0xffffffff; |
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s->tcpr = 0xdeadbeef; |
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s->tcor = 0; |
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s->enabled = 0; |
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bh = qemu_bh_new(sh_timer_tick, s); |
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s->timer = ptimer_init(bh); |
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/* ??? Save/restore. */ |
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return s; |
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} |
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typedef struct { |
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void *timer[3]; |
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int level[3]; |
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uint32_t tocr; |
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uint32_t tstr; |
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target_phys_addr_t base; |
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int feat; |
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} tmu012_state; |
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static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) |
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{ |
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tmu012_state *s = (tmu012_state *)opaque; |
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#ifdef DEBUG_TIMER |
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printf("tmu012_read 0x%lx\n", (unsigned long) offset); |
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#endif |
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offset -= s->base; |
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if (offset >= 0x20) { |
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if (!(s->feat & TMU012_FEAT_3CHAN)) |
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cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n", |
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(int)offset); |
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return sh_timer_read(s->timer[2], offset - 0x20); |
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} |
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if (offset >= 0x14) |
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return sh_timer_read(s->timer[1], offset - 0x14); |
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if (offset >= 0x08) |
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return sh_timer_read(s->timer[0], offset - 0x08); |
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if (offset == 4) |
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return s->tstr; |
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if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) |
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return s->tocr; |
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cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n", |
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(int)offset); |
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return 0; |
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} |
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static void tmu012_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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tmu012_state *s = (tmu012_state *)opaque; |
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#ifdef DEBUG_TIMER |
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printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
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#endif |
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offset -= s->base; |
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if (offset >= 0x20) { |
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if (!(s->feat & TMU012_FEAT_3CHAN)) |
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cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n", |
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(int)offset); |
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sh_timer_write(s->timer[2], offset - 0x20, value); |
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return; |
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} |
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if (offset >= 0x14) { |
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sh_timer_write(s->timer[1], offset - 0x14, value); |
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return; |
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} |
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if (offset >= 0x08) { |
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sh_timer_write(s->timer[0], offset - 0x08, value); |
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return; |
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} |
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if (offset == 4) { |
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sh_timer_start_stop(s->timer[0], value & (1 << 0)); |
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sh_timer_start_stop(s->timer[1], value & (1 << 1)); |
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if (s->feat & TMU012_FEAT_3CHAN) |
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sh_timer_start_stop(s->timer[2], value & (1 << 2)); |
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else |
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if (value & (1 << 2)) |
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cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n"); |
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s->tstr = value; |
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return; |
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} |
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if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { |
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s->tocr = value & (1 << 0); |
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} |
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} |
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static CPUReadMemoryFunc *tmu012_readfn[] = { |
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tmu012_read, |
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tmu012_read, |
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tmu012_read |
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}; |
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static CPUWriteMemoryFunc *tmu012_writefn[] = { |
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tmu012_write, |
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tmu012_write, |
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tmu012_write |
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}; |
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void tmu012_init(uint32_t base, int feat, uint32_t freq) |
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{ |
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int iomemtype; |
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tmu012_state *s; |
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int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; |
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s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state)); |
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s->base = base; |
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s->feat = feat; |
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s->timer[0] = sh_timer_init(freq, timer_feat); |
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s->timer[1] = sh_timer_init(freq, timer_feat); |
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if (feat & TMU012_FEAT_3CHAN) |
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s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT); |
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iomemtype = cpu_register_io_memory(0, tmu012_readfn, |
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tmu012_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype); |
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/* ??? Save/restore. */ |
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} |
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