riscv
/
qemu
mirror of https://gitea.goldendeliverer.com/riscv/qemu.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

Add {l,st}ve{b,h,w}x instructions. 

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
stable-0.10
aurel32 18 years ago
parent
bcd2ee23ea
commit
cbfb6ae9b3
3 changed files with 90 additions and 0 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 6
      target-ppc/helper.h
  2. 40
      target-ppc/op_helper.c
  3. 44
      target-ppc/translate.c

6
target-ppc/helper.h
View File

@ -185,6 +185,12 @@ DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
DEF_HELPER_2(lvebx, void, avr, tl)
DEF_HELPER_2(lvehx, void, avr, tl)
DEF_HELPER_2(lvewx, void, avr, tl)
DEF_HELPER_2(stvebx, void, avr, tl)
DEF_HELPER_2(stvehx, void, avr, tl)
DEF_HELPER_2(stvewx, void, avr, tl)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)

40
target-ppc/op_helper.c
View File

@ -1999,6 +1999,26 @@ SATCVT(sw, uh, int32_t, uint16_t, 0, UINT16_MAX, 1, 1)
SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1)
#undef SATCVT
#define LVE(name, access, swap, element) \
void helper_##name (ppc_avr_t *r, target_ulong addr) \
{ \
size_t n_elems = ARRAY_SIZE(r->element); \
int adjust = HI_IDX*(n_elems-1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
if(msr_le) { \
r->element[LO_IDX ? index : (adjust - index)] = swap(access(addr)); \
} else { \
r->element[LO_IDX ? index : (adjust - index)] = access(addr); \
} \
}
#define I(x) (x)
LVE(lvebx, ldub, I, u8)
LVE(lvehx, lduw, bswap16, u16)
LVE(lvewx, ldl, bswap32, u32)
#undef I
#undef LVE
void helper_lvsl (ppc_avr_t *r, target_ulong sh)
{
int i, j = (sh & 0xf);
@ -2017,6 +2037,26 @@ void helper_lvsr (ppc_avr_t *r, target_ulong sh)
}
}
#define STVE(name, access, swap, element) \
void helper_##name (ppc_avr_t *r, target_ulong addr) \
{ \
size_t n_elems = ARRAY_SIZE(r->element); \
int adjust = HI_IDX*(n_elems-1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
if(msr_le) { \
access(addr, swap(r->element[LO_IDX ? index : (adjust - index)])); \
} else { \
access(addr, r->element[LO_IDX ? index : (adjust - index)]); \
} \
}
#define I(x) (x)
STVE(stvebx, stb, I, u8)
STVE(stvehx, stw, bswap16, u16)
STVE(stvewx, stl, bswap32, u32)
#undef I
#undef LVE
void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;

44
target-ppc/translate.c
View File

@ -6144,14 +6144,58 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
tcg_temp_free(EA); \
}
#define GEN_VR_LVE(name, opc2, opc3) \
GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
{ \
TCGv EA; \
TCGv_ptr rs; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_lve##name (rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
#define GEN_VR_STVE(name, opc2, opc3) \
GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
{ \
TCGv EA; \
TCGv_ptr rs; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_stve##name (rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
GEN_VR_LVE(bx, 0x07, 0x00);
GEN_VR_LVE(hx, 0x07, 0x01);
GEN_VR_LVE(wx, 0x07, 0x02);
GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
GEN_VR_STVE(bx, 0x07, 0x04);
GEN_VR_STVE(hx, 0x07, 0x05);
GEN_VR_STVE(wx, 0x07, 0x06);
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
{
TCGv_ptr rd;

Write Preview
Loading…
Cancel
Save