Browse Source

hw/nvme: Validate PMR memory size

Per the PCI spec 3.0, in section 6.2.5.1, "Address Maps":

  A 32-bit register can be implemented to support a single
  memory size that is a power of 2 from 16 bytes to 2 GB.

Add a check in nvme_init_pmr(), returning an error if the
PMR region size is too small; and update the QTest.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
pull/312/head
Philippe Mathieu-Daudé 4 months ago
committed by Klaus Jensen
parent
commit
bd3ba0d342
  1. 13
      hw/nvme/ctrl.c
  2. 2
      tests/qtest/nvme-test.c

13
hw/nvme/ctrl.c

@ -8814,10 +8814,15 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
}
}
static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
static bool nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
{
uint32_t pmrcap = ldl_le_p(&n->bar.pmrcap);
if (memory_region_size(&n->pmr.dev->mr) < 16) {
error_setg(errp, "PMR device must have at least 16 bytes");
return false;
}
NVME_PMRCAP_SET_RDS(pmrcap, 1);
NVME_PMRCAP_SET_WDS(pmrcap, 1);
NVME_PMRCAP_SET_BIR(pmrcap, NVME_PMR_BIR);
@ -8832,6 +8837,8 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr);
memory_region_set_enabled(&n->pmr.dev->mr, false);
return true;
}
static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs,
@ -9050,7 +9057,9 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
}
if (n->pmr.dev) {
nvme_init_pmr(n, pci_dev);
if (!nvme_init_pmr(n, pci_dev, errp)) {
return false;
}
}
return true;

2
tests/qtest/nvme-test.c

@ -149,7 +149,7 @@ static void nvme_register_nodes(void)
.before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
"file.read-zeroes=on,format=raw "
"-object memory-backend-ram,id=pmr0,"
"share=on,size=8",
"share=on,size=16",
};
add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });

Loading…
Cancel
Save