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@ -57,6 +57,30 @@ extern "C" { |
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* may preserve meaning - such as number of planes - from the fourcc code, |
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* whereas others may not. |
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* |
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* Modifiers must uniquely encode buffer layout. In other words, a buffer must |
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* match only a single modifier. A modifier must not be a subset of layouts of |
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* another modifier. For instance, it's incorrect to encode pitch alignment in |
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* a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel |
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* aligned modifier. That said, modifiers can have implicit minimal |
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* requirements. |
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* |
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* For modifiers where the combination of fourcc code and modifier can alias, |
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* a canonical pair needs to be defined and used by all drivers. Preferred |
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* combinations are also encouraged where all combinations might lead to |
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* confusion and unnecessarily reduced interoperability. An example for the |
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* latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. |
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* |
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* There are two kinds of modifier users: |
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* |
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* - Kernel and user-space drivers: for drivers it's important that modifiers |
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* don't alias, otherwise two drivers might support the same format but use |
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* different aliases, preventing them from sharing buffers in an efficient |
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* format. |
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* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users |
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* see modifiers as opaque tokens they can check for equality and intersect. |
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* These users musn't need to know to reason about the modifier value |
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* (i.e. they are not expected to extract information out of the modifier). |
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* |
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* Vendors should document their modifier usage in as much detail as |
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* possible, to ensure maximum compatibility across devices, drivers and |
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* applications. |
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@ -154,6 +178,12 @@ extern "C" { |
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#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ |
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#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ |
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/*
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* RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits |
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* of unused padding per component: |
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*/ |
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#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ |
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/* packed YCbCr */ |
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#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ |
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#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ |
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@ -319,7 +349,6 @@ extern "C" { |
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*/ |
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/* Vendor Ids: */ |
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#define DRM_FORMAT_MOD_NONE 0 |
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#define DRM_FORMAT_MOD_VENDOR_NONE 0 |
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 |
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@ -391,6 +420,16 @@ extern "C" { |
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*/ |
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) |
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/*
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* Deprecated: use DRM_FORMAT_MOD_LINEAR instead |
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* |
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* The "none" format modifier doesn't actually mean that the modifier is |
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* implicit, instead it means that the layout is linear. Whether modifiers are |
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* used is out-of-band information carried in an API-specific way (e.g. in a |
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* flag for drm_mode_fb_cmd2). |
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*/ |
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#define DRM_FORMAT_MOD_NONE 0 |
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/* Intel framebuffer modifiers */ |
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/*
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@ -1055,6 +1094,140 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) |
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*/ |
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#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) |
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/*
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* AMD modifiers |
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* |
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* Memory layout: |
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* |
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* without DCC: |
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* - main surface |
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* |
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* with DCC & without DCC_RETILE: |
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* - main surface in plane 0 |
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* - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) |
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* |
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* with DCC & DCC_RETILE: |
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* - main surface in plane 0 |
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* - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) |
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* - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) |
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* |
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* For multi-plane formats the above surfaces get merged into one plane for |
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* each format plane, based on the required alignment only. |
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* |
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* Bits Parameter Notes |
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* ----- ------------------------ --------------------------------------------- |
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* |
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* 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* |
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* 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* |
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* 13 DCC |
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* 14 DCC_RETILE |
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* 15 DCC_PIPE_ALIGN |
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* 16 DCC_INDEPENDENT_64B |
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* 17 DCC_INDEPENDENT_128B |
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* 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* |
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* 20 DCC_CONSTANT_ENCODE |
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* 23:21 PIPE_XOR_BITS Only for some chips |
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* 26:24 BANK_XOR_BITS Only for some chips |
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* 29:27 PACKERS Only for some chips |
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* 32:30 RB Only for some chips |
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* 35:33 PIPE Only for some chips |
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* 55:36 - Reserved for future use, must be zero |
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*/ |
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#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) |
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#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) |
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/* Reserve 0 for GFX8 and older */ |
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#define AMD_FMT_MOD_TILE_VER_GFX9 1 |
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#define AMD_FMT_MOD_TILE_VER_GFX10 2 |
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#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 |
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/*
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* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical |
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* version. |
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*/ |
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#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 |
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/*
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* 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has |
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* GFX9 as canonical version. |
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*/ |
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 |
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 |
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#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 |
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 |
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#define AMD_FMT_MOD_DCC_BLOCK_64B 0 |
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#define AMD_FMT_MOD_DCC_BLOCK_128B 1 |
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#define AMD_FMT_MOD_DCC_BLOCK_256B 2 |
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#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 |
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#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF |
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#define AMD_FMT_MOD_TILE_SHIFT 8 |
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#define AMD_FMT_MOD_TILE_MASK 0x1F |
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/* Whether DCC compression is enabled. */ |
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#define AMD_FMT_MOD_DCC_SHIFT 13 |
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#define AMD_FMT_MOD_DCC_MASK 0x1 |
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/*
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* Whether to include two DCC surfaces, one which is rb & pipe aligned, and |
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* one which is not-aligned. |
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*/ |
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#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 |
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#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 |
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/* Only set if DCC_RETILE = false */ |
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 |
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 |
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 |
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 |
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 |
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 |
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 |
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 |
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/*
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* DCC supports embedding some clear colors directly in the DCC surface. |
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* However, on older GPUs the rendering HW ignores the embedded clear color |
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* and prefers the driver provided color. This necessitates doing a fastclear |
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* eliminate operation before a process transfers control. |
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* |
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* If this bit is set that means the fastclear eliminate is not needed for these |
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* embeddable colors. |
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*/ |
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#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 |
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#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 |
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/*
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* The below fields are for accounting for per GPU differences. These are only |
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* relevant for GFX9 and later and if the tile field is *_X/_T. |
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* |
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* PIPE_XOR_BITS = always needed |
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* BANK_XOR_BITS = only for TILE_VER_GFX9 |
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* PACKERS = only for TILE_VER_GFX10_RBPLUS |
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* RB = only for TILE_VER_GFX9 & DCC |
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* PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) |
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*/ |
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#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 |
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#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 |
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#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 |
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#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 |
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#define AMD_FMT_MOD_PACKERS_SHIFT 27 |
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#define AMD_FMT_MOD_PACKERS_MASK 0x7 |
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#define AMD_FMT_MOD_RB_SHIFT 30 |
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#define AMD_FMT_MOD_RB_MASK 0x7 |
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#define AMD_FMT_MOD_PIPE_SHIFT 33 |
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#define AMD_FMT_MOD_PIPE_MASK 0x7 |
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#define AMD_FMT_MOD_SET(field, value) \ |
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((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) |
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#define AMD_FMT_MOD_GET(field, value) \ |
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(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) |
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#define AMD_FMT_MOD_CLEAR(field) \ |
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(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) |
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#if defined(__cplusplus) |
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} |
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#endif |
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Eric Farman
6 years ago
Cornelia Huck