Browse Source
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4920 c046a42c-6fe2-441c-8c8c-71466251a162stable-0.10
balrog
18 years ago
7 changed files with 896 additions and 164 deletions
@ -0,0 +1,366 @@ |
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/*
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* On-chip DMA controller framework. |
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* |
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* Copyright (C) 2008 Nokia Corporation |
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* Written by Andrzej Zaborowski <andrew@openedhand.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 or |
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* (at your option) version 3 of the License. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include "qemu-common.h" |
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#include "qemu-timer.h" |
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#include "soc_dma.h" |
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void transfer_mem2mem(struct soc_dma_ch_s *ch) |
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{ |
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memcpy(ch->paddr[0], ch->paddr[1], ch->bytes); |
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ch->paddr[0] += ch->bytes; |
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ch->paddr[1] += ch->bytes; |
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} |
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void transfer_mem2fifo(struct soc_dma_ch_s *ch) |
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{ |
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ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes); |
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ch->paddr[0] += ch->bytes; |
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} |
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void transfer_fifo2mem(struct soc_dma_ch_s *ch) |
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{ |
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ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes); |
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ch->paddr[1] += ch->bytes; |
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} |
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/* This is further optimisable but isn't very important because often
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* DMA peripherals forbid this kind of transfers and even when they don't, |
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* oprating systems may not need to use them. */ |
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static void *fifo_buf; |
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static int fifo_size; |
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void transfer_fifo2fifo(struct soc_dma_ch_s *ch) |
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{ |
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if (ch->bytes < fifo_size) |
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fifo_buf = realloc(fifo_buf, fifo_size = ch->bytes); |
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/* Implement as transfer_fifo2linear + transfer_linear2fifo. */ |
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ch->io_fn[0](ch->io_opaque[0], fifo_buf, ch->bytes); |
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ch->io_fn[1](ch->io_opaque[1], fifo_buf, ch->bytes); |
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} |
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struct dma_s { |
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struct soc_dma_s soc; |
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int chnum; |
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uint64_t ch_enable_mask; |
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int64_t channel_freq; |
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int enabled_count; |
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struct memmap_entry_s { |
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enum soc_dma_port_type type; |
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target_phys_addr_t addr; |
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union { |
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struct { |
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void *opaque; |
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soc_dma_io_t fn; |
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int out; |
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} fifo; |
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struct { |
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void *base; |
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size_t size; |
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} mem; |
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} u; |
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} *memmap; |
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int memmap_size; |
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struct soc_dma_ch_s ch[0]; |
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}; |
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static void soc_dma_ch_schedule(struct soc_dma_ch_s *ch, int delay_bytes) |
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{ |
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int64_t now = qemu_get_clock(vm_clock); |
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struct dma_s *dma = (struct dma_s *) ch->dma; |
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qemu_mod_timer(ch->timer, now + delay_bytes / dma->channel_freq); |
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} |
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static void soc_dma_ch_run(void *opaque) |
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{ |
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struct soc_dma_ch_s *ch = (struct soc_dma_ch_s *) opaque; |
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ch->running = 1; |
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ch->dma->setup_fn(ch); |
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ch->transfer_fn(ch); |
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ch->running = 0; |
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if (ch->enable) |
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soc_dma_ch_schedule(ch, ch->bytes); |
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ch->bytes = 0; |
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} |
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static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma, |
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target_phys_addr_t addr) |
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{ |
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struct memmap_entry_s *lo; |
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int hi; |
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lo = dma->memmap; |
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hi = dma->memmap_size; |
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while (hi > 1) { |
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hi /= 2; |
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if (lo[hi].addr <= addr) |
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lo += hi; |
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} |
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return lo; |
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} |
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static inline enum soc_dma_port_type soc_dma_ch_update_type( |
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struct soc_dma_ch_s *ch, int port) |
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{ |
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struct dma_s *dma = (struct dma_s *) ch->dma; |
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struct memmap_entry_s *entry = soc_dma_lookup(dma, ch->vaddr[port]); |
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if (entry->type == soc_dma_port_fifo) { |
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while (entry < dma->memmap + dma->memmap_size && |
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entry->u.fifo.out != port) |
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entry ++; |
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if (entry->addr != ch->vaddr[port] || entry->u.fifo.out != port) |
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return soc_dma_port_other; |
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if (ch->type[port] != soc_dma_access_const) |
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return soc_dma_port_other; |
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ch->io_fn[port] = entry->u.fifo.fn; |
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ch->io_opaque[port] = entry->u.fifo.opaque; |
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return soc_dma_port_fifo; |
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} else if (entry->type == soc_dma_port_mem) { |
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if (entry->addr > ch->vaddr[port] || |
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entry->addr + entry->u.mem.size <= ch->vaddr[port]) |
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return soc_dma_port_other; |
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/* TODO: support constant memory address for source port as used for
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* drawing solid rectangles by PalmOS(R). */ |
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if (ch->type[port] != soc_dma_access_const) |
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return soc_dma_port_other; |
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ch->paddr[port] = (uint8_t *) entry->u.mem.base + |
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(ch->vaddr[port] - entry->addr); |
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/* TODO: save bytes left to the end of the mapping somewhere so we
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* can check we're not reading beyond it. */ |
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return soc_dma_port_mem; |
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} else |
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return soc_dma_port_other; |
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} |
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void soc_dma_ch_update(struct soc_dma_ch_s *ch) |
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{ |
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enum soc_dma_port_type src, dst; |
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src = soc_dma_ch_update_type(ch, 0); |
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if (src == soc_dma_port_other) { |
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ch->update = 0; |
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ch->transfer_fn = ch->dma->transfer_fn; |
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return; |
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} |
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dst = soc_dma_ch_update_type(ch, 1); |
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/* TODO: use src and dst as array indices. */ |
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if (src == soc_dma_port_mem && dst == soc_dma_port_mem) |
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ch->transfer_fn = transfer_mem2mem; |
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else if (src == soc_dma_port_mem && dst == soc_dma_port_fifo) |
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ch->transfer_fn = transfer_mem2fifo; |
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else if (src == soc_dma_port_fifo && dst == soc_dma_port_mem) |
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ch->transfer_fn = transfer_fifo2mem; |
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else if (src == soc_dma_port_fifo && dst == soc_dma_port_fifo) |
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ch->transfer_fn = transfer_fifo2fifo; |
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else |
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ch->transfer_fn = ch->dma->transfer_fn; |
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ch->update = (dst != soc_dma_port_other); |
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} |
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static void soc_dma_ch_freq_update(struct dma_s *s) |
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{ |
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if (s->enabled_count) |
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/* We completely ignore channel priorities and stuff */ |
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s->channel_freq = s->soc.freq / s->enabled_count; |
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else |
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/* TODO: Signal that we want to disable the functional clock and let
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* the platform code decide what to do with it, i.e. check that |
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* auto-idle is enabled in the clock controller and if we are stopping |
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* the clock, do the same with any parent clocks that had only one |
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* user keeping them on and auto-idle enabled. */; |
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} |
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void soc_dma_set_request(struct soc_dma_ch_s *ch, int level) |
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{ |
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struct dma_s *dma = (struct dma_s *) ch->dma; |
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dma->enabled_count += level - ch->enable; |
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if (level) |
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dma->ch_enable_mask |= 1 << ch->num; |
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else |
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dma->ch_enable_mask &= ~(1 << ch->num); |
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if (level != ch->enable) { |
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soc_dma_ch_freq_update(dma); |
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ch->enable = level; |
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if (!ch->enable) |
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qemu_del_timer(ch->timer); |
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else if (!ch->running) |
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soc_dma_ch_run(ch); |
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else |
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soc_dma_ch_schedule(ch, 1); |
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} |
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} |
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void soc_dma_reset(struct soc_dma_s *soc) |
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{ |
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struct dma_s *s = (struct dma_s *) soc; |
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s->soc.drqbmp = 0; |
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s->ch_enable_mask = 0; |
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s->enabled_count = 0; |
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soc_dma_ch_freq_update(s); |
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} |
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/* TODO: take a functional-clock argument */ |
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struct soc_dma_s *soc_dma_init(int n) |
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{ |
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int i; |
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struct dma_s *s = qemu_mallocz(sizeof(*s) + n * sizeof(*s->ch)); |
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s->chnum = n; |
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s->soc.ch = s->ch; |
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for (i = 0; i < n; i ++) { |
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s->ch[i].dma = &s->soc; |
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s->ch[i].num = i; |
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s->ch[i].timer = qemu_new_timer(vm_clock, soc_dma_ch_run, &s->ch[i]); |
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} |
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soc_dma_reset(&s->soc); |
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return &s->soc; |
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} |
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void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base, |
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soc_dma_io_t fn, void *opaque, int out) |
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{ |
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struct memmap_entry_s *entry; |
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struct dma_s *dma = (struct dma_s *) soc; |
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dma->memmap = realloc(dma->memmap, sizeof(*entry) * |
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(dma->memmap_size + 1)); |
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entry = soc_dma_lookup(dma, virt_base); |
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if (dma->memmap_size) { |
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if (entry->type == soc_dma_port_mem) { |
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if (entry->addr <= virt_base && |
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entry->addr + entry->u.mem.size > virt_base) { |
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fprintf(stderr, "%s: FIFO at " TARGET_FMT_lx |
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" collides with RAM region at " TARGET_FMT_lx |
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"-" TARGET_FMT_lx "\n", __FUNCTION__, |
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(target_ulong) virt_base, |
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(target_ulong) entry->addr, (target_ulong) |
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(entry->addr + entry->u.mem.size)); |
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exit(-1); |
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} |
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if (entry->addr <= virt_base) |
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entry ++; |
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} else |
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while (entry < dma->memmap + dma->memmap_size && |
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entry->addr <= virt_base) { |
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if (entry->addr == virt_base && entry->u.fifo.out == out) { |
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fprintf(stderr, "%s: FIFO at " TARGET_FMT_lx |
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" collides FIFO at " TARGET_FMT_lx "\n", |
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__FUNCTION__, (target_ulong) virt_base, |
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(target_ulong) entry->addr); |
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exit(-1); |
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} |
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entry ++; |
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} |
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memmove(entry + 1, entry, |
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(uint8_t *) (dma->memmap + dma->memmap_size ++) - |
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(uint8_t *) entry); |
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} else |
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dma->memmap_size ++; |
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entry->addr = virt_base; |
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entry->type = soc_dma_port_fifo; |
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entry->u.fifo.fn = fn; |
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entry->u.fifo.opaque = opaque; |
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entry->u.fifo.out = out; |
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} |
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void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base, |
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target_phys_addr_t virt_base, size_t size) |
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{ |
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struct memmap_entry_s *entry; |
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struct dma_s *dma = (struct dma_s *) soc; |
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dma->memmap = realloc(dma->memmap, sizeof(*entry) * |
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(dma->memmap_size + 1)); |
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entry = soc_dma_lookup(dma, virt_base); |
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if (dma->memmap_size) { |
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if (entry->type == soc_dma_port_mem) { |
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if ((entry->addr >= virt_base && entry->addr < virt_base + size) || |
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(entry->addr <= virt_base && |
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entry->addr + entry->u.mem.size > virt_base)) { |
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fprintf(stderr, "%s: RAM at " TARGET_FMT_lx "-" TARGET_FMT_lx |
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" collides with RAM region at " TARGET_FMT_lx |
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"-" TARGET_FMT_lx "\n", __FUNCTION__, |
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(target_ulong) virt_base, |
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(target_ulong) (virt_base + size), |
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(target_ulong) entry->addr, (target_ulong) |
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(entry->addr + entry->u.mem.size)); |
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exit(-1); |
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} |
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if (entry->addr <= virt_base) |
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entry ++; |
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} else { |
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if (entry->addr >= virt_base && |
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entry->addr < virt_base + size) { |
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fprintf(stderr, "%s: RAM at " TARGET_FMT_lx "-" TARGET_FMT_lx |
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" collides with FIFO at " TARGET_FMT_lx |
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"\n", __FUNCTION__, |
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(target_ulong) virt_base, |
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(target_ulong) (virt_base + size), |
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(target_ulong) entry->addr); |
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exit(-1); |
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} |
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while (entry < dma->memmap + dma->memmap_size && |
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entry->addr <= virt_base) |
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entry ++; |
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} |
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memmove(entry + 1, entry, |
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(uint8_t *) (dma->memmap + dma->memmap_size ++) - |
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(uint8_t *) entry); |
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} else |
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dma->memmap_size ++; |
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entry->addr = virt_base; |
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entry->type = soc_dma_port_mem; |
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entry->u.mem.base = phys_base; |
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entry->u.mem.size = size; |
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} |
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/* TODO: port removal for ports like PCMCIA memory */ |
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@ -0,0 +1,115 @@ |
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/*
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* On-chip DMA controller framework. |
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* |
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* Copyright (C) 2008 Nokia Corporation |
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* Written by Andrzej Zaborowski <andrew@openedhand.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 or |
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* (at your option) version 3 of the License. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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struct soc_dma_s; |
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struct soc_dma_ch_s; |
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typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len); |
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typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch); |
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enum soc_dma_port_type { |
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soc_dma_port_mem, |
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soc_dma_port_fifo, |
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soc_dma_port_other, |
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}; |
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enum soc_dma_access_type { |
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soc_dma_access_const, |
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soc_dma_access_linear, |
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soc_dma_access_other, |
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}; |
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struct soc_dma_ch_s { |
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/* Private */ |
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struct soc_dma_s *dma; |
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int num; |
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QEMUTimer *timer; |
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/* Set by soc_dma.c */ |
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int enable; |
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int update; |
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/* This should be set by dma->setup_fn(). */ |
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int bytes; |
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/* Initialised by the DMA module, call soc_dma_ch_update after writing. */ |
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enum soc_dma_access_type type[2]; |
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target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */ |
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/* Private */ |
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void *paddr[2]; |
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soc_dma_io_t io_fn[2]; |
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void *io_opaque[2]; |
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int running; |
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soc_dma_transfer_t transfer_fn; |
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/* Set and used by the DMA module. */ |
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void *opaque; |
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}; |
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struct soc_dma_s { |
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/* Following fields are set by the SoC DMA module and can be used
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* by anybody. */ |
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uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ |
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qemu_irq *drq; |
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void *opaque; |
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int64_t freq; |
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soc_dma_transfer_t transfer_fn; |
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soc_dma_transfer_t setup_fn; |
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/* Set by soc_dma_init() for use by the DMA module. */ |
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struct soc_dma_ch_s *ch; |
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}; |
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|
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/* Call to activate or stop a DMA channel. */ |
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void soc_dma_set_request(struct soc_dma_ch_s *ch, int level); |
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/* Call after every write to one of the following fields and before
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* calling soc_dma_set_request(ch, 1): |
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* ch->type[0...1], |
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* ch->vaddr[0...1], |
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* ch->paddr[0...1], |
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* or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */ |
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void soc_dma_ch_update(struct soc_dma_ch_s *ch); |
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/* The SoC should call this when the DMA module is being reset. */ |
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void soc_dma_reset(struct soc_dma_s *s); |
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struct soc_dma_s *soc_dma_init(int n); |
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void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base, |
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soc_dma_io_t fn, void *opaque, int out); |
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void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base, |
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target_phys_addr_t virt_base, size_t size); |
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static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, |
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target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque) |
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{ |
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return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); |
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} |
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static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, |
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target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque) |
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{ |
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return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); |
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} |
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static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma, |
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ram_addr_t offset, target_phys_addr_t virt_base, size_t size) |
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{ |
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return soc_dma_port_add_mem(dma, phys_ram_base + offset, virt_base, size); |
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} |
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