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target/arm/machine: Use VMSTATE_VARRAY_INT32_ALLOC for cpreg arrays

This removes the need for explicitly allocating cpreg_vmstate arrays.
On post save we simply point to cpreg arrays and set the length
accordingly.

Remove VMSTATE_VARRAY_INT32 for cpreg_vmstate_array_len as now
the array is dynamically allocated.

Also add a trace point on post_load to trace potential mismatch
between the number of incoming cpregs versus current ones.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260304101625.1962633-3-eric.auger@redhat.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Eric Auger 5 months ago
committed by Peter Maydell
parent
commit
ab2ddc7b66
  1. 5
      target/arm/helper.c
  2. 5
      target/arm/kvm.c
  3. 45
      target/arm/machine.c
  4. 3
      target/arm/trace-events
  5. 7
      target/arm/whpx/whpx-all.c

5
target/arm/helper.c

@ -265,15 +265,10 @@ void arm_init_cpreg_list(ARMCPU *cpu)
if (arraylen) {
cpu->cpreg_indexes = g_new(uint64_t, arraylen);
cpu->cpreg_values = g_new(uint64_t, arraylen);
cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
} else {
cpu->cpreg_indexes = NULL;
cpu->cpreg_values = NULL;
cpu->cpreg_vmstate_indexes = NULL;
cpu->cpreg_vmstate_values = NULL;
}
cpu->cpreg_vmstate_array_len = arraylen;
cpu->cpreg_array_len = 0;
g_hash_table_foreach(cpu->cp_regs, add_cpreg_to_list, cpu);

5
target/arm/kvm.c

@ -864,12 +864,7 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu)
cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
arraylen);
cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
arraylen);
cpu->cpreg_array_len = arraylen;
cpu->cpreg_vmstate_array_len = arraylen;
for (i = 0, arraylen = 0; i < rlp->n; i++) {
uint64_t regidx = rlp->reg[i];

45
target/arm/machine.c

@ -1,5 +1,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "trace.h"
#include "qemu/error-report.h"
#include "system/kvm.h"
#include "system/tcg.h"
@ -984,11 +985,14 @@ static int cpu_pre_save(void *opaque)
}
}
/*
* On outbound migration, send the data in our cpreg_{values,indexes}
* arrays. The migration code will not allocate anything, but just
* reads the data pointed to by the VMSTATE_VARRAY_INT32_ALLOC() fields.
*/
cpu->cpreg_vmstate_indexes = cpu->cpreg_indexes;
cpu->cpreg_vmstate_values = cpu->cpreg_values;
cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
cpu->cpreg_array_len * sizeof(uint64_t));
memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
cpu->cpreg_array_len * sizeof(uint64_t));
return 0;
}
@ -1001,6 +1005,9 @@ static int cpu_post_save(void *opaque)
pmu_op_finish(&cpu->env);
}
cpu->cpreg_vmstate_indexes = NULL;
cpu->cpreg_vmstate_values = NULL;
return 0;
}
@ -1034,6 +1041,9 @@ static int cpu_pre_load(void *opaque)
pmu_op_start(env);
}
g_assert(!cpu->cpreg_vmstate_indexes);
g_assert(!cpu->cpreg_vmstate_values);
return 0;
}
@ -1043,6 +1053,9 @@ static int cpu_post_load(void *opaque, int version_id)
CPUARMState *env = &cpu->env;
int i, v;
trace_cpu_post_load(cpu->cpreg_vmstate_array_len,
cpu->cpreg_array_len);
/*
* Handle migration compatibility from old QEMU which didn't
* send the irq-line-state subsection. A QEMU without it did not
@ -1094,6 +1107,11 @@ static int cpu_post_load(void *opaque, int version_id)
}
}
g_free(cpu->cpreg_vmstate_indexes);
g_free(cpu->cpreg_vmstate_values);
cpu->cpreg_vmstate_indexes = NULL;
cpu->cpreg_vmstate_values = NULL;
/*
* Misaligned thumb pc is architecturally impossible. Fail the
* incoming migration. For TCG it would trigger the assert in
@ -1167,16 +1185,17 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
/* The length-check must come before the arrays to avoid
* incoming data possibly overflowing the array.
/*
* The length must come before the arrays so we can
* allocate the arrays before their data arrives
*/
VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
cpreg_vmstate_array_len,
0, vmstate_info_uint64, uint64_t),
VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
cpreg_vmstate_array_len,
0, vmstate_info_uint64, uint64_t),
VMSTATE_INT32(cpreg_vmstate_array_len, ARMCPU),
VMSTATE_VARRAY_INT32_ALLOC(cpreg_vmstate_indexes, ARMCPU,
cpreg_vmstate_array_len,
0, vmstate_info_uint64, uint64_t),
VMSTATE_VARRAY_INT32_ALLOC(cpreg_vmstate_values, ARMCPU,
cpreg_vmstate_array_len,
0, vmstate_info_uint64, uint64_t),
VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
VMSTATE_UINT64(env.exclusive_val, ARMCPU),
VMSTATE_UINT64(env.exclusive_high, ARMCPU),

3
target/arm/trace-events

@ -26,3 +26,6 @@ arm_powerctl_reset_cpu(uint64_t mp_aff) "cpu %" PRIu64
# tcg/psci.c and hvf/hvf.c
arm_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpuid=0x%x"
# machine.c
cpu_post_load(uint32_t cpreg_vmstate_array_len, uint32_t cpreg_array_len) "cpreg_vmstate_array_len=%d cpreg_array_len=%d"

7
target/arm/whpx/whpx-all.c

@ -783,12 +783,6 @@ int whpx_init_vcpu(CPUState *cpu)
sregs_match_len);
arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
sregs_match_len);
arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
arm_cpu->cpreg_vmstate_indexes,
sregs_match_len);
arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
arm_cpu->cpreg_vmstate_values,
sregs_match_len);
memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
@ -807,7 +801,6 @@ int whpx_init_vcpu(CPUState *cpu)
}
}
arm_cpu->cpreg_array_len = sregs_cnt;
arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
assert(write_cpustate_to_list(arm_cpu, false));

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