Browse Source
- Update the PLIC and CLINT DT bindings - Improve documentation for RISC-V machines - Support direct kernel boot for microchip_pfsoc - Fix WFI exception behaviour - Improve CSR printing - Initial support for the experimental Bit Manip extension -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmC+uasACgkQIeENKd+X cFTUFwf/TqBBNl8oWFBMTeV+Puwy5s8l9LZpBzWq6W0Wd3y/RyetutMI0v2ir3lC ezGMLEmGSvYVugDzb2tdZI1DOx/ka8d3mzyU7+Jf8/LA9LCBp0Uj0kVKOw5wL8+V LoTT6/v0ymEr7Achp4LSpxY//A4BxcCfFRxH83BdUHeybl37UvUpXkaAraGUjfVR afoB4KQk/IrhT4KtCXnSqr3T/Q9vVHnXhkKOFiR6db3RqWtyq9VDI/lwx/X1Vg+V iaP/a5IGhfGJP+IHPyEINrp6LPJv8qBl1j0PXhbo2NbIJtZr7lJdB/hmfKOjcHag r5RtzGVa+JODY4JTTYa1UlXiLVsVHw== =Dhie -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging Second RISC-V PR for QEMU 6.1 - Update the PLIC and CLINT DT bindings - Improve documentation for RISC-V machines - Support direct kernel boot for microchip_pfsoc - Fix WFI exception behaviour - Improve CSR printing - Initial support for the experimental Bit Manip extension # gpg: Signature made Tue 08 Jun 2021 01:28:27 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits) target/riscv: rvb: add b-ext version cpu option target/riscv: rvb: support and turn on B-extension from command line target/riscv: rvb: add/shift with prefix zero-extend target/riscv: rvb: address calculation target/riscv: rvb: generalized or-combine target/riscv: rvb: generalized reverse target/riscv: rvb: rotate (left/right) target/riscv: rvb: shift ones target/riscv: rvb: single-bit instructions target/riscv: add gen_shifti() and gen_shiftiw() helper functions target/riscv: rvb: sign-extend instructions target/riscv: rvb: min/max instructions target/riscv: rvb: pack two words into one register target/riscv: rvb: logic-with-negate target/riscv: rvb: count bits set target/riscv: rvb: count leading/trailing zeros target/riscv: reformat @sh format encoding for B-extension target/riscv: Pass the same value to oprsz and maxsz. target/riscv/pmp: Add assert for ePMP operations target/riscv: Dump CSR mscratch/sscratch/satp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>pull/121/head
Peter Maydell
5 years ago
23 changed files with 1258 additions and 185 deletions
@ -0,0 +1,90 @@ |
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/*
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* RISC-V Bitmanip Extension Helpers for QEMU. |
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* |
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com |
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2 or later, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License along with |
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include "qemu/osdep.h" |
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#include "qemu/host-utils.h" |
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#include "exec/exec-all.h" |
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#include "exec/helper-proto.h" |
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#include "tcg/tcg.h" |
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static const uint64_t adjacent_masks[] = { |
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dup_const(MO_8, 0x55), |
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dup_const(MO_8, 0x33), |
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dup_const(MO_8, 0x0f), |
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dup_const(MO_16, 0xff), |
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dup_const(MO_32, 0xffff), |
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UINT32_MAX |
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}; |
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static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift) |
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{ |
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return ((x & mask) << shift) | ((x & ~mask) >> shift); |
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} |
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static target_ulong do_grev(target_ulong rs1, |
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target_ulong rs2, |
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int bits) |
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{ |
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target_ulong x = rs1; |
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int i, shift; |
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for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) { |
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if (rs2 & shift) { |
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x = do_swap(x, adjacent_masks[i], shift); |
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} |
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} |
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return x; |
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} |
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target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2) |
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{ |
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return do_grev(rs1, rs2, TARGET_LONG_BITS); |
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} |
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target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2) |
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{ |
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return do_grev(rs1, rs2, 32); |
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} |
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static target_ulong do_gorc(target_ulong rs1, |
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target_ulong rs2, |
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int bits) |
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{ |
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target_ulong x = rs1; |
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int i, shift; |
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for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) { |
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if (rs2 & shift) { |
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x |= do_swap(x, adjacent_masks[i], shift); |
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} |
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} |
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return x; |
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} |
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target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2) |
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{ |
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return do_gorc(rs1, rs2, TARGET_LONG_BITS); |
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} |
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target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2) |
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{ |
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return do_gorc(rs1, rs2, 32); |
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} |
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@ -0,0 +1,438 @@ |
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/* |
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* RISC-V translation routines for the RVB Standard Extension. |
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* |
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com |
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2 or later, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License along with |
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* this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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static bool trans_clz(DisasContext *ctx, arg_clz *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, gen_clz); |
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} |
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static bool trans_ctz(DisasContext *ctx, arg_ctz *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, gen_ctz); |
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} |
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static bool trans_cpop(DisasContext *ctx, arg_cpop *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, tcg_gen_ctpop_tl); |
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} |
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static bool trans_andn(DisasContext *ctx, arg_andn *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_andc_tl); |
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} |
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static bool trans_orn(DisasContext *ctx, arg_orn *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_orc_tl); |
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} |
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static bool trans_xnor(DisasContext *ctx, arg_xnor *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_eqv_tl); |
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} |
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static bool trans_pack(DisasContext *ctx, arg_pack *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, gen_pack); |
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} |
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static bool trans_packu(DisasContext *ctx, arg_packu *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, gen_packu); |
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} |
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static bool trans_packh(DisasContext *ctx, arg_packh *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, gen_packh); |
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} |
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static bool trans_min(DisasContext *ctx, arg_min *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_smin_tl); |
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} |
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static bool trans_max(DisasContext *ctx, arg_max *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_smax_tl); |
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} |
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static bool trans_minu(DisasContext *ctx, arg_minu *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_umin_tl); |
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} |
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static bool trans_maxu(DisasContext *ctx, arg_maxu *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, tcg_gen_umax_tl); |
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} |
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static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, tcg_gen_ext8s_tl); |
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} |
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static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, tcg_gen_ext16s_tl); |
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} |
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static bool trans_bset(DisasContext *ctx, arg_bset *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_bset); |
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} |
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static bool trans_bseti(DisasContext *ctx, arg_bseti *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_bset); |
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} |
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static bool trans_bclr(DisasContext *ctx, arg_bclr *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_bclr); |
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} |
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static bool trans_bclri(DisasContext *ctx, arg_bclri *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_bclr); |
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} |
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static bool trans_binv(DisasContext *ctx, arg_binv *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_binv); |
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} |
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static bool trans_binvi(DisasContext *ctx, arg_binvi *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_binv); |
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} |
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static bool trans_bext(DisasContext *ctx, arg_bext *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_bext); |
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} |
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static bool trans_bexti(DisasContext *ctx, arg_bexti *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_bext); |
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} |
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static bool trans_slo(DisasContext *ctx, arg_slo *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_slo); |
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} |
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static bool trans_sloi(DisasContext *ctx, arg_sloi *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_slo); |
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} |
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static bool trans_sro(DisasContext *ctx, arg_sro *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_sro); |
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} |
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static bool trans_sroi(DisasContext *ctx, arg_sroi *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_sro); |
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} |
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static bool trans_ror(DisasContext *ctx, arg_ror *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, tcg_gen_rotr_tl); |
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} |
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static bool trans_rori(DisasContext *ctx, arg_rori *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, tcg_gen_rotr_tl); |
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} |
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static bool trans_rol(DisasContext *ctx, arg_rol *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, tcg_gen_rotl_tl); |
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} |
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static bool trans_grev(DisasContext *ctx, arg_grev *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_helper_grev); |
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} |
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static bool trans_grevi(DisasContext *ctx, arg_grevi *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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if (a->shamt >= TARGET_LONG_BITS) { |
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return false; |
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} |
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return gen_grevi(ctx, a); |
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} |
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static bool trans_gorc(DisasContext *ctx, arg_gorc *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shift(ctx, a, gen_helper_gorc); |
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} |
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static bool trans_gorci(DisasContext *ctx, arg_gorci *a) |
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{ |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shifti(ctx, a, gen_helper_gorc); |
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} |
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#define GEN_TRANS_SHADD(SHAMT) \ |
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static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \ |
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{ \ |
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REQUIRE_EXT(ctx, RVB); \ |
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return gen_arith(ctx, a, gen_sh##SHAMT##add); \ |
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} |
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GEN_TRANS_SHADD(1) |
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GEN_TRANS_SHADD(2) |
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GEN_TRANS_SHADD(3) |
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static bool trans_clzw(DisasContext *ctx, arg_clzw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, gen_clzw); |
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} |
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static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, gen_ctzw); |
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} |
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static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_unary(ctx, a, gen_cpopw); |
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} |
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static bool trans_packw(DisasContext *ctx, arg_packw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, gen_packw); |
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} |
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static bool trans_packuw(DisasContext *ctx, arg_packuw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_arith(ctx, a, gen_packuw); |
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} |
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static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_bset); |
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} |
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static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftiw(ctx, a, gen_bset); |
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} |
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static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_bclr); |
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} |
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static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftiw(ctx, a, gen_bclr); |
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} |
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static bool trans_binvw(DisasContext *ctx, arg_binvw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_binv); |
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} |
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static bool trans_binviw(DisasContext *ctx, arg_binviw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftiw(ctx, a, gen_binv); |
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} |
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static bool trans_bextw(DisasContext *ctx, arg_bextw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_bext); |
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} |
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static bool trans_slow(DisasContext *ctx, arg_slow *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_slo); |
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} |
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|
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static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftiw(ctx, a, gen_slo); |
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} |
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|
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static bool trans_srow(DisasContext *ctx, arg_srow *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_sro); |
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} |
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|
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static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftiw(ctx, a, gen_sro); |
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} |
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|
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static bool trans_rorw(DisasContext *ctx, arg_rorw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_rorw); |
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} |
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|
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static bool trans_roriw(DisasContext *ctx, arg_roriw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftiw(ctx, a, gen_rorw); |
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} |
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|
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static bool trans_rolw(DisasContext *ctx, arg_rolw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_rolw); |
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} |
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|
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static bool trans_grevw(DisasContext *ctx, arg_grevw *a) |
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{ |
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REQUIRE_64BIT(ctx); |
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REQUIRE_EXT(ctx, RVB); |
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return gen_shiftw(ctx, a, gen_grevw); |
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} |
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|
|||
static bool trans_greviw(DisasContext *ctx, arg_greviw *a) |
|||
{ |
|||
REQUIRE_64BIT(ctx); |
|||
REQUIRE_EXT(ctx, RVB); |
|||
return gen_shiftiw(ctx, a, gen_grevw); |
|||
} |
|||
|
|||
static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a) |
|||
{ |
|||
REQUIRE_64BIT(ctx); |
|||
REQUIRE_EXT(ctx, RVB); |
|||
return gen_shiftw(ctx, a, gen_gorcw); |
|||
} |
|||
|
|||
static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a) |
|||
{ |
|||
REQUIRE_64BIT(ctx); |
|||
REQUIRE_EXT(ctx, RVB); |
|||
return gen_shiftiw(ctx, a, gen_gorcw); |
|||
} |
|||
|
|||
#define GEN_TRANS_SHADD_UW(SHAMT) \ |
|||
static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ |
|||
arg_sh##SHAMT##add_uw *a) \ |
|||
{ \ |
|||
REQUIRE_64BIT(ctx); \ |
|||
REQUIRE_EXT(ctx, RVB); \ |
|||
return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \ |
|||
} |
|||
|
|||
GEN_TRANS_SHADD_UW(1) |
|||
GEN_TRANS_SHADD_UW(2) |
|||
GEN_TRANS_SHADD_UW(3) |
|||
|
|||
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) |
|||
{ |
|||
REQUIRE_64BIT(ctx); |
|||
REQUIRE_EXT(ctx, RVB); |
|||
return gen_arith(ctx, a, gen_add_uw); |
|||
} |
|||
|
|||
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) |
|||
{ |
|||
REQUIRE_64BIT(ctx); |
|||
REQUIRE_EXT(ctx, RVB); |
|||
|
|||
TCGv source1 = tcg_temp_new(); |
|||
gen_get_gpr(source1, a->rs1); |
|||
|
|||
if (a->shamt < 32) { |
|||
tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); |
|||
} else { |
|||
tcg_gen_shli_tl(source1, source1, a->shamt); |
|||
} |
|||
|
|||
gen_set_gpr(a->rd, source1); |
|||
tcg_temp_free(source1); |
|||
return true; |
|||
} |
|||
Loading…
Reference in new issue