Browse Source
* Support for PowerNV11 and PPE42 CPU/Machines. * Deprecation of Power8E and Power8NVL * Decodetree patches for some floating-point instructions * Minor bug fixes, improvements in ppc/spapr/xive/xics. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmjZgYQACgkQRUTplPnW j7uNJQ/8Cbr3xqyCyyqL+MM+Ze1PbXe4xSgdg13A1sNU3IHTffB77DCQVOxjudUS uo+XHVFssc4SKDZYjEzXFnYpzRpbZzfcuhG4kgn9QQ3VyKP+2xe6kWLleDbB6ds1 e9ZAW6Ryk4R3ZFLnZzGfEdltliaoIn6zy4R25oJfJUgIRt0Xz++GBxll+Tdr8Exy qstvvyyjeTiIS3kA1zk6fbhDRJKKBsA0L1G1Pk6AuTMKa1RRTCniA36idnGVFAuY ef8WCEQYQS0do9Ytai06Tp1QNRVMG2y+AsKbSQRMi92lFfn+qhvA29OJd5TNvXtp LNiIfXHo3jLjGBUP13iVN8b8udWdis9BayvA/OwDaKWgononEHb9nqJgzVJR4n7t DxxUxcSCiEXOpObtklrKhi1nDt16nXPZ/bnnreMSWzxHBZK1My7qnI3S0hA7c11z YgssB5wJbRaETaEVzQfWfAcSaPpXBzBEXOAJcbd+Ni6w9SxXz2OrhckTOvfrXpmI XQ1KFUCkmTtXF1qB+oEihlrvG2qjdGuleRZdyiktaM2psBFgN/2gHl3S+JjL9kiY 9FdBffr/2K604l7EQkAYWixe2WMMsjHVHpuxJ7opG7MMSXJZq9cXKIK+tbkSNoRO Ia6Qr6eWJWjFF3y4OZCbYAOVU77ez6lo7kRj0e99fOjxfI+UuWU= =Fjdq -----END PGP SIGNATURE----- Merge tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu into staging ppc queue for 20250928 * Support for PowerNV11 and PPE42 CPU/Machines. * Deprecation of Power8E and Power8NVL * Decodetree patches for some floating-point instructions * Minor bug fixes, improvements in ppc/spapr/xive/xics. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmjZgYQACgkQRUTplPnW # j7uNJQ/8Cbr3xqyCyyqL+MM+Ze1PbXe4xSgdg13A1sNU3IHTffB77DCQVOxjudUS # uo+XHVFssc4SKDZYjEzXFnYpzRpbZzfcuhG4kgn9QQ3VyKP+2xe6kWLleDbB6ds1 # e9ZAW6Ryk4R3ZFLnZzGfEdltliaoIn6zy4R25oJfJUgIRt0Xz++GBxll+Tdr8Exy # qstvvyyjeTiIS3kA1zk6fbhDRJKKBsA0L1G1Pk6AuTMKa1RRTCniA36idnGVFAuY # ef8WCEQYQS0do9Ytai06Tp1QNRVMG2y+AsKbSQRMi92lFfn+qhvA29OJd5TNvXtp # LNiIfXHo3jLjGBUP13iVN8b8udWdis9BayvA/OwDaKWgononEHb9nqJgzVJR4n7t # DxxUxcSCiEXOpObtklrKhi1nDt16nXPZ/bnnreMSWzxHBZK1My7qnI3S0hA7c11z # YgssB5wJbRaETaEVzQfWfAcSaPpXBzBEXOAJcbd+Ni6w9SxXz2OrhckTOvfrXpmI # XQ1KFUCkmTtXF1qB+oEihlrvG2qjdGuleRZdyiktaM2psBFgN/2gHl3S+JjL9kiY # 9FdBffr/2K604l7EQkAYWixe2WMMsjHVHpuxJ7opG7MMSXJZq9cXKIK+tbkSNoRO # Ia6Qr6eWJWjFF3y4OZCbYAOVU77ez6lo7kRj0e99fOjxfI+UuWU= # =Fjdq # -----END PGP SIGNATURE----- # gpg: Signature made Sun 28 Sep 2025 11:42:12 AM PDT # gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB # gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined] # gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB * tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu: (27 commits) target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask target/ppc: Deprecate Power8E and Power8NVL target/ppc: Introduce macro for deprecating PowerPC CPUs target/ppc: Move remaining floating-point move instructions to decodetree. target/ppc: Move floating-point move instructions to decodetree. target/ppc: Move floating-point compare instructions to decodetree. target/ppc: Move floating-point rounding and conversion instructions to decodetree. ppc/xive2: Fix integer overflow warning in xive2_redistribute() ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided hw/intc/xics: Add missing call to register vmstate_icp_server tests/functional: Add test for IBM PPE42 instructions hw/ppc: Add a test machine for the IBM PPE42 CPU hw/ppc: Support for an IBM PPE42 CPU decrementer target/ppc: Add IBM PPE42 special instructions target/ppc: Support for IBM PPE42 MMU target/ppc: Add IBM PPE42 exception model target/ppc: IBM PPE42 exception flags and regs target/ppc: Add IBM PPE42 family of processors target/ppc: IBM PPE42 general regs and flags tests/powernv: Add PowerNV test for Power11 ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>pull/305/head
Richard Henderson
6 months ago
36 changed files with 2407 additions and 368 deletions
@ -0,0 +1,101 @@ |
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/*
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* Test Machine for the IBM PPE42 processor |
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* |
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* Copyright (c) 2025, IBM Corporation. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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#include "qemu/osdep.h" |
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#include "qemu/units.h" |
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#include "qemu/error-report.h" |
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#include "system/address-spaces.h" |
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#include "hw/boards.h" |
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#include "hw/ppc/ppc.h" |
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#include "system/system.h" |
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#include "system/reset.h" |
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#include "system/kvm.h" |
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#include "qapi/error.h" |
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#define TYPE_PPE42_MACHINE MACHINE_TYPE_NAME("ppe42_machine") |
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typedef MachineClass Ppe42MachineClass; |
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typedef struct Ppe42MachineState Ppe42MachineState; |
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DECLARE_OBJ_CHECKERS(Ppe42MachineState, Ppe42MachineClass, |
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PPE42_MACHINE, TYPE_PPE42_MACHINE) |
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struct Ppe42MachineState { |
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MachineState parent_obj; |
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PowerPCCPU cpu; |
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}; |
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static void main_cpu_reset(void *opaque) |
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{ |
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PowerPCCPU *cpu = opaque; |
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cpu_reset(CPU(cpu)); |
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} |
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static void ppe42_machine_init(MachineState *machine) |
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{ |
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Ppe42MachineState *pms = PPE42_MACHINE(machine); |
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PowerPCCPU *cpu = &pms->cpu; |
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if (kvm_enabled()) { |
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error_report("machine %s does not support the KVM accelerator", |
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MACHINE_GET_CLASS(machine)->name); |
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exit(EXIT_FAILURE); |
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} |
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if (machine->ram_size > 512 * KiB) { |
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error_report("RAM size more than 512 KiB is not supported"); |
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exit(1); |
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} |
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/* init CPU */ |
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object_initialize_child(OBJECT(pms), "cpu", cpu, machine->cpu_type); |
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if (!qdev_realize(DEVICE(cpu), NULL, &error_fatal)) { |
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return; |
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} |
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qemu_register_reset(main_cpu_reset, cpu); |
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/* This sets the decrementer timebase */ |
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ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE); |
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/* RAM */ |
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memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->ram); |
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} |
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static void ppe42_machine_class_init(ObjectClass *oc, const void *data) |
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{ |
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MachineClass *mc = MACHINE_CLASS(oc); |
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static const char * const valid_cpu_types[] = { |
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POWERPC_CPU_TYPE_NAME("PPE42"), |
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POWERPC_CPU_TYPE_NAME("PPE42X"), |
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POWERPC_CPU_TYPE_NAME("PPE42XM"), |
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NULL, |
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}; |
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mc->desc = "PPE42 Test Machine"; |
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mc->init = ppe42_machine_init; |
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("PPE42XM"); |
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mc->valid_cpu_types = valid_cpu_types; |
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mc->default_ram_id = "ram"; |
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mc->default_ram_size = 512 * KiB; |
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} |
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static const TypeInfo ppe42_machine_info = { |
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.name = TYPE_PPE42_MACHINE, |
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.parent = TYPE_MACHINE, |
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.instance_size = sizeof(Ppe42MachineState), |
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.class_init = ppe42_machine_class_init, |
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.class_size = sizeof(Ppe42MachineClass), |
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}; |
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static void ppe42_machine_register_types(void) |
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{ |
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type_register_static(&ppe42_machine_info); |
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} |
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type_init(ppe42_machine_register_types); |
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@ -0,0 +1,609 @@ |
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/* |
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* IBM PPE Instructions |
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* |
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* Copyright (c) 2025, IBM Corporation. |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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static bool vdr_is_valid(uint32_t vdr) |
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{ |
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const uint32_t valid_bitmap = 0xf00003ff; |
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return !!((1ul << (vdr & 0x1f)) & valid_bitmap); |
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} |
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static bool ppe_gpr_is_valid(uint32_t reg) |
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{ |
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const uint32_t valid_bitmap = 0xf00027ff; |
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return !!((1ul << (reg & 0x1f)) & valid_bitmap); |
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} |
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#define CHECK_VDR(CTX, VDR) \ |
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do { \ |
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if (unlikely(!vdr_is_valid(VDR))) { \ |
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gen_invalid(CTX); \ |
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return true; \ |
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} \ |
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} while (0) |
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|
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#define CHECK_PPE_GPR(CTX, REG) \ |
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do { \ |
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if (unlikely(!ppe_gpr_is_valid(REG))) { \ |
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gen_invalid(CTX); \ |
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return true; \ |
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} \ |
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} while (0) |
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#define VDR_PAIR_REG(VDR) (((VDR) + 1) & 0x1f) |
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#define CHECK_PPE_LEVEL(CTX, LVL) \ |
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do { \ |
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if (unlikely(!((CTX)->insns_flags2 & (LVL)))) { \ |
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gen_invalid(CTX); \ |
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return true; \ |
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} \ |
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} while (0) |
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static bool trans_LCXU(DisasContext *ctx, arg_LCXU *a) |
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{ |
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int i; |
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TCGv base, EA; |
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TCGv lo, hi; |
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TCGv_i64 t8; |
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const uint8_t vd_list[] = {9, 7, 5, 3, 0}; |
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if (unlikely(!is_ppe(ctx))) { |
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return false; |
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} |
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CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
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CHECK_PPE_GPR(ctx, a->rt); |
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if (unlikely((a->rt != a->ra) || (a->ra == 0) || (a->si < 0xB))) { |
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gen_invalid(ctx); |
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return true; |
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} |
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EA = tcg_temp_new(); |
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base = tcg_temp_new(); |
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tcg_gen_addi_tl(base, cpu_gpr[a->ra], a->si * 8); |
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gen_store_spr(SPR_PPE42_EDR, base); |
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t8 = tcg_temp_new_i64(); |
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tcg_gen_addi_tl(EA, base, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_extr_i64_tl(cpu_gpr[31], cpu_gpr[30], t8); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_extr_i64_tl(cpu_gpr[29], cpu_gpr[28], t8); |
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lo = tcg_temp_new(); |
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hi = tcg_temp_new(); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_extr_i64_tl(lo, hi, t8); |
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gen_store_spr(SPR_SRR0, hi); |
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gen_store_spr(SPR_SRR1, lo); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_extr_i64_tl(lo, hi, t8); |
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gen_set_xer(ctx, hi); |
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tcg_gen_mov_tl(cpu_ctr, lo); |
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for (i = 0; i < sizeof(vd_list); i++) { |
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int vd = vd_list[i]; |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_extr_i64_tl(cpu_gpr[VDR_PAIR_REG(vd)], cpu_gpr[vd], t8); |
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} |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_extr_i64_tl(lo, hi, t8); |
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tcg_gen_shri_tl(hi, hi, 28); |
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tcg_gen_trunc_tl_i32(cpu_crf[0], hi); |
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gen_store_spr(SPR_SPRG0, lo); |
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tcg_gen_addi_tl(EA, base, 4); |
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tcg_gen_qemu_ld_tl(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_ALIGN); |
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tcg_gen_mov_tl(cpu_gpr[a->ra], base); |
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return true; |
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} |
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static bool trans_LSKU(DisasContext *ctx, arg_LSKU *a) |
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{ |
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int64_t n; |
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TCGv base, EA; |
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TCGv lo, hi; |
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TCGv_i64 t8; |
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if (unlikely(!is_ppe(ctx))) { |
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return false; |
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} |
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CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
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CHECK_PPE_GPR(ctx, a->rt); |
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if (unlikely((a->rt != a->ra) || (a->ra == 0) || |
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(a->si & PPC_BIT(0)) || (a->si == 0))) { |
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gen_invalid(ctx); |
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return true; |
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} |
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EA = tcg_temp_new(); |
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base = tcg_temp_new(); |
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gen_addr_register(ctx, base); |
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tcg_gen_addi_tl(base, base, a->si * 8); |
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gen_store_spr(SPR_PPE42_EDR, base); |
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n = a->si - 1; |
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t8 = tcg_temp_new_i64(); |
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if (n > 0) { |
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tcg_gen_addi_tl(EA, base, -8); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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hi = cpu_gpr[30]; |
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lo = cpu_gpr[31]; |
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tcg_gen_extr_i64_tl(lo, hi, t8); |
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} |
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if (n > 1) { |
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tcg_gen_addi_tl(EA, base, -16); |
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tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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hi = cpu_gpr[28]; |
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lo = cpu_gpr[29]; |
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tcg_gen_extr_i64_tl(lo, hi, t8); |
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} |
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tcg_gen_addi_tl(EA, base, 4); |
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tcg_gen_qemu_ld_tl(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_ALIGN); |
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tcg_gen_mov_tl(cpu_gpr[a->ra], base); |
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return true; |
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} |
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static bool trans_STCXU(DisasContext *ctx, arg_STCXU *a) |
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{ |
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TCGv EA; |
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TCGv lo, hi; |
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TCGv_i64 t8; |
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int i; |
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const uint8_t vd_list[] = {9, 7, 5, 3, 0}; |
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if (unlikely(!is_ppe(ctx))) { |
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return false; |
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} |
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CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
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CHECK_PPE_GPR(ctx, a->rt); |
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if (unlikely((a->rt != a->ra) || (a->ra == 0) || !(a->si & PPC_BIT(0)))) { |
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gen_invalid(ctx); |
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return true; |
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} |
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EA = tcg_temp_new(); |
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tcg_gen_addi_tl(EA, cpu_gpr[a->ra], 4); |
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tcg_gen_qemu_st_tl(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_ALIGN); |
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gen_store_spr(SPR_PPE42_EDR, cpu_gpr[a->ra]); |
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t8 = tcg_temp_new_i64(); |
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tcg_gen_concat_tl_i64(t8, cpu_gpr[31], cpu_gpr[30]); |
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tcg_gen_addi_tl(EA, cpu_gpr[a->ra], -8); |
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tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_concat_tl_i64(t8, cpu_gpr[29], cpu_gpr[28]); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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lo = tcg_temp_new(); |
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hi = tcg_temp_new(); |
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gen_load_spr(hi, SPR_SRR0); |
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gen_load_spr(lo, SPR_SRR1); |
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tcg_gen_concat_tl_i64(t8, lo, hi); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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gen_get_xer(ctx, hi); |
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tcg_gen_mov_tl(lo, cpu_ctr); |
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tcg_gen_concat_tl_i64(t8, lo, hi); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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for (i = 0; i < sizeof(vd_list); i++) { |
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int vd = vd_list[i]; |
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tcg_gen_concat_tl_i64(t8, cpu_gpr[VDR_PAIR_REG(vd)], cpu_gpr[vd]); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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} |
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gen_load_spr(lo, SPR_SPRG0); |
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tcg_gen_extu_i32_tl(hi, cpu_crf[0]); |
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tcg_gen_shli_tl(hi, hi, 28); |
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tcg_gen_concat_tl_i64(t8, lo, hi); |
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tcg_gen_addi_tl(EA, EA, -8); |
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tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
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tcg_gen_addi_tl(EA, cpu_gpr[a->ra], a->si * 8); |
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tcg_gen_qemu_st_tl(cpu_gpr[a->rt], EA, ctx->mem_idx, DEF_MEMOP(MO_32) | |
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MO_ALIGN); |
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tcg_gen_mov_tl(cpu_gpr[a->ra], EA); |
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return true; |
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} |
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static bool trans_STSKU(DisasContext *ctx, arg_STSKU *a) |
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{ |
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int64_t n; |
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TCGv base, EA; |
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TCGv lo, hi; |
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TCGv_i64 t8; |
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if (unlikely(!is_ppe(ctx))) { |
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return false; |
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} |
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|
|||
CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
|||
CHECK_PPE_GPR(ctx, a->rt); |
|||
|
|||
if (unlikely((a->rt != a->ra) || (a->ra == 0) || !(a->si & PPC_BIT(0)))) { |
|||
gen_invalid(ctx); |
|||
return true; |
|||
} |
|||
|
|||
EA = tcg_temp_new(); |
|||
base = tcg_temp_new(); |
|||
gen_addr_register(ctx, base); |
|||
tcg_gen_addi_tl(EA, base, 4); |
|||
tcg_gen_qemu_st_tl(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_ALIGN); |
|||
|
|||
gen_store_spr(SPR_PPE42_EDR, base); |
|||
|
|||
n = ~(a->si); |
|||
|
|||
t8 = tcg_temp_new_i64(); |
|||
if (n > 0) { |
|||
hi = cpu_gpr[30]; |
|||
lo = cpu_gpr[31]; |
|||
tcg_gen_concat_tl_i64(t8, lo, hi); |
|||
tcg_gen_addi_tl(EA, base, -8); |
|||
tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
|||
} |
|||
if (n > 1) { |
|||
hi = cpu_gpr[28]; |
|||
lo = cpu_gpr[29]; |
|||
tcg_gen_concat_tl_i64(t8, lo, hi); |
|||
tcg_gen_addi_tl(EA, base, -16); |
|||
tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); |
|||
} |
|||
|
|||
tcg_gen_addi_tl(EA, base, a->si * 8); |
|||
tcg_gen_qemu_st_tl(cpu_gpr[a->rt], EA, ctx->mem_idx, DEF_MEMOP(MO_32) | |
|||
MO_ALIGN); |
|||
tcg_gen_mov_tl(cpu_gpr[a->ra], EA); |
|||
return true; |
|||
} |
|||
|
|||
static bool do_ppe_ldst(DisasContext *ctx, int rt, int ra, TCGv disp, |
|||
bool update, bool store) |
|||
{ |
|||
TCGv ea; |
|||
int rt_lo; |
|||
TCGv_i64 t8; |
|||
|
|||
CHECK_VDR(ctx, rt); |
|||
CHECK_PPE_GPR(ctx, ra); |
|||
rt_lo = VDR_PAIR_REG(rt); |
|||
if (update && (ra == 0 || (!store && ((ra == rt) || (ra == rt_lo))))) { |
|||
gen_invalid(ctx); |
|||
return true; |
|||
} |
|||
gen_set_access_type(ctx, ACCESS_INT); |
|||
|
|||
ea = do_ea_calc(ctx, ra, disp); |
|||
t8 = tcg_temp_new_i64(); |
|||
if (store) { |
|||
tcg_gen_concat_tl_i64(t8, cpu_gpr[rt_lo], cpu_gpr[rt]); |
|||
tcg_gen_qemu_st_i64(t8, ea, ctx->mem_idx, DEF_MEMOP(MO_64)); |
|||
} else { |
|||
tcg_gen_qemu_ld_i64(t8, ea, ctx->mem_idx, DEF_MEMOP(MO_64)); |
|||
tcg_gen_extr_i64_tl(cpu_gpr[rt_lo], cpu_gpr[rt], t8); |
|||
} |
|||
if (update) { |
|||
tcg_gen_mov_tl(cpu_gpr[ra], ea); |
|||
} |
|||
return true; |
|||
} |
|||
|
|||
static bool do_ppe_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store) |
|||
{ |
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
return do_ppe_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, |
|||
store); |
|||
} |
|||
|
|||
static bool do_ppe_ldst_X(DisasContext *ctx, arg_X *a, bool store) |
|||
{ |
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
CHECK_PPE_GPR(ctx, a->rb); |
|||
return do_ppe_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], false, store); |
|||
} |
|||
|
|||
TRANS(LVD, do_ppe_ldst_D, false, false) |
|||
TRANS(LVDU, do_ppe_ldst_D, true, false) |
|||
TRANS(STVD, do_ppe_ldst_D, false, true) |
|||
TRANS(STVDU, do_ppe_ldst_D, true, true) |
|||
TRANS(LVDX, do_ppe_ldst_X, false) |
|||
TRANS(STVDX, do_ppe_ldst_X, true) |
|||
|
|||
|
|||
static bool do_fcb(DisasContext *ctx, TCGv ra_val, TCGv rb_val, int bix, |
|||
int32_t bdx, bool s, bool px, bool lk) |
|||
{ |
|||
TCGCond cond; |
|||
uint32_t mask; |
|||
TCGLabel *no_branch; |
|||
target_ulong dest; |
|||
|
|||
/* Update CR0 */ |
|||
gen_op_cmp32(ra_val, rb_val, s, 0); |
|||
|
|||
if (lk) { |
|||
gen_setlr(ctx, ctx->base.pc_next); |
|||
} |
|||
|
|||
|
|||
mask = PPC_BIT32(28 + bix); |
|||
cond = (px) ? TCG_COND_TSTEQ : TCG_COND_TSTNE; |
|||
no_branch = gen_new_label(); |
|||
dest = ctx->cia + bdx; |
|||
|
|||
/* Do the branch if CR0[bix] == PX */ |
|||
tcg_gen_brcondi_i32(cond, cpu_crf[0], mask, no_branch); |
|||
gen_goto_tb(ctx, 0, dest); |
|||
gen_set_label(no_branch); |
|||
gen_goto_tb(ctx, 1, ctx->base.pc_next); |
|||
ctx->base.is_jmp = DISAS_NORETURN; |
|||
return true; |
|||
} |
|||
|
|||
static bool do_cmp_branch(DisasContext *ctx, arg_FCB_bix *a, bool s, |
|||
bool rb_is_gpr) |
|||
{ |
|||
TCGv old_ra; |
|||
TCGv rb_val; |
|||
|
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
CHECK_PPE_GPR(ctx, a->ra); |
|||
if (rb_is_gpr) { |
|||
CHECK_PPE_GPR(ctx, a->rb); |
|||
rb_val = cpu_gpr[a->rb]; |
|||
} else { |
|||
rb_val = tcg_constant_tl(a->rb); |
|||
} |
|||
if (a->bix == 3) { |
|||
old_ra = tcg_temp_new(); |
|||
tcg_gen_mov_tl(old_ra, cpu_gpr[a->ra]); |
|||
tcg_gen_sub_tl(cpu_gpr[a->ra], cpu_gpr[a->ra], rb_val); |
|||
return do_fcb(ctx, old_ra, rb_val, 2, |
|||
a->bdx, s, a->px, a->lk); |
|||
} else { |
|||
return do_fcb(ctx, cpu_gpr[a->ra], rb_val, a->bix, |
|||
a->bdx, s, a->px, a->lk); |
|||
} |
|||
} |
|||
|
|||
TRANS(CMPWBC, do_cmp_branch, true, true) |
|||
TRANS(CMPLWBC, do_cmp_branch, false, true) |
|||
TRANS(CMPWIBC, do_cmp_branch, true, false) |
|||
|
|||
static bool do_mask_branch(DisasContext *ctx, arg_FCB * a, bool invert, |
|||
bool update, bool rb_is_gpr) |
|||
{ |
|||
TCGv r; |
|||
TCGv mask, shift; |
|||
|
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
CHECK_PPE_GPR(ctx, a->ra); |
|||
if (rb_is_gpr) { |
|||
CHECK_PPE_GPR(ctx, a->rb); |
|||
mask = tcg_temp_new(); |
|||
shift = tcg_temp_new(); |
|||
tcg_gen_andi_tl(shift, cpu_gpr[a->rb], 0x1f); |
|||
tcg_gen_shr_tl(mask, tcg_constant_tl(0x80000000), shift); |
|||
} else { |
|||
mask = tcg_constant_tl(PPC_BIT32(a->rb)); |
|||
} |
|||
if (invert) { |
|||
tcg_gen_not_tl(mask, mask); |
|||
} |
|||
|
|||
/* apply mask to ra */ |
|||
r = tcg_temp_new(); |
|||
tcg_gen_and_tl(r, cpu_gpr[a->ra], mask); |
|||
if (update) { |
|||
tcg_gen_mov_tl(cpu_gpr[a->ra], r); |
|||
} |
|||
return do_fcb(ctx, r, tcg_constant_tl(0), 2, |
|||
a->bdx, false, a->px, a->lk); |
|||
} |
|||
|
|||
TRANS(BNBWI, do_mask_branch, false, false, false) |
|||
TRANS(BNBW, do_mask_branch, false, false, true) |
|||
TRANS(CLRBWIBC, do_mask_branch, true, true, false) |
|||
TRANS(CLRBWBC, do_mask_branch, true, true, true) |
|||
|
|||
static void gen_set_Rc0_i64(DisasContext *ctx, TCGv_i64 reg) |
|||
{ |
|||
TCGv_i64 t0 = tcg_temp_new_i64(); |
|||
TCGv_i64 t1 = tcg_temp_new_i64(); |
|||
TCGv_i32 t = tcg_temp_new_i32(); |
|||
|
|||
tcg_gen_movi_i64(t0, CRF_EQ); |
|||
tcg_gen_movi_i64(t1, CRF_LT); |
|||
tcg_gen_movcond_i64(TCG_COND_LT, t0, reg, tcg_constant_i64(0), t1, t0); |
|||
tcg_gen_movi_i64(t1, CRF_GT); |
|||
tcg_gen_movcond_i64(TCG_COND_GT, t0, reg, tcg_constant_i64(0), t1, t0); |
|||
tcg_gen_extrl_i64_i32(t, t0); |
|||
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
|||
tcg_gen_or_i32(cpu_crf[0], cpu_crf[0], t); |
|||
} |
|||
|
|||
static bool do_shift64(DisasContext *ctx, arg_X_rc *a, bool left) |
|||
{ |
|||
int rt_lo, ra_lo; |
|||
TCGv_i64 t0, t8; |
|||
|
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
|||
CHECK_VDR(ctx, a->rt); |
|||
CHECK_VDR(ctx, a->ra); |
|||
CHECK_PPE_GPR(ctx, a->rb); |
|||
rt_lo = VDR_PAIR_REG(a->rt); |
|||
ra_lo = VDR_PAIR_REG(a->ra); |
|||
t8 = tcg_temp_new_i64(); |
|||
|
|||
/* AND rt with a mask that is 0 when rb >= 0x40 */ |
|||
t0 = tcg_temp_new_i64(); |
|||
tcg_gen_extu_tl_i64(t0, cpu_gpr[a->rb]); |
|||
tcg_gen_shli_i64(t0, t0, 0x39); |
|||
tcg_gen_sari_i64(t0, t0, 0x3f); |
|||
|
|||
/* form 64bit value from two 32bit regs */ |
|||
tcg_gen_concat_tl_i64(t8, cpu_gpr[rt_lo], cpu_gpr[a->rt]); |
|||
|
|||
/* apply mask */ |
|||
tcg_gen_andc_i64(t8, t8, t0); |
|||
|
|||
/* do the shift */ |
|||
tcg_gen_extu_tl_i64(t0, cpu_gpr[a->rb]); |
|||
tcg_gen_andi_i64(t0, t0, 0x3f); |
|||
if (left) { |
|||
tcg_gen_shl_i64(t8, t8, t0); |
|||
} else { |
|||
tcg_gen_shr_i64(t8, t8, t0); |
|||
} |
|||
|
|||
/* split the 64bit word back into two 32bit regs */ |
|||
tcg_gen_extr_i64_tl(cpu_gpr[ra_lo], cpu_gpr[a->ra], t8); |
|||
|
|||
/* update CR0 if requested */ |
|||
if (unlikely(a->rc != 0)) { |
|||
gen_set_Rc0_i64(ctx, t8); |
|||
} |
|||
return true; |
|||
} |
|||
|
|||
TRANS(SRVD, do_shift64, false) |
|||
TRANS(SLVD, do_shift64, true) |
|||
|
|||
static bool trans_DCBQ(DisasContext *ctx, arg_DCBQ * a) |
|||
{ |
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
|
|||
CHECK_PPE_GPR(ctx, a->rt); |
|||
CHECK_PPE_GPR(ctx, a->ra); |
|||
CHECK_PPE_GPR(ctx, a->rb); |
|||
|
|||
/* No cache exists, so just set RT to 0 */ |
|||
tcg_gen_movi_tl(cpu_gpr[a->rt], 0); |
|||
return true; |
|||
} |
|||
|
|||
static bool trans_RLDIMI(DisasContext *ctx, arg_RLDIMI *a) |
|||
{ |
|||
TCGv_i64 t_rs, t_ra; |
|||
int ra_lo, rs_lo; |
|||
uint32_t sh = a->sh; |
|||
uint32_t mb = a->mb; |
|||
uint32_t me = 63 - sh; |
|||
|
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
|||
CHECK_VDR(ctx, a->rs); |
|||
CHECK_VDR(ctx, a->ra); |
|||
|
|||
rs_lo = VDR_PAIR_REG(a->rs); |
|||
ra_lo = VDR_PAIR_REG(a->ra); |
|||
|
|||
t_rs = tcg_temp_new_i64(); |
|||
t_ra = tcg_temp_new_i64(); |
|||
|
|||
tcg_gen_concat_tl_i64(t_rs, cpu_gpr[rs_lo], cpu_gpr[a->rs]); |
|||
tcg_gen_concat_tl_i64(t_ra, cpu_gpr[ra_lo], cpu_gpr[a->ra]); |
|||
|
|||
if (mb <= me) { |
|||
tcg_gen_deposit_i64(t_ra, t_ra, t_rs, sh, me - mb + 1); |
|||
} else { |
|||
uint64_t mask = mask_u64(mb, me); |
|||
TCGv_i64 t1 = tcg_temp_new_i64(); |
|||
|
|||
tcg_gen_rotli_i64(t1, t_rs, sh); |
|||
tcg_gen_andi_i64(t1, t1, mask); |
|||
tcg_gen_andi_i64(t_ra, t_ra, ~mask); |
|||
tcg_gen_or_i64(t_ra, t_ra, t1); |
|||
} |
|||
|
|||
tcg_gen_extr_i64_tl(cpu_gpr[ra_lo], cpu_gpr[a->ra], t_ra); |
|||
|
|||
if (unlikely(a->rc != 0)) { |
|||
gen_set_Rc0_i64(ctx, t_ra); |
|||
} |
|||
return true; |
|||
} |
|||
|
|||
|
|||
static bool gen_rldinm_i64(DisasContext *ctx, arg_MD *a, int mb, int me, int sh) |
|||
{ |
|||
int len = me - mb + 1; |
|||
int rsh = (64 - sh) & 63; |
|||
int ra_lo, rs_lo; |
|||
TCGv_i64 t8; |
|||
|
|||
if (unlikely(!is_ppe(ctx))) { |
|||
return false; |
|||
} |
|||
CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); |
|||
CHECK_VDR(ctx, a->rs); |
|||
CHECK_VDR(ctx, a->ra); |
|||
|
|||
rs_lo = VDR_PAIR_REG(a->rs); |
|||
ra_lo = VDR_PAIR_REG(a->ra); |
|||
t8 = tcg_temp_new_i64(); |
|||
tcg_gen_concat_tl_i64(t8, cpu_gpr[rs_lo], cpu_gpr[a->rs]); |
|||
if (sh != 0 && len > 0 && me == (63 - sh)) { |
|||
tcg_gen_deposit_z_i64(t8, t8, sh, len); |
|||
} else if (me == 63 && rsh + len <= 64) { |
|||
tcg_gen_extract_i64(t8, t8, rsh, len); |
|||
} else { |
|||
tcg_gen_rotli_i64(t8, t8, sh); |
|||
tcg_gen_andi_i64(t8, t8, mask_u64(mb, me)); |
|||
} |
|||
tcg_gen_extr_i64_tl(cpu_gpr[ra_lo], cpu_gpr[a->ra], t8); |
|||
if (unlikely(a->rc != 0)) { |
|||
gen_set_Rc0_i64(ctx, t8); |
|||
} |
|||
return true; |
|||
} |
|||
|
|||
TRANS(RLDICL, gen_rldinm_i64, a->mb, 63, a->sh) |
|||
TRANS(RLDICR, gen_rldinm_i64, 0, a->mb, a->sh) |
|||
@ -0,0 +1,79 @@ |
|||
#!/usr/bin/env python3 |
|||
# |
|||
# Functional tests for the IBM PPE42 processor |
|||
# |
|||
# Copyright (c) 2025, IBM Corporation |
|||
# |
|||
# SPDX-License-Identifier: GPL-2.0-or-later |
|||
|
|||
from qemu_test import QemuSystemTest, Asset |
|||
import asyncio |
|||
|
|||
class Ppe42Machine(QemuSystemTest): |
|||
|
|||
timeout = 90 |
|||
poll_period = 1.0 |
|||
|
|||
ASSET_PPE42_TEST_IMAGE = Asset( |
|||
('https://github.com/milesg-github/ppe42-tests/raw/refs/heads/main/' |
|||
'images/ppe42-test.out'), |
|||
'03c1ac0fb7f6c025102a02776a93b35101dae7c14b75e4eab36a337e39042ea8') |
|||
|
|||
def _test_completed(self): |
|||
self.log.info("Checking for test completion...") |
|||
try: |
|||
output = self.vm.cmd('human-monitor-command', |
|||
command_line='info registers') |
|||
except Exception as err: |
|||
self.log.debug(f"'info registers' cmd failed due to {err=}," |
|||
" {type(err)=}") |
|||
raise |
|||
|
|||
self.log.info(output) |
|||
if "NIP fff80200" in output: |
|||
self.log.info("<test completed>") |
|||
return True |
|||
else: |
|||
self.log.info("<test not completed>") |
|||
return False |
|||
|
|||
def _wait_pass_fail(self, timeout): |
|||
while not self._test_completed(): |
|||
if timeout >= self.poll_period: |
|||
timeout = timeout - self.poll_period |
|||
self.log.info(f"Waiting {self.poll_period} seconds for test" |
|||
" to complete...") |
|||
e = None |
|||
try: |
|||
e = self.vm.event_wait('STOP', self.poll_period) |
|||
|
|||
except asyncio.TimeoutError: |
|||
self.log.info("Poll period ended.") |
|||
pass |
|||
|
|||
except Exception as err: |
|||
self.log.debug(f"event_wait() failed due to {err=}," |
|||
" {type(err)=}") |
|||
raise |
|||
|
|||
if e != None: |
|||
self.log.debug(f"Execution stopped: {e}") |
|||
self.log.debug("Exiting due to test failure") |
|||
self.fail("Failure detected!") |
|||
break |
|||
else: |
|||
self.fail("Timed out waiting for test completion.") |
|||
|
|||
def test_ppe42_instructions(self): |
|||
self.set_machine('ppe42_machine') |
|||
self.require_accelerator("tcg") |
|||
image_path = self.ASSET_PPE42_TEST_IMAGE.fetch() |
|||
self.vm.add_args('-nographic') |
|||
self.vm.add_args('-device', f'loader,file={image_path}') |
|||
self.vm.add_args('-device', 'loader,addr=0xfff80040,cpu-num=0') |
|||
self.vm.add_args('-action', 'panic=pause') |
|||
self.vm.launch() |
|||
self._wait_pass_fail(self.timeout) |
|||
|
|||
if __name__ == '__main__': |
|||
QemuSystemTest.main() |
|||
Loading…
Reference in new issue