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@ -180,6 +180,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) |
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* tci_args_<arguments> |
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* where arguments is a sequence of |
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* |
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* c = condition (TCGCond) |
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* r = register |
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* s = signed ldst offset |
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*/ |
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@ -207,6 +208,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, |
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*i2 = tci_read_s32(tb_ptr); |
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} |
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static void tci_args_rrrc(const uint8_t **tb_ptr, |
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TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) |
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{ |
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*r0 = tci_read_r(tb_ptr); |
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*r1 = tci_read_r(tb_ptr); |
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*r2 = tci_read_r(tb_ptr); |
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*c3 = tci_read_b(tb_ptr); |
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} |
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static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) |
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{ |
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bool result = false; |
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@ -413,11 +423,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, |
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tb_ptr = (uint8_t *)label; |
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continue; |
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case INDEX_op_setcond_i32: |
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t0 = *tb_ptr++; |
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t1 = tci_read_rval(regs, &tb_ptr); |
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t2 = tci_read_rval(regs, &tb_ptr); |
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condition = *tb_ptr++; |
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tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); |
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tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); |
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regs[r0] = tci_compare32(regs[r1], regs[r2], condition); |
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break; |
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#if TCG_TARGET_REG_BITS == 32 |
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case INDEX_op_setcond2_i32: |
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@ -429,11 +436,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, |
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break; |
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#elif TCG_TARGET_REG_BITS == 64 |
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case INDEX_op_setcond_i64: |
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t0 = *tb_ptr++; |
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t1 = tci_read_rval(regs, &tb_ptr); |
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t2 = tci_read_rval(regs, &tb_ptr); |
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condition = *tb_ptr++; |
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tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); |
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tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); |
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regs[r0] = tci_compare64(regs[r1], regs[r2], condition); |
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break; |
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#endif |
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CASE_32_64(mov) |
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