Browse Source
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162stable-0.10
pbrook
19 years ago
224 changed files with 2416 additions and 1842 deletions
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#ifndef CONSOLE_H |
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#define CONSOLE_H |
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#include "qemu-char.h" |
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/* keyboard/mouse support */ |
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#define MOUSE_EVENT_LBUTTON 0x01 |
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#define MOUSE_EVENT_RBUTTON 0x02 |
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#define MOUSE_EVENT_MBUTTON 0x04 |
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typedef void QEMUPutKBDEvent(void *opaque, int keycode); |
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); |
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typedef struct QEMUPutMouseEntry { |
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QEMUPutMouseEvent *qemu_put_mouse_event; |
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void *qemu_put_mouse_event_opaque; |
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int qemu_put_mouse_event_absolute; |
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char *qemu_put_mouse_event_name; |
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/* used internally by qemu for handling mice */ |
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struct QEMUPutMouseEntry *next; |
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} QEMUPutMouseEntry; |
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
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void *opaque, int absolute, |
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const char *name); |
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry); |
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void kbd_put_keycode(int keycode); |
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); |
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int kbd_mouse_is_absolute(void); |
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void do_info_mice(void); |
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void do_mouse_set(int index); |
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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constants) */ |
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100) |
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#define QEMU_KEY_BACKSPACE 0x007f |
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#define QEMU_KEY_UP QEMU_KEY_ESC1('A') |
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#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') |
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#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') |
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#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') |
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#define QEMU_KEY_HOME QEMU_KEY_ESC1(1) |
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#define QEMU_KEY_END QEMU_KEY_ESC1(4) |
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#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) |
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#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) |
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#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) |
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#define QEMU_KEY_CTRL_UP 0xe400 |
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#define QEMU_KEY_CTRL_DOWN 0xe401 |
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#define QEMU_KEY_CTRL_LEFT 0xe402 |
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#define QEMU_KEY_CTRL_RIGHT 0xe403 |
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#define QEMU_KEY_CTRL_HOME 0xe404 |
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#define QEMU_KEY_CTRL_END 0xe405 |
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#define QEMU_KEY_CTRL_PAGEUP 0xe406 |
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#define QEMU_KEY_CTRL_PAGEDOWN 0xe407 |
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void kbd_put_keysym(int keysym); |
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/* consoles */ |
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struct DisplayState { |
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uint8_t *data; |
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int linesize; |
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int depth; |
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int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
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int width; |
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int height; |
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void *opaque; |
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struct QEMUTimer *gui_timer; |
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void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
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void (*dpy_resize)(struct DisplayState *s, int w, int h); |
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void (*dpy_refresh)(struct DisplayState *s); |
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void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
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int dst_x, int dst_y, int w, int h); |
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void (*dpy_fill)(struct DisplayState *s, int x, int y, |
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int w, int h, uint32_t c); |
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void (*mouse_set)(int x, int y, int on); |
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void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, |
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uint8_t *image, uint8_t *mask); |
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}; |
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static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) |
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{ |
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s->dpy_update(s, x, y, w, h); |
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} |
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static inline void dpy_resize(DisplayState *s, int w, int h) |
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{ |
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s->dpy_resize(s, w, h); |
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} |
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typedef void (*vga_hw_update_ptr)(void *); |
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typedef void (*vga_hw_invalidate_ptr)(void *); |
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); |
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, |
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vga_hw_invalidate_ptr invalidate, |
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vga_hw_screen_dump_ptr screen_dump, |
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void *opaque); |
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void vga_hw_update(void); |
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void vga_hw_invalidate(void); |
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void vga_hw_screen_dump(const char *filename); |
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int is_graphic_console(void); |
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CharDriverState *text_console_init(DisplayState *ds, const char *p); |
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void console_select(unsigned int index); |
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void console_color_init(DisplayState *ds); |
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/* sdl.c */ |
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void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
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/* cocoa.m */ |
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void cocoa_display_init(DisplayState *ds, int full_screen); |
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/* vnc.c */ |
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void vnc_display_init(DisplayState *ds); |
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void vnc_display_close(DisplayState *ds); |
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int vnc_display_open(DisplayState *ds, const char *display); |
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int vnc_display_password(DisplayState *ds, const char *password); |
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void do_info_vnc(void); |
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/* x_keymap.c */ |
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extern uint8_t _translate_keycode(const int key); |
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/* FIXME: term_printf et al should probably go elsewhere so everything
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does not need to include console.h */ |
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/* monitor.c */ |
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void monitor_init(CharDriverState *hd, int show_banner); |
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void term_puts(const char *str); |
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void term_vprintf(const char *fmt, va_list ap); |
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void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
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void term_print_filename(const char *filename); |
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void term_flush(void); |
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void term_print_help(void); |
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void monitor_readline(const char *prompt, int is_password, |
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char *buf, int buf_size); |
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/* readline.c */ |
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typedef void ReadLineFunc(void *opaque, const char *str); |
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extern int completion_index; |
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void add_completion(const char *str); |
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void readline_handle_byte(int ch); |
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void readline_find_completion(const char *cmdline); |
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const char *readline_get_history(unsigned int index); |
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void readline_start(const char *prompt, int is_password, |
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ReadLineFunc *readline_func, void *opaque); |
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#endif |
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@ -0,0 +1,33 @@ |
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/*
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* Misc ARM declarations |
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* |
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* Copyright (c) 2006 CodeSourcery. |
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* Written by Paul Brook |
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* |
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* This code is licenced under the LGPL. |
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* |
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*/ |
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#ifndef ARM_MISC_H |
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#define ARM_MISC_H 1 |
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/* The CPU is also modeled as an interrupt controller. */ |
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#define ARM_PIC_CPU_IRQ 0 |
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#define ARM_PIC_CPU_FIQ 1 |
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qemu_irq *arm_pic_init_cpu(CPUState *env); |
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/* armv7m.c */ |
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qemu_irq *armv7m_init(int flash_size, int sram_size, |
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const char *kernel_filename, const char *cpu_model); |
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/* arm_boot.c */ |
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void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
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const char *kernel_cmdline, const char *initrd_filename, |
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int board_id, target_phys_addr_t loader_start); |
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/* armv7m_nvic.c */ |
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qemu_irq *armv7m_nvic_init(CPUState *env); |
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#endif /* !ARM_MISC_H */ |
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@ -1,23 +0,0 @@ |
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/*
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* Generic ARM Programmable Interrupt Controller support. |
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* |
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* Copyright (c) 2006 CodeSourcery. |
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* Written by Paul Brook |
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* |
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* This code is licenced under the LGPL. |
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* |
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* Arm hardware uses a wide variety of interrupt handling hardware. |
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* This provides a generic framework for connecting interrupt sources and |
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* inputs. |
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*/ |
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#ifndef ARM_INTERRUPT_H |
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#define ARM_INTERRUPT_H 1 |
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/* The CPU is also modeled as an interrupt controller. */ |
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#define ARM_PIC_CPU_IRQ 0 |
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#define ARM_PIC_CPU_FIQ 1 |
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qemu_irq *arm_pic_init_cpu(CPUState *env); |
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#endif /* !ARM_INTERRUPT_H */ |
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@ -0,0 +1,12 @@ |
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/* es1370.c */ |
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int es1370_init (PCIBus *bus, AudioState *s); |
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/* sb16.c */ |
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int SB16_init (AudioState *s, qemu_irq *pic); |
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/* adlib.c */ |
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int Adlib_init (AudioState *s, qemu_irq *pic); |
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/* gus.c */ |
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int GUS_init (AudioState *s, qemu_irq *pic); |
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@ -0,0 +1,94 @@ |
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/* Declarations for use by board files for creating devices. */ |
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#ifndef HW_BOARDS_H |
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#define HW_BOARDS_H |
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typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
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const char *boot_device, |
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DisplayState *ds, const char **fd_filename, int snapshot, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model); |
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typedef struct QEMUMachine { |
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const char *name; |
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const char *desc; |
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QEMUMachineInitFunc *init; |
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struct QEMUMachine *next; |
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} QEMUMachine; |
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int qemu_register_machine(QEMUMachine *m); |
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/* Axis ETRAX. */ |
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extern QEMUMachine bareetraxfs_machine; |
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/* pc.c */ |
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extern QEMUMachine pc_machine; |
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extern QEMUMachine isapc_machine; |
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/* ppc.c */ |
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extern QEMUMachine prep_machine; |
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extern QEMUMachine core99_machine; |
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extern QEMUMachine heathrow_machine; |
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extern QEMUMachine ref405ep_machine; |
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extern QEMUMachine taihu_machine; |
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/* mips_r4k.c */ |
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extern QEMUMachine mips_machine; |
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/* mips_malta.c */ |
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extern QEMUMachine mips_malta_machine; |
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/* mips_pica61.c */ |
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extern QEMUMachine mips_pica61_machine; |
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/* mips_mipssim.c */ |
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extern QEMUMachine mips_mipssim_machine; |
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/* shix.c */ |
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extern QEMUMachine shix_machine; |
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/* r2d.c */ |
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extern QEMUMachine r2d_machine; |
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/* sun4m.c */ |
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extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine; |
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/* sun4u.c */ |
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extern QEMUMachine sun4u_machine; |
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/* integratorcp.c */ |
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extern QEMUMachine integratorcp_machine; |
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/* versatilepb.c */ |
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extern QEMUMachine versatilepb_machine; |
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extern QEMUMachine versatileab_machine; |
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/* realview.c */ |
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extern QEMUMachine realview_machine; |
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/* spitz.c */ |
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extern QEMUMachine akitapda_machine; |
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extern QEMUMachine spitzpda_machine; |
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extern QEMUMachine borzoipda_machine; |
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extern QEMUMachine terrierpda_machine; |
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/* palm.c */ |
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extern QEMUMachine palmte_machine; |
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/* gumstix.c */ |
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extern QEMUMachine connex_machine; |
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/* stellaris.c */ |
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extern QEMUMachine lm3s811evb_machine; |
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extern QEMUMachine lm3s6965evb_machine; |
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/* an5206.c */ |
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extern QEMUMachine an5206_machine; |
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/* mcf5208.c */ |
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extern QEMUMachine mcf5208evb_machine; |
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/* dummy_m68k.c */ |
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extern QEMUMachine dummy_m68k_machine; |
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#endif |
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@ -0,0 +1,19 @@ |
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#ifndef QEMU_DEVICES_H |
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#define QEMU_DEVICES_H |
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/* Devices that have nowhere better to go. */ |
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/* smc91c111.c */ |
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void smc91c111_init(NICInfo *, uint32_t, qemu_irq); |
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/* ssd0323.c */ |
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int ssd0323_xfer_ssi(void *opaque, int data); |
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void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p); |
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/* ads7846.c */ |
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struct ads7846_state_s; |
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uint32_t ads7846_read(void *opaque); |
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void ads7846_write(void *opaque, uint32_t value); |
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struct ads7846_state_s *ads7846_init(qemu_irq penirq); |
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#endif |
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@ -0,0 +1,12 @@ |
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/* fdc.c */ |
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#define MAX_FD 2 |
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extern BlockDriverState *fd_table[MAX_FD]; |
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typedef struct fdctrl_t fdctrl_t; |
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fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
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target_phys_addr_t io_base, |
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BlockDriverState **fds); |
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fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, |
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BlockDriverState **fds); |
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int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); |
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@ -0,0 +1,40 @@ |
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/* NOR flash devices */ |
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typedef struct pflash_t pflash_t; |
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pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, |
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BlockDriverState *bs, |
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uint32_t sector_len, int nb_blocs, int width, |
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uint16_t id0, uint16_t id1, |
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uint16_t id2, uint16_t id3); |
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/* nand.c */ |
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struct nand_flash_s; |
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struct nand_flash_s *nand_init(int manf_id, int chip_id); |
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void nand_done(struct nand_flash_s *s); |
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void nand_setpins(struct nand_flash_s *s, |
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int cle, int ale, int ce, int wp, int gnd); |
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void nand_getpins(struct nand_flash_s *s, int *rb); |
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void nand_setio(struct nand_flash_s *s, uint8_t value); |
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uint8_t nand_getio(struct nand_flash_s *s); |
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#define NAND_MFR_TOSHIBA 0x98 |
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#define NAND_MFR_SAMSUNG 0xec |
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#define NAND_MFR_FUJITSU 0x04 |
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#define NAND_MFR_NATIONAL 0x8f |
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#define NAND_MFR_RENESAS 0x07 |
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#define NAND_MFR_STMICRO 0x20 |
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#define NAND_MFR_HYNIX 0xad |
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#define NAND_MFR_MICRON 0x2c |
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/* ecc.c */ |
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struct ecc_state_s { |
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uint8_t cp; /* Column parity */ |
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uint16_t lp[2]; /* Line parity */ |
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uint16_t count; |
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}; |
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uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample); |
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void ecc_reset(struct ecc_state_s *s); |
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void ecc_put(QEMUFile *f, struct ecc_state_s *s); |
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void ecc_get(QEMUFile *f, struct ecc_state_s *s); |
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@ -0,0 +1,99 @@ |
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/* Declarations for use by hardware emulation. */ |
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#ifndef QEMU_HW_H |
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#define QEMU_HW_H |
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#include "qemu-common.h" |
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#include "irq.h" |
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/* VM Load/Save */ |
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QEMUFile *qemu_fopen(const char *filename, const char *mode); |
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void qemu_fflush(QEMUFile *f); |
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void qemu_fclose(QEMUFile *f); |
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void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
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void qemu_put_byte(QEMUFile *f, int v); |
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void qemu_put_be16(QEMUFile *f, unsigned int v); |
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void qemu_put_be32(QEMUFile *f, unsigned int v); |
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void qemu_put_be64(QEMUFile *f, uint64_t v); |
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int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); |
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int qemu_get_byte(QEMUFile *f); |
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unsigned int qemu_get_be16(QEMUFile *f); |
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unsigned int qemu_get_be32(QEMUFile *f); |
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uint64_t qemu_get_be64(QEMUFile *f); |
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static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) |
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{ |
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qemu_put_be64(f, *pv); |
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} |
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static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) |
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{ |
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qemu_put_be32(f, *pv); |
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} |
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static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) |
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{ |
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qemu_put_be16(f, *pv); |
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} |
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static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) |
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{ |
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qemu_put_byte(f, *pv); |
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} |
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static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) |
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{ |
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*pv = qemu_get_be64(f); |
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} |
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static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) |
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{ |
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*pv = qemu_get_be32(f); |
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} |
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static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) |
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{ |
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*pv = qemu_get_be16(f); |
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} |
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static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) |
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{ |
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*pv = qemu_get_byte(f); |
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} |
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#ifdef NEED_CPU_H |
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#if TARGET_LONG_BITS == 64 |
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#define qemu_put_betl qemu_put_be64 |
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#define qemu_get_betl qemu_get_be64 |
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#define qemu_put_betls qemu_put_be64s |
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#define qemu_get_betls qemu_get_be64s |
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#else |
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#define qemu_put_betl qemu_put_be32 |
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#define qemu_get_betl qemu_get_be32 |
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#define qemu_put_betls qemu_put_be32s |
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#define qemu_get_betls qemu_get_be32s |
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#endif |
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#endif |
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int64_t qemu_ftell(QEMUFile *f); |
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int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence); |
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typedef void SaveStateHandler(QEMUFile *f, void *opaque); |
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typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); |
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int register_savevm(const char *idstr, |
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int instance_id, |
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int version_id, |
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SaveStateHandler *save_state, |
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LoadStateHandler *load_state, |
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void *opaque); |
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typedef void QEMUResetHandler(void *opaque); |
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|
|||
void qemu_register_reset(QEMUResetHandler *func, void *opaque); |
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|
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/* These should really be in isa.h, but are here to make pc.h happy. */ |
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typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); |
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typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); |
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|
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#endif |
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@ -0,0 +1,24 @@ |
|||
/* ISA bus */ |
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|
|||
extern target_phys_addr_t isa_mem_base; |
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|
|||
int register_ioport_read(int start, int length, int size, |
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IOPortReadFunc *func, void *opaque); |
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int register_ioport_write(int start, int length, int size, |
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IOPortWriteFunc *func, void *opaque); |
|||
void isa_unassign_ioport(int start, int length); |
|||
|
|||
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size); |
|||
|
|||
/* dma.c */ |
|||
int DMA_get_channel_mode (int nchan); |
|||
int DMA_read_memory (int nchan, void *buf, int pos, int size); |
|||
int DMA_write_memory (int nchan, void *buf, int pos, int size); |
|||
void DMA_hold_DREQ (int nchan); |
|||
void DMA_release_DREQ (int nchan); |
|||
void DMA_schedule(int nchan); |
|||
void DMA_run (void); |
|||
void DMA_init (int high_page_enable); |
|||
void DMA_register_channel (int nchan, |
|||
DMA_transfer_handler transfer_handler, |
|||
void *opaque); |
|||
@ -1,13 +0,0 @@ |
|||
#if !defined (__M48T59_H__) |
|||
#define __M48T59_H__ |
|||
|
|||
typedef struct m48t59_t m48t59_t; |
|||
|
|||
void m48t59_write (void *private, uint32_t addr, uint32_t val); |
|||
uint32_t m48t59_read (void *private, uint32_t addr); |
|||
void m48t59_toggle_lock (void *private, int lock); |
|||
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
|||
uint32_t io_base, uint16_t size, |
|||
int type); |
|||
|
|||
#endif /* !defined (__M48T59_H__) */ |
|||
@ -0,0 +1,21 @@ |
|||
#ifndef HW_MCF_H |
|||
#define HW_MCF_H |
|||
/* Motorola ColdFire device prototypes. */ |
|||
|
|||
/* mcf_uart.c */ |
|||
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr); |
|||
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); |
|||
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr); |
|||
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, |
|||
CharDriverState *chr); |
|||
|
|||
/* mcf_intc.c */ |
|||
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); |
|||
|
|||
/* mcf_fec.c */ |
|||
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq); |
|||
|
|||
/* mcf5206.c */ |
|||
qemu_irq *mcf5206_init(uint32_t base, CPUState *env); |
|||
|
|||
#endif |
|||
@ -0,0 +1,25 @@ |
|||
#ifndef HW_MIPS_H |
|||
#define HW_MIPS_H |
|||
/* Definitions for mips board emulation. */ |
|||
|
|||
/* gt64xxx.c */ |
|||
PCIBus *pci_gt64120_init(qemu_irq *pic); |
|||
|
|||
/* ds1225y.c */ |
|||
typedef struct ds1225y_t ds1225y_t; |
|||
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename); |
|||
|
|||
/* mipsnet.c */ |
|||
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd); |
|||
|
|||
/* jazz_led.c */ |
|||
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base); |
|||
|
|||
/* mips_int.c */ |
|||
extern void cpu_mips_irq_init_cpu(CPUState *env); |
|||
|
|||
/* mips_timer.c */ |
|||
extern void cpu_mips_clock_init(CPUState *); |
|||
extern void cpu_mips_irqctrl_init (void); |
|||
|
|||
#endif |
|||
@ -0,0 +1,41 @@ |
|||
#ifndef NVRAM_H |
|||
#define NVRAM_H |
|||
|
|||
/* NVRAM helpers */ |
|||
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr); |
|||
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val); |
|||
typedef struct nvram_t { |
|||
void *opaque; |
|||
nvram_read_t read_fn; |
|||
nvram_write_t write_fn; |
|||
} nvram_t; |
|||
|
|||
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value); |
|||
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr); |
|||
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value); |
|||
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr); |
|||
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value); |
|||
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr); |
|||
void NVRAM_set_string (nvram_t *nvram, uint32_t addr, |
|||
const unsigned char *str, uint32_t max); |
|||
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max); |
|||
void NVRAM_set_crc (nvram_t *nvram, uint32_t addr, |
|||
uint32_t start, uint32_t count); |
|||
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, |
|||
const unsigned char *arch, |
|||
uint32_t RAM_size, int boot_device, |
|||
uint32_t kernel_image, uint32_t kernel_size, |
|||
const char *cmdline, |
|||
uint32_t initrd_image, uint32_t initrd_size, |
|||
uint32_t NVRAM_image, |
|||
int width, int height, int depth); |
|||
typedef struct m48t59_t m48t59_t; |
|||
|
|||
void m48t59_write (void *private, uint32_t addr, uint32_t val); |
|||
uint32_t m48t59_read (void *private, uint32_t addr); |
|||
void m48t59_toggle_lock (void *private, int lock); |
|||
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
|||
uint32_t io_base, uint16_t size, |
|||
int type); |
|||
|
|||
#endif /* !NVRAM_H */ |
|||
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Reference in new issue