riscv
/
qemu
mirror of https://gitea.goldendeliverer.com/riscv/qemu.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

Introduce reset notifier order 

Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.

Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
stable-0.11
Jan Kiszka 17 years ago
committed by Anthony Liguori
parent
93102fd601
commit
8217606e6e
74 changed files with 109 additions and 105 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 2
      hw/ac97.c
  2. 2
      hw/acpi.c
  3. 2
      hw/adb.c
  4. 2
      hw/apic.c
  5. 2
      hw/arm_boot.c
  6. 2
      hw/axis_dev88.c
  7. 2
      hw/cirrus_vga.c
  8. 2
      hw/cs4231.c
  9. 2
      hw/cs4231a.c
  10. 2
      hw/cuda.c
  11. 2
      hw/dma.c
  12. 2
      hw/dp8393x.c
  13. 2
      hw/eccmemctl.c
  14. 2
      hw/eepro100.c
  15. 2
      hw/es1370.c
  16. 4
      hw/escc.c
  17. 2
      hw/esp.c
  18. 2
      hw/etraxfs.c
  19. 2
      hw/etraxfs_timer.c
  20. 2
      hw/fdc.c
  21. 2
      hw/fw_cfg.c
  22. 2
      hw/g364fb.c
  23. 2
      hw/grackle_pci.c
  24. 2
      hw/heathrow_pic.c
  25. 2
      hw/hpet.c
  26. 2
      hw/hw.h
  27. 2
      hw/i8254.c
  28. 2
      hw/i8259.c
  29. 8
      hw/ide.c
  30. 2
      hw/ioapic.c
  31. 2
      hw/iommu.c
  32. 2
      hw/lm832x.c
  33. 2
      hw/m48t59.c
  34. 2
      hw/mac_dbdma.c
  35. 2
      hw/mac_nvram.c
  36. 2
      hw/mips_jazz.c
  37. 4
      hw/mips_malta.c
  38. 2
      hw/mips_mipssim.c
  39. 2
      hw/mips_r4k.c
  40. 4
      hw/musicpal.c
  41. 2
      hw/nseries.c
  42. 2
      hw/omap1.c
  43. 2
      hw/omap2.c
  44. 4
      hw/openpic.c
  45. 4
      hw/parallel.c
  46. 4
      hw/pc.c
  47. 4
      hw/pckbd.c
  48. 2
      hw/pl181.c
  49. 4
      hw/ppc405_boards.c
  50. 24
      hw/ppc405_uc.c
  51. 6
      hw/ppc4xx_devs.c
  52. 2
      hw/ppc4xx_pci.c
  53. 2
      hw/ppc_newworld.c
  54. 2
      hw/ppc_oldworld.c
  55. 2
      hw/ppc_prep.c
  56. 4
      hw/ps2.c
  57. 2
      hw/rc4030.c
  58. 2
      hw/sbi.c
  59. 2
      hw/serial.c
  60. 2
      hw/slavio_intctl.c
  61. 2
      hw/slavio_misc.c
  62. 2
      hw/slavio_timer.c
  63. 2
      hw/sparc32_dma.c
  64. 2
      hw/sun4c_intctl.c
  65. 10
      hw/sun4m.c
  66. 2
      hw/sun4u.c
  67. 2
      hw/tcx.c
  68. 2
      hw/tsc2005.c
  69. 4
      hw/tsc210x.c
  70. 2
      hw/unin_pci.c
  71. 2
      hw/usb-ohci.c
  72. 2
      hw/vga.c
  73. 3
      hw/virtio.c
  74. 7
      vl.c

2
hw/ac97.c
View File

@ -1369,7 +1369,7 @@ int ac97_init (PCIBus *bus)
pci_register_io_region (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
pci_register_io_region (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);
qemu_register_reset (ac97_on_reset, s);
qemu_register_reset (ac97_on_reset, 0, s);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (s);
return 0;

2
hw/acpi.c
View File

@ -550,7 +550,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
s->smbus = i2c_init_bus();
s->irq = sci_irq;
qemu_register_reset(piix4_reset, s);
qemu_register_reset(piix4_reset, 0, s);
return s->smbus;
}

2
hw/adb.c
View File

@ -122,7 +122,7 @@ ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
d->devreq = devreq;
d->devreset = devreset;
d->opaque = opaque;
qemu_register_reset((QEMUResetHandler *)devreset, d);
qemu_register_reset((QEMUResetHandler *)devreset, 0, d);
d->devreset(d);
return d;
}

2
hw/apic.c
View File

@ -924,7 +924,7 @@ int apic_init(CPUState *env)
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
register_savevm("apic", s->id, 2, apic_save, apic_load, s);
qemu_register_reset(apic_reset, s);
qemu_register_reset(apic_reset, 0, s);
local_apics[s->id] = s;
return 0;

2
hw/arm_boot.c
View File

@ -203,7 +203,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
if (info->nb_cpus == 0)
info->nb_cpus = 1;
env->boot_info = info;
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
}
/* Assume that raw images are linux kernels, and ELF images are not. */

2
hw/axis_dev88.c
View File

@ -271,7 +271,7 @@ void axisdev88_init (ram_addr_t ram_size,
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
phys_ram = qemu_ram_alloc(ram_size);

2
hw/cirrus_vga.c
View File

@ -3228,7 +3228,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
s->vga.cursor_invalidate = cirrus_cursor_invalidate;
s->vga.cursor_draw_line = cirrus_cursor_draw_line;
qemu_register_reset(cirrus_reset, s);
qemu_register_reset(cirrus_reset, 0, s);
cirrus_reset(s);
register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
}

2
hw/cs4231.c
View File

@ -175,6 +175,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
register_savevm("cs4231", base, 1, cs_save, cs_load, s);
qemu_register_reset(cs_reset, s);
qemu_register_reset(cs_reset, 0, s);
cs_reset(s);
}

2
hw/cs4231a.c
View File

@ -656,7 +656,7 @@ int cs4231a_init (qemu_irq *pic)
DMA_register_channel (s->dma, cs_dma_read, s);
register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);
qemu_register_reset (cs_reset, s);
qemu_register_reset (cs_reset, 0, s);
cs_reset (s);
AUD_register_card ("cs4231a", &s->card);

2
hw/cuda.c
View File

@ -762,6 +762,6 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, s);
qemu_register_reset(cuda_reset, 0, s);
cuda_reset(s);
}

2
hw/dma.c
View File

@ -493,7 +493,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
register_ioport_read (base + ((i + 8) << dshift), 1, 1,
read_cont, d);
}
qemu_register_reset(dma_reset, d);
qemu_register_reset(dma_reset, 0, d);
dma_reset(d);
for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
d->regs[i].transfer_handler = dma_phony_handler;

2
hw/dp8393x.c
View File

@ -892,7 +892,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
nic_receive, nic_can_receive, nic_cleanup, s);
qemu_format_nic_info_str(s->vc, nd->macaddr);
qemu_register_reset(nic_reset, s);
qemu_register_reset(nic_reset, 0, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(0, dp8393x_read, dp8393x_write, s);

2
hw/eccmemctl.c
View File

@ -334,7 +334,7 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
ecc_io_memory);
}
register_savevm("ECC", base, 3, ecc_save, ecc_load, s);
qemu_register_reset(ecc_reset, s);
qemu_register_reset(ecc_reset, 0, s);
ecc_reset(s);
return s;
}

2
hw/eepro100.c
View File

@ -1771,7 +1771,7 @@ static void nic_init(PCIDevice *pci_dev, uint32_t device)
qemu_format_nic_info_str(s->vc, s->macaddr);
qemu_register_reset(nic_reset, s);
qemu_register_reset(nic_reset, 0, s);
register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
}

2
hw/es1370.c
View File

@ -1055,7 +1055,7 @@ int es1370_init (PCIBus *bus)
pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
qemu_register_reset (es1370_on_reset, s);
qemu_register_reset (es1370_on_reset, 0, s);
AUD_register_card ("es1370", &s->card);
es1370_reset (s);

4
hw/escc.c
View File

@ -758,7 +758,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
register_savevm("escc", base, 2, escc_save, escc_load, s);
else
register_savevm("escc", -1, 2, escc_save, escc_load, s);
qemu_register_reset(escc_reset, s);
qemu_register_reset(escc_reset, 0, s);
escc_reset(s);
return escc_io_memory;
}
@ -932,6 +932,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
"QEMU Sun Mouse");
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
register_savevm("slavio_serial_mouse", base, 2, escc_save, escc_load, s);
qemu_register_reset(escc_reset, s);
qemu_register_reset(escc_reset, 0, s);
escc_reset(s);
}

2
hw/esp.c
View File

@ -682,7 +682,7 @@ static void esp_init1(SysBusDevice *dev)
esp_reset(s);
register_savevm("esp", -1, 3, esp_save, esp_load, s);
qemu_register_reset(esp_reset, s);
qemu_register_reset(esp_reset, 0, s);
qdev_init_irq_sink(&dev->qdev, parent_esp_reset, 1);

2
hw/etraxfs.c
View File

@ -64,7 +64,7 @@ void bareetraxfs_init (ram_addr_t ram_size,
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
phys_ram = qemu_ram_alloc(ram_size);

2
hw/etraxfs_timer.c
View File

@ -327,7 +327,7 @@ static void etraxfs_timer_init(SysBusDevice *dev)
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
sysbus_init_mmio(dev, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, t);
qemu_register_reset(etraxfs_timer_reset, 0, t);
}
static void etraxfs_timer_register(void)

2
hw/fdc.c
View File

@ -1883,7 +1883,7 @@ static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
}
fdctrl_external_reset(fdctrl);
register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
qemu_register_reset(fdctrl_external_reset, fdctrl);
qemu_register_reset(fdctrl_external_reset, 0, fdctrl);
for (i = 0; i < MAX_FD; i++) {
fd_revalidate(&fdctrl->drives[i]);
}

2
hw/fw_cfg.c
View File

@ -281,7 +281,7 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
qemu_register_reset(fw_cfg_reset, s);
qemu_register_reset(fw_cfg_reset, 0, s);
fw_cfg_reset(s);
return s;

2
hw/g364fb.c
View File

@ -598,7 +598,7 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
s->vram = qemu_get_ram_ptr(s->vram_offset);
s->irq = irq;
qemu_register_reset(g364fb_reset, s);
qemu_register_reset(g364fb_reset, 0, s);
register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);
g364fb_reset(s);

2
hw/grackle_pci.c
View File

@ -176,7 +176,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
d->config[0x27] = 0x85;
#endif
register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
qemu_register_reset(pci_grackle_reset, d);
qemu_register_reset(pci_grackle_reset, 0, d);
pci_grackle_reset(d);
return s->bus;

2
hw/heathrow_pic.c
View File

@ -230,7 +230,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);
qemu_register_reset(heathrow_pic_reset, s);
qemu_register_reset(heathrow_pic_reset, 0, s);
heathrow_pic_reset(s);
return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
}

2
hw/hpet.c
View File

@ -580,7 +580,7 @@ void hpet_init(qemu_irq *irq) {
}
hpet_reset(s);
register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
qemu_register_reset(hpet_reset, s);
qemu_register_reset(hpet_reset, 0, s);
/* HPET Area */
iomemtype = cpu_register_io_memory(0, hpet_ram_read,
hpet_ram_write, s);

2
hw/hw.h
View File

@ -258,7 +258,7 @@ void unregister_savevm(const char *idstr, void *opaque);
typedef void QEMUResetHandler(void *opaque);
void qemu_register_reset(QEMUResetHandler *func, void *opaque);
void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque);
/* handler to set the boot_device for a specific type of QEMUMachine */
/* return 0 if success */

2
hw/i8254.c
View File

@ -497,7 +497,7 @@ PITState *pit_init(int base, qemu_irq irq)
register_savevm("i8254", base, 1, pit_save, pit_load, pit);
qemu_register_reset(pit_reset, pit);
qemu_register_reset(pit_reset, 0, pit);
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
register_ioport_read(base, 3, 1, pit_ioport_read, pit);

2
hw/i8259.c
View File

@ -508,7 +508,7 @@ static void pic_init1(int io_addr, int elcr_addr, PicState *s)
register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
}
register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
qemu_register_reset(pic_reset, s);
qemu_register_reset(pic_reset, 0, s);
}
void pic_info(Monitor *mon)

8
hw/ide.c
View File

@ -3330,7 +3330,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d);
qemu_register_reset(cmd646_reset, d);
qemu_register_reset(cmd646_reset, 0, d);
cmd646_reset(d);
}
@ -3373,7 +3373,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
qemu_register_reset(piix3_reset, d);
qemu_register_reset(piix3_reset, 0, d);
piix3_reset(d);
pci_register_io_region((PCIDevice *)d, 4, 0x10,
@ -3413,7 +3413,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
qemu_register_reset(piix3_reset, d);
qemu_register_reset(piix3_reset, 0, d);
piix3_reset(d);
pci_register_io_region((PCIDevice *)d, 4, 0x10,
@ -3754,7 +3754,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_write, d);
register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);
qemu_register_reset(pmac_ide_reset, d);
qemu_register_reset(pmac_ide_reset, 0, d);
pmac_ide_reset(d);
return pmac_ide_memory;

2
hw/ioapic.c
View File

@ -255,7 +255,7 @@ IOAPICState *ioapic_init(void)
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
qemu_register_reset(ioapic_reset, s);
qemu_register_reset(ioapic_reset, 0, s);
return s;
}

2
hw/iommu.c
View File

@ -380,7 +380,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
qemu_register_reset(iommu_reset, s);
qemu_register_reset(iommu_reset, 0, s);
iommu_reset(s);
return s;
}

2
hw/lm832x.c
View File

@ -501,7 +501,7 @@ static void lm8323_init(i2c_slave *i2c)
lm_kbd_reset(s);
qemu_register_reset((void *) lm_kbd_reset, s);
qemu_register_reset((void *) lm_kbd_reset, 0, s);
register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s);
}

2
hw/m48t59.c
View File

@ -641,7 +641,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
}
qemu_get_timedate(&s->alarm, 0);
qemu_register_reset(m48t59_reset, s);
qemu_register_reset(m48t59_reset, 0, s);
save_base = mem_base ? mem_base : io_base;
register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);

2
hw/mac_dbdma.c
View File

@ -839,7 +839,7 @@ void* DBDMA_init (int *dbdma_mem_index)
*dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, s);
qemu_register_reset(dbdma_reset, 0, s);
dbdma_reset(s);
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);

2
hw/mac_nvram.c
View File

@ -142,7 +142,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
*mem_index = s->mem_index;
register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
s);
qemu_register_reset(macio_nvram_reset, s);
qemu_register_reset(macio_nvram_reset, 0, s);
macio_nvram_reset(s);
return s;

2
hw/mips_jazz.c
View File

@ -146,7 +146,7 @@ void mips_jazz_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
ram_offset = qemu_ram_alloc(ram_size);

4
hw/mips_malta.c
View File

@ -447,7 +447,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);
qemu_register_reset(malta_fpga_reset, 0, s);
return s;
}
@ -792,7 +792,7 @@ void mips_malta_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {

2
hw/mips_mipssim.c
View File

@ -126,7 +126,7 @@ mips_mipssim_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
/* Allocate RAM. */
ram_offset = qemu_ram_alloc(ram_size);

2
hw/mips_r4k.c
View File

@ -171,7 +171,7 @@ void mips_r4k_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {

4
hw/musicpal.c
View File

@ -441,7 +441,7 @@ static i2c_interface *musicpal_audio_init(qemu_irq irq)
musicpal_audio_writefn, s);
cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
qemu_register_reset(musicpal_audio_reset, s);
qemu_register_reset(musicpal_audio_reset, 0, s);
return i2c;
}
@ -1046,7 +1046,7 @@ static void mv88w8618_pic_init(SysBusDevice *dev)
mv88w8618_pic_writefn, s);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
qemu_register_reset(mv88w8618_pic_reset, s);
qemu_register_reset(mv88w8618_pic_reset, 0, s);
}
/* PIT register offsets */

2
hw/nseries.c
View File

@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
binfo->initrd_filename = initrd_filename;
arm_load_kernel(s->cpu->env, binfo);
qemu_register_reset(n8x0_boot_init, s);
qemu_register_reset(n8x0_boot_init, 0, s);
n8x0_boot_init(s);
}

2
hw/omap1.c
View File

@ -4797,7 +4797,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_setup_dsp_mapping(omap15xx_dsp_mm);
omap_setup_mpui_io(s);
qemu_register_reset(omap1_mpu_reset, s);
qemu_register_reset(omap1_mpu_reset, 0, s);
return s;
}

2
hw/omap2.c
View File

@ -4868,7 +4868,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
* GPMC registers 6800a000 6800afff
*/
qemu_register_reset(omap2_mpu_reset, s);
qemu_register_reset(omap2_mpu_reset, 0, s);
return s;
}

4
hw/openpic.c
View File

@ -1249,7 +1249,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
opp->need_swap = 1;
register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, opp);
qemu_register_reset(openpic_reset, 0, opp);
opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset;
@ -1709,7 +1709,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
mpp->reset = mpic_reset;
register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
qemu_register_reset(mpic_reset, mpp);
qemu_register_reset(mpic_reset, 0, mpp);
mpp->reset(mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);

4
hw/parallel.c
View File

@ -448,7 +448,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
s->irq = irq;
s->chr = chr;
parallel_reset(s);
qemu_register_reset(parallel_reset, s);
qemu_register_reset(parallel_reset, 0, s);
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
@ -541,7 +541,7 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
s->chr = chr;
s->it_shift = it_shift;
parallel_reset(s);
qemu_register_reset(parallel_reset, s);
qemu_register_reset(parallel_reset, 0, s);
io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);

4
hw/pc.c
View File

@ -81,7 +81,7 @@ static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
cpu_physical_memory_read(addr, rrd->data, size);
rrd->addr = addr;
rrd->size = size;
qemu_register_reset(option_rom_reset, rrd);
qemu_register_reset(option_rom_reset, 0, rrd);
}
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
@ -875,7 +875,7 @@ static void pc_init1(ram_addr_t ram_size,
/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
}
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
if (pci_enabled) {
apic_init(env);
}

4
hw/pckbd.c
View File

@ -381,7 +381,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base)
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
qemu_register_reset(kbd_reset, s);
qemu_register_reset(kbd_reset, 0, s);
}
/* Memory mapped interface */
@ -438,5 +438,5 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
qemu_register_reset(kbd_reset, s);
qemu_register_reset(kbd_reset, 0, s);
}

2
hw/pl181.c
View File

@ -458,7 +458,7 @@ static void pl181_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq[1]);
bd = qdev_init_bdrv(&dev->qdev, IF_SD);
s->card = sd_init(bd, 0);
qemu_register_reset(pl181_reset, s);
qemu_register_reset(pl181_reset, 0, s);
pl181_reset(s);
/* ??? Save/restore. */
}

4
hw/ppc405_boards.c
View File

@ -165,7 +165,7 @@ static void ref405ep_fpga_init (uint32_t base)
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
ref405ep_fpga_reset(fpga);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
qemu_register_reset(&ref405ep_fpga_reset, 0, fpga);
}
static void ref405ep_init (ram_addr_t ram_size,
@ -483,7 +483,7 @@ static void taihu_cpld_init (uint32_t base)
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
taihu_cpld_reset(cpld);
qemu_register_reset(&taihu_cpld_reset, cpld);
qemu_register_reset(&taihu_cpld_reset, 0, cpld);
}
static void taihu_405ep_init(ram_addr_t ram_size,

24
hw/ppc405_uc.c
View File

@ -173,7 +173,7 @@ void ppc4xx_plb_init (CPUState *env)
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_plb_reset(plb);
qemu_register_reset(ppc4xx_plb_reset, plb);
qemu_register_reset(ppc4xx_plb_reset, 0, plb);
}
/*****************************************************************************/
@ -249,7 +249,7 @@ void ppc4xx_pob_init (CPUState *env)
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
qemu_register_reset(ppc4xx_pob_reset, 0, pob);
ppc4xx_pob_reset(env);
}
@ -386,7 +386,7 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x002,
opba_read, opba_write, opba);
qemu_register_reset(ppc4xx_opba_reset, opba);
qemu_register_reset(ppc4xx_opba_reset, 0, opba);
ppc4xx_opba_reset(opba);
}
@ -580,7 +580,7 @@ void ppc405_ebc_init (CPUState *env)
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
ebc_reset(ebc);
qemu_register_reset(&ebc_reset, ebc);
qemu_register_reset(&ebc_reset, 0, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
@ -672,7 +672,7 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
dma = qemu_mallocz(sizeof(ppc405_dma_t));
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
ppc405_dma_reset(dma);
qemu_register_reset(&ppc405_dma_reset, dma);
qemu_register_reset(&ppc405_dma_reset, 0, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT0,
@ -837,7 +837,7 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
gpio->base = offset;
ppc405_gpio_reset(gpio);
qemu_register_reset(&ppc405_gpio_reset, gpio);
qemu_register_reset(&ppc405_gpio_reset, 0, gpio);
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
@ -1028,7 +1028,7 @@ void ppc405_ocm_init (CPUState *env)
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
ocm->offset = qemu_ram_alloc(4096);
ocm_reset(ocm);
qemu_register_reset(&ocm_reset, ocm);
qemu_register_reset(&ocm_reset, 0, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
@ -1280,7 +1280,7 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x011,
i2c_read, i2c_write, i2c);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
qemu_register_reset(ppc4xx_i2c_reset, 0, i2c);
}
/*****************************************************************************/
@ -1562,7 +1562,7 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
gpt_read, gpt_write, gpt);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
qemu_register_reset(ppc4xx_gpt_reset, 0, gpt);
}
/*****************************************************************************/
@ -1787,7 +1787,7 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
ppc40x_mal_reset(mal);
qemu_register_reset(&ppc40x_mal_reset, mal);
qemu_register_reset(&ppc40x_mal_reset, 0, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
@ -2171,7 +2171,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
qemu_register_reset(ppc405cr_cpc_reset, cpc);
qemu_register_reset(ppc405cr_cpc_reset, 0, cpc);
ppc405cr_cpc_reset(cpc);
}
@ -2493,7 +2493,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
ppc405ep_cpc_reset(cpc);
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,

6
hw/ppc4xx_devs.c
View File

@ -60,7 +60,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
qemu_register_reset(&cpu_ppc_reset, env);
qemu_register_reset(&cpu_ppc_reset, 0, env);
return env;
}
@ -498,7 +498,7 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
ppc_dcr_register(env, dcr_base + i, uic,
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
qemu_register_reset(ppcuic_reset, 0, uic);
ppcuic_reset(uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
@ -834,7 +834,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
qemu_register_reset(&sdram_reset, 0, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,

2
hw/ppc4xx_pci.c
View File

@ -403,7 +403,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
qemu_register_reset(ppc4xx_pci_reset, controller);
qemu_register_reset(ppc4xx_pci_reset, 0, controller);
/* XXX load/save code not tested. */
register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,

2
hw/ppc_newworld.c
View File

@ -128,7 +128,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
#if 0
env->osi_call = vga_osi_call;
#endif
qemu_register_reset(&cpu_ppc_reset, env);
qemu_register_reset(&cpu_ppc_reset, 0, env);
envs[i] = env;
}

2
hw/ppc_oldworld.c
View File

@ -154,7 +154,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
env->osi_call = vga_osi_call;
qemu_register_reset(&cpu_ppc_reset, env);
qemu_register_reset(&cpu_ppc_reset, 0, env);
envs[i] = env;
}

2
hw/ppc_prep.c
View File

@ -573,7 +573,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
qemu_register_reset(&cpu_ppc_reset, env);
qemu_register_reset(&cpu_ppc_reset, 0, env);
envs[i] = env;
}

4
hw/ps2.c
View File

@ -593,7 +593,7 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg)
ps2_reset(&s->common);
register_savevm("ps2kbd", 0, 3, ps2_kbd_save, ps2_kbd_load, s);
qemu_add_kbd_event_handler(ps2_put_keycode, s);
qemu_register_reset(ps2_reset, &s->common);
qemu_register_reset(ps2_reset, 0, &s->common);
return s;
}
@ -606,6 +606,6 @@ void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg)
ps2_reset(&s->common);
register_savevm("ps2mouse", 0, 2, ps2_mouse_save, ps2_mouse_load, s);
qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse");
qemu_register_reset(ps2_reset, &s->common);
qemu_register_reset(ps2_reset, 0, &s->common);
return s;
}

2
hw/rc4030.c
View File

@ -810,7 +810,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
s->timer_irq = timer;
s->jazz_bus_irq = jazz_bus;
qemu_register_reset(rc4030_reset, s);
qemu_register_reset(rc4030_reset, 0, s);
register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
rc4030_reset(s);

2
hw/sbi.c
View File

@ -155,7 +155,7 @@ void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
qemu_register_reset(sbi_reset, s);
qemu_register_reset(sbi_reset, 0, s);
*irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
sbi_reset(s);

2
hw/serial.c
View File

@ -718,7 +718,7 @@ static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase,
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
qemu_register_reset(serial_reset, s);
qemu_register_reset(serial_reset, 0, s);
serial_reset(s);
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,

2
hw/slavio_intctl.c
View File

@ -407,7 +407,7 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
slavio_intctl_load, s);
qemu_register_reset(slavio_intctl_reset, s);
qemu_register_reset(slavio_intctl_reset, 0, s);
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);

2
hw/slavio_misc.c
View File

@ -501,7 +501,7 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
s);
qemu_register_reset(slavio_misc_reset, s);
qemu_register_reset(slavio_misc_reset, 0, s);
slavio_misc_reset(s);
return s;

2
hw/slavio_timer.c
View File

@ -391,7 +391,7 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
slavio_timer_io_memory);
register_savevm("slavio_timer", addr, 3, slavio_timer_save,
slavio_timer_load, s);
qemu_register_reset(slavio_timer_reset, s);
qemu_register_reset(slavio_timer_reset, 0, s);
slavio_timer_reset(s);
return s;

2
hw/sparc32_dma.c
View File

@ -256,7 +256,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
qemu_register_reset(dma_reset, s);
qemu_register_reset(dma_reset, 0, s);
*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
*reset = &s->dev_reset;

2
hw/sun4c_intctl.c
View File

@ -213,7 +213,7 @@ void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
sun4c_intctl_load, s);
qemu_register_reset(sun4c_intctl_reset, s);
qemu_register_reset(sun4c_intctl_reset, 0, s);
*irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
sun4c_intctl_reset(s);

10
hw/sun4m.c
View File

@ -418,9 +418,9 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
cpu_sparc_set_id(env, i);
envs[i] = env;
if (i == 0) {
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
} else {
qemu_register_reset(secondary_cpu_reset, env);
qemu_register_reset(secondary_cpu_reset, 0, env);
env->halted = 1;
}
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
@ -1201,9 +1201,9 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
cpu_sparc_set_id(env, i);
envs[i] = env;
if (i == 0) {
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
} else {
qemu_register_reset(secondary_cpu_reset, env);
qemu_register_reset(secondary_cpu_reset, 0, env);
env->halted = 1;
}
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
@ -1416,7 +1416,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
cpu_sparc_set_id(env, 0);
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, 0, env);
cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
env->prom_addr = hwdef->slavio_base;

2
hw/sun4u.c
View File

@ -374,7 +374,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
reset_info = qemu_mallocz(sizeof(ResetData));
reset_info->env = env;
reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
qemu_register_reset(main_cpu_reset, reset_info);
qemu_register_reset(main_cpu_reset, 0, reset_info);
main_cpu_reset(reset_info);
// Override warm reset address with cold start address
env->pc = hwdef->prom_addr + 0x20ULL;

2
hw/tcx.c
View File

@ -560,7 +560,7 @@ void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
dummy_memory);
register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
qemu_register_reset(tcx_reset, s);
qemu_register_reset(tcx_reset, 0, s);
tcx_reset(s);
qemu_console_resize(s->ds, width, height);
}

2
hw/tsc2005.c
View File

@ -548,7 +548,7 @@ void *tsc2005_init(qemu_irq pintdav)
qemu_add_mouse_event_handler(tsc2005_touchscreen_event, s, 1,
"QEMU TSC2005-driven Touchscreen");
qemu_register_reset((void *) tsc2005_reset, s);
qemu_register_reset((void *) tsc2005_reset, 0, s);
register_savevm("tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);
return s;

4
hw/tsc210x.c
View File

@ -1143,7 +1143,7 @@ uWireSlave *tsc2102_init(qemu_irq pint)
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
qemu_register_reset((void *) tsc210x_reset, 0, s);
register_savevm(s->name, -1, 0,
tsc210x_save, tsc210x_load, s);
@ -1194,7 +1194,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
qemu_register_reset((void *) tsc210x_reset, 0, s);
register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s);
return &s->chip;

2
hw/unin_pci.c
View File

@ -265,7 +265,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
d->config[0x34] = 0x00; // capabilities_pointer
#endif
register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
qemu_register_reset(pci_unin_reset, d);
qemu_register_reset(pci_unin_reset, 0, d);
pci_unin_reset(d);
return s->bus;

2
hw/usb-ohci.c
View File

@ -1695,7 +1695,7 @@ static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn,
}
ohci->async_td = 0;
qemu_register_reset(ohci_reset, ohci);
qemu_register_reset(ohci_reset, 0, ohci);
ohci_reset(ohci);
}

2
hw/vga.c
View File

@ -2306,7 +2306,7 @@ void vga_init(VGAState *s)
{
int vga_io_memory;
qemu_register_reset(vga_reset, s);
qemu_register_reset(vga_reset, 0, s);
register_savevm("vga", 0, 2, vga_save, vga_load, s);
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);

3
hw/virtio.c
View File

@ -636,7 +636,8 @@ VirtIODevice *virtio_common_init(const char *name, uint16_t device_id,
else
vdev->config = NULL;
qemu_register_reset(virtio_reset, vdev);
qemu_register_reset(virtio_reset, 0, vdev);
return vdev;
}

7
vl.c
View File

@ -3579,6 +3579,7 @@ void vm_start(void)
typedef struct QEMUResetEntry {
QEMUResetHandler *func;
void *opaque;
int order;
struct QEMUResetEntry *next;
} QEMUResetEntry;
@ -3634,16 +3635,18 @@ static void do_vm_stop(int reason)
}
}
void qemu_register_reset(QEMUResetHandler *func, void *opaque)
void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque)
{
QEMUResetEntry **pre, *re;
pre = &first_reset_entry;
while (*pre != NULL)
while (*pre != NULL && (*pre)->order >= order) {
pre = &(*pre)->next;
}
re = qemu_mallocz(sizeof(QEMUResetEntry));
re->func = func;
re->opaque = opaque;
re->order = order;
re->next = NULL;
*pre = re;
}

Write Preview
Loading…
Cancel
Save