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tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally 

By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
pull/291/head
Philippe Mathieu-Daudé 1 year ago
committed by Richard Henderson
parent
0eca13c29a
commit
8201f1a29c
40 changed files with 66 additions and 101 deletions
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  1. 4
      docs/devel/multi-thread-tcg.rst
  2. 3
      target/alpha/cpu-param.h
  3. 3
      target/alpha/cpu.c
  4. 3
      target/arm/cpu-param.h
  5. 3
      target/arm/cpu.c
  6. 3
      target/arm/tcg/cpu-v7m.c
  7. 2
      target/avr/cpu-param.h
  8. 2
      target/avr/cpu.c
  9. 3
      target/hexagon/cpu-param.h
  10. 3
      target/hexagon/cpu.c
  11. 8
      target/hppa/cpu-param.h
  12. 8
      target/hppa/cpu.c
  13. 3
      target/i386/cpu-param.h
  14. 5
      target/i386/tcg/tcg-cpu.c
  15. 2
      target/loongarch/cpu-param.h
  16. 2
      target/loongarch/cpu.c
  17. 3
      target/m68k/cpu-param.h
  18. 3
      target/m68k/cpu.c
  19. 3
      target/microblaze/cpu-param.h
  20. 3
      target/microblaze/cpu.c
  21. 2
      target/mips/cpu-param.h
  22. 2
      target/mips/cpu.c
  23. 2
      target/openrisc/cpu-param.h
  24. 2
      target/openrisc/cpu.c
  25. 2
      target/ppc/cpu-param.h
  26. 2
      target/ppc/cpu_init.c
  27. 2
      target/riscv/cpu-param.h
  28. 2
      target/riscv/tcg/tcg-cpu.c
  29. 3
      target/rx/cpu-param.h
  30. 3
      target/rx/cpu.c
  31. 6
      target/s390x/cpu-param.h
  32. 6
      target/s390x/cpu.c
  33. 3
      target/sh4/cpu-param.h
  34. 3
      target/sh4/cpu.c
  35. 23
      target/sparc/cpu-param.h
  36. 23
      target/sparc/cpu.c
  37. 3
      target/tricore/cpu-param.h
  38. 3
      target/tricore/cpu.c
  39. 3
      target/xtensa/cpu-param.h
  40. 3
      target/xtensa/cpu.c

4
docs/devel/multi-thread-tcg.rst
View File

@ -28,8 +28,8 @@ vCPU Scheduling
We introduce a new running mode where each vCPU will run on its own
user-space thread. This is enabled by default for all FE/BE
combinations where the host memory model is able to accommodate the
guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the
guest has had the required work done to support this safely
guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero)
and the guest has had the required work done to support this safely
(TARGET_SUPPORTS_MTTCG).
System emulation will fall back to the original round robin approach

3
target/alpha/cpu-param.h
View File

@ -26,7 +26,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#endif

3
target/alpha/cpu.c
View File

@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* Alpha processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = alpha_translate_init,
.translate_code = alpha_translate_code,

3
target/arm/cpu-param.h
View File

@ -44,7 +44,4 @@
*/
#define TARGET_INSN_START_EXTRA_WORDS 2
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#endif

3
target/arm/cpu.c
View File

@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#ifdef CONFIG_TCG
static const TCGCPUOps arm_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* ARM processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = arm_translate_init,
.translate_code = arm_translate_code,

3
target/arm/tcg/cpu-v7m.c
View File

@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj)
}
static const TCGCPUOps arm_v7m_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* ARM processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = arm_translate_init,
.translate_code = arm_translate_code,

2
target/avr/cpu-param.h
View File

@ -27,6 +27,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO 0
#endif

2
target/avr/cpu.c
View File

@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = avr_cpu_tcg_init,
.translate_code = avr_cpu_translate_code,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,

3
target/hexagon/cpu-param.h
View File

@ -25,7 +25,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

3
target/hexagon/cpu.c
View File

@ -325,7 +325,8 @@ static void hexagon_cpu_init(Object *obj)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = hexagon_translate_init,
.translate_code = hexagon_translate_code,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,

8
target/hppa/cpu-param.h
View File

@ -21,12 +21,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
* a weak memory model, but with TLB bits that force ordering on a per-page
* basis. It's probably easier to fall back to a strong memory model.
*/
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

8
target/hppa/cpu.c
View File

@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
* a weak memory model, but with TLB bits that force ordering on a per-page
* basis. It's probably easier to fall back to a strong memory model.
*/
.guest_default_memory_order = TCG_MO_ALL,
.initialize = hppa_translate_init,
.translate_code = hppa_translate_code,

3
target/i386/cpu-param.h
View File

@ -24,7 +24,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
#endif

5
target/i386/tcg/tcg-cpu.c
View File

@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/*
* The x86 has a strong memory model with some store-after-load re-ordering
*/
.guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD,
.initialize = tcg_x86_init,
.translate_code = x86_translate_code,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,

2
target/loongarch/cpu-param.h
View File

@ -15,6 +15,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO (0)
#endif

2
target/loongarch/cpu.c
View File

@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = loongarch_translate_init,
.translate_code = loongarch_translate_code,

3
target/m68k/cpu-param.h
View File

@ -19,7 +19,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

3
target/m68k/cpu.c
View File

@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = m68k_tcg_init,
.translate_code = m68k_translate_code,

3
target/microblaze/cpu-param.h
View File

@ -29,7 +29,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* MicroBlaze is always in-order. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

3
target/microblaze/cpu.c
View File

@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MicroBlaze is always in-order. */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = mb_tcg_init,
.translate_code = mb_translate_code,

2
target/mips/cpu-param.h
View File

@ -22,6 +22,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
#define TCG_GUEST_DEFAULT_MO (0)
#endif

2
target/mips/cpu.c
View File

@ -551,7 +551,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
}
static const TCGCPUOps mips_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = mips_tcg_init,
.translate_code = mips_translate_code,

2
target/openrisc/cpu-param.h
View File

@ -14,6 +14,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
#define TCG_GUEST_DEFAULT_MO (0)
#endif

2
target/openrisc/cpu.c
View File

@ -243,7 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps openrisc_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = openrisc_translate_init,
.translate_code = openrisc_translate_code,

2
target/ppc/cpu-param.h
View File

@ -39,6 +39,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO 0
#endif

2
target/ppc/cpu_init.c
View File

@ -7479,7 +7479,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps ppc_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = ppc_translate_init,
.translate_code = ppc_translate_code,
.restore_state_to_opc = ppc_restore_state_to_opc,

2
target/riscv/cpu-param.h
View File

@ -34,6 +34,4 @@
* - M mode HLV/HLVX/HSV 0b111
*/
#define TCG_GUEST_DEFAULT_MO 0
#endif

2
target/riscv/tcg/tcg-cpu.c
View File

@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
}
static const TCGCPUOps riscv_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = riscv_translate_init,
.translate_code = riscv_translate_code,

3
target/rx/cpu-param.h
View File

@ -26,7 +26,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

3
target/rx/cpu.c
View File

@ -204,7 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps rx_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = rx_translate_init,
.translate_code = rx_translate_code,

6
target/s390x/cpu-param.h
View File

@ -14,10 +14,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
/*
* The z/Architecture has a strong memory model with some
* store-after-load re-ordering.
*/
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
#endif

6
target/s390x/cpu.c
View File

@ -345,7 +345,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
}
static const TCGCPUOps s390_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/*
* The z/Architecture has a strong memory model with some
* store-after-load re-ordering.
*/
.guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD,
.initialize = s390x_translate_init,
.translate_code = s390x_translate_code,

3
target/sh4/cpu-param.h
View File

@ -18,7 +18,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

3
target/sh4/cpu.c
View File

@ -262,7 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = sh4_translate_init,
.translate_code = sh4_translate_code,

23
target/sparc/cpu-param.h
View File

@ -23,27 +23,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/*
* From Oracle SPARC Architecture 2015:
*
* Compatibility notes: The PSO memory model described in SPARC V8 and
* SPARC V9 compatibility architecture specifications was never implemented
* in a SPARC V9 implementation and is not included in the Oracle SPARC
* Architecture specification.
*
* The RMO memory model described in the SPARC V9 specification was
* implemented in some non-Sun SPARC V9 implementations, but is not
* directly supported in Oracle SPARC Architecture 2015 implementations.
*
* Therefore always use TSO in QEMU.
*
* D.5 Specification of Partial Store Order (PSO)
* ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
*
* D.6 Specification of Total Store Order (TSO)
* ... PSO with the additional requirement that all [stores] are followed
* by an implied MEMBAR #StoreStore.
*/
#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
#endif

23
target/sparc/cpu.c
View File

@ -1001,7 +1001,28 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps sparc_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/*
* From Oracle SPARC Architecture 2015:
*
* Compatibility notes: The PSO memory model described in SPARC V8 and
* SPARC V9 compatibility architecture specifications was never
* implemented in a SPARC V9 implementation and is not included in the
* Oracle SPARC Architecture specification.
*
* The RMO memory model described in the SPARC V9 specification was
* implemented in some non-Sun SPARC V9 implementations, but is not
* directly supported in Oracle SPARC Architecture 2015 implementations.
*
* Therefore always use TSO in QEMU.
*
* D.5 Specification of Partial Store Order (PSO)
* ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
*
* D.6 Specification of Total Store Order (TSO)
* ... PSO with the additional requirement that all [stores] are followed
* by an implied MEMBAR #StoreStore.
*/
.guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST,
.initialize = sparc_tcg_init,
.translate_code = sparc_translate_code,

3
target/tricore/cpu-param.h
View File

@ -14,7 +14,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

3
target/tricore/cpu.c
View File

@ -172,7 +172,8 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps tricore_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = tricore_tcg_init,
.translate_code = tricore_translate_code,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,

3
target/xtensa/cpu-param.h
View File

@ -18,7 +18,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#endif

3
target/xtensa/cpu.c
View File

@ -232,7 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps xtensa_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* Xtensa processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = xtensa_translate_init,
.translate_code = xtensa_translate_code,

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