diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index fbe05a93a8..18d8726af6 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8422,7 +8422,8 @@ static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env)
      * 4 bytes from the page boundary, so we cross the page if the first
      * 16 bits indicate that this is a 32 bit insn.
      */
-    uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+    uint16_t insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,
+                                        MO_LE);
 
     return !tricore_insn_is_16bit(insn);
 }
@@ -8435,15 +8436,15 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint16_t insn_lo;
     bool is_16bit;
 
-    insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+    insn_lo = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, MO_LE);
     is_16bit = tricore_insn_is_16bit(insn_lo);
     if (is_16bit) {
         ctx->opcode = insn_lo;
         ctx->pc_succ_insn = ctx->base.pc_next + 2;
         decode_16Bit_opc(ctx);
     } else {
-        uint32_t insn_hi = translator_lduw(env, &ctx->base,
-                                           ctx->base.pc_next + 2);
+        uint32_t insn_hi = translator_lduw_end(env, &ctx->base,
+                                               ctx->base.pc_next + 2, MO_LE);
         ctx->opcode = insn_hi << 16 | insn_lo;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         decode_32Bit_opc(ctx);