From 7f359375fc8dd4c503b6a0b078fc253fdae4f3e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 18 Jun 2025 08:06:13 +0200 Subject: [PATCH] target/arm/hvf: Really set Generic Timer counter frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting ARMCPU::gt_cntfrq_hz in hvf_arch_init_vcpu() is not correct because the timers have already be initialized with the default frequency. Set it earlier in the AccelOpsClass::cpu_target_realize() handler instead, and assert the value is correct when reaching hvf_arch_init_vcpu(). Fixes: a1477da3dde ("hvf: Add Apple Silicon support") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-ID: <20251103101034.59039-19-philmd@linaro.org> --- target/arm/hvf/hvf.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index bf8bed1495..e4c0d936f1 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -897,6 +897,13 @@ cleanup: return ret; } +static uint64_t get_cntfrq_el0(void) +{ + uint64_t freq_hz = 0; + asm volatile("mrs %0, cntfrq_el0" : "=r"(freq_hz)); + return freq_hz; +} + int hvf_arch_init_vcpu(CPUState *cpu) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -908,7 +915,9 @@ int hvf_arch_init_vcpu(CPUState *cpu) int i; env->aarch64 = true; - asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); + + /* system count frequency sanity check */ + assert(arm_cpu->gt_cntfrq_hz == get_cntfrq_el0()); /* Allocate enough space for our sysreg sync */ arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, @@ -974,6 +983,15 @@ int hvf_arch_init_vcpu(CPUState *cpu) bool hvf_arch_cpu_realize(CPUState *cs, Error **errp) { + ARMCPU *cpu = ARM_CPU(cs); + + /* + * We must set the counter frequency HVF will be using + * early, before arm_cpu_realizefn initializes the timers + * with it. + */ + cpu->gt_cntfrq_hz = get_cntfrq_el0(); + return true; }