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target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 

The MIPS ISA release 2 is common to 32/64-bit CPUs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
pull/109/head
Philippe Mathieu-Daudé 6 years ago
parent
bbd5e4a27f
commit
7a47bae586
6 changed files with 76 additions and 76 deletions
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  1. 2
      linux-user/mips/cpu_loop.c
  2. 4
      target/mips/cp0_timer.c
  3. 2
      target/mips/helper.c
  4. 2
      target/mips/internal.h
  5. 4
      target/mips/mips-defs.h
  6. 138
      target/mips/translate.c

2
linux-user/mips/cpu_loop.c
View File

@ -384,7 +384,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.frdefault &= interp_req.frdefault; prog_req.frdefault &= interp_req.frdefault;
prog_req.fre &= interp_req.fre; prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
env->insn_flags & ISA_MIPS32R6; env->insn_flags & ISA_MIPS32R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {

4
target/mips/cp0_timer.c
View File

@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
static void cpu_mips_timer_expire(CPUMIPSState *env) static void cpu_mips_timer_expire(CPUMIPSState *env)
{ {
cpu_mips_timer_update(env); cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2) { if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause |= 1 << CP0Ca_TI; env->CP0_Cause |= 1 << CP0Ca_TI;
} }
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env); cpu_mips_timer_update(env);
} }
if (env->insn_flags & ISA_MIPS32R2) { if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI); env->CP0_Cause &= ~(1 << CP0Ca_TI);
} }
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);

2
target/mips/helper.c
View File

@ -431,7 +431,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
uint32_t old = env->CP0_Cause; uint32_t old = env->CP0_Cause;
int i; int i;
if (env->insn_flags & ISA_MIPS32R2) { if (env->insn_flags & ISA_MIPS_R2) {
mask |= 1 << CP0Ca_DC; mask |= 1 << CP0Ca_DC;
} }
if (env->insn_flags & ISA_MIPS32R6) { if (env->insn_flags & ISA_MIPS32R6) {

2
target/mips/internal.h
View File

@ -407,7 +407,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} }
} }
if (env->insn_flags & ISA_MIPS32R2) { if (env->insn_flags & ISA_MIPS_R2) {
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X; env->hflags |= MIPS_HFLAG_COP1X;
} }

4
target/mips/mips-defs.h
View File

@ -17,7 +17,7 @@
#define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_MIPS32R6 0x0000000000002000ULL
@ -73,7 +73,7 @@
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */ /* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2)
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */ /* MIPS Technologies "Release 3" */

138
target/mips/translate.c
View File

@ -7612,7 +7612,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask"; register_name = "PageMask";
break; break;
case CP0_REG05__PAGEGRAIN: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain"; register_name = "PageGrain";
break; break;
@ -7660,27 +7660,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired"; register_name = "Wired";
break; break;
case CP0_REG06__SRSCONF0: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case CP0_REG06__SRSCONF1: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case CP0_REG06__SRSCONF2: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case CP0_REG06__SRSCONF3: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case CP0_REG06__SRSCONF4: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
@ -7696,7 +7696,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07: case CP0_REGISTER_07:
switch (sel) { switch (sel) {
case CP0_REG07__HWRENA: case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna"; register_name = "HWREna";
break; break;
@ -7791,17 +7791,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status"; register_name = "Status";
break; break;
case CP0_REG12__INTCTL: case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl"; register_name = "IntCtl";
break; break;
case CP0_REG12__SRSCTL: case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl"; register_name = "SRSCtl";
break; break;
case CP0_REG12__SRSMAP: case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap"; register_name = "SRSMap";
break; break;
@ -7837,13 +7837,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid"; register_name = "PRid";
break; break;
case CP0_REG15__EBASE: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg); tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase"; register_name = "EBase";
break; break;
case CP0_REG15__CMGCRBASE: case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr); CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg); tcg_gen_ext32s_tl(arg, arg);
@ -8357,7 +8357,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask"; register_name = "PageMask";
break; break;
case CP0_REG05__PAGEGRAIN: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg); gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain"; register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
@ -8403,27 +8403,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired"; register_name = "Wired";
break; break;
case CP0_REG06__SRSCONF0: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg); gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case CP0_REG06__SRSCONF1: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg); gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case CP0_REG06__SRSCONF2: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg); gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case CP0_REG06__SRSCONF3: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg); gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case CP0_REG06__SRSCONF4: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg); gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
@ -8439,7 +8439,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07: case CP0_REGISTER_07:
switch (sel) { switch (sel) {
case CP0_REG07__HWRENA: case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg); gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna"; register_name = "HWREna";
@ -8522,21 +8522,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status"; register_name = "Status";
break; break;
case CP0_REG12__INTCTL: case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg); gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl"; register_name = "IntCtl";
break; break;
case CP0_REG12__SRSCTL: case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg); gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl"; register_name = "SRSCtl";
break; break;
case CP0_REG12__SRSMAP: case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
@ -8581,7 +8581,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid"; register_name = "PRid";
break; break;
case CP0_REG15__EBASE: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg); gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase"; register_name = "EBase";
break; break;
@ -9120,7 +9120,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask"; register_name = "PageMask";
break; break;
case CP0_REG05__PAGEGRAIN: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain"; register_name = "PageGrain";
break; break;
@ -9165,27 +9165,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired"; register_name = "Wired";
break; break;
case CP0_REG06__SRSCONF0: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case CP0_REG06__SRSCONF1: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case CP0_REG06__SRSCONF2: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case CP0_REG06__SRSCONF3: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case CP0_REG06__SRSCONF4: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
@ -9201,7 +9201,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07: case CP0_REGISTER_07:
switch (sel) { switch (sel) {
case CP0_REG07__HWRENA: case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna"; register_name = "HWREna";
break; break;
@ -9294,17 +9294,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status"; register_name = "Status";
break; break;
case CP0_REG12__INTCTL: case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl"; register_name = "IntCtl";
break; break;
case CP0_REG12__SRSCTL: case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl"; register_name = "SRSCtl";
break; break;
case CP0_REG12__SRSMAP: case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap"; register_name = "SRSMap";
break; break;
@ -9339,12 +9339,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid"; register_name = "PRid";
break; break;
case CP0_REG15__EBASE: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase"; register_name = "EBase";
break; break;
case CP0_REG15__CMGCRBASE: case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr); CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
register_name = "CMGCRBase"; register_name = "CMGCRBase";
@ -9847,7 +9847,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask"; register_name = "PageMask";
break; break;
case CP0_REG05__PAGEGRAIN: case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg); gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain"; register_name = "PageGrain";
break; break;
@ -9892,27 +9892,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired"; register_name = "Wired";
break; break;
case CP0_REG06__SRSCONF0: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg); gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case CP0_REG06__SRSCONF1: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg); gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case CP0_REG06__SRSCONF2: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg); gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case CP0_REG06__SRSCONF3: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg); gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case CP0_REG06__SRSCONF4: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg); gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
@ -9928,7 +9928,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07: case CP0_REGISTER_07:
switch (sel) { switch (sel) {
case CP0_REG07__HWRENA: case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg); gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna"; register_name = "HWREna";
@ -10015,21 +10015,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status"; register_name = "Status";
break; break;
case CP0_REG12__INTCTL: case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg); gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl"; register_name = "IntCtl";
break; break;
case CP0_REG12__SRSCTL: case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg); gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl"; register_name = "SRSCtl";
break; break;
case CP0_REG12__SRSMAP: case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
@ -10074,7 +10074,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid"; register_name = "PRid";
break; break;
case CP0_REG15__EBASE: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg); gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase"; register_name = "EBase";
break; break;
@ -13453,7 +13453,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
* The Linux kernel will emulate rdhwr if it's not supported natively. * The Linux kernel will emulate rdhwr if it's not supported natively.
* Therefore only check the ISA in system mode. * Therefore only check the ISA in system mode.
*/ */
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
#endif #endif
t0 = tcg_temp_new(); t0 = tcg_temp_new();
@ -16269,12 +16269,12 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
switch (minor) { switch (minor) {
case RDPGPR: case RDPGPR:
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rs, rt); gen_load_srsgpr(rs, rt);
break; break;
case WRPGPR: case WRPGPR:
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rs, rt); gen_store_srsgpr(rs, rt);
break; break;
default: default:
@ -24984,7 +24984,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) { switch ((ctx->opcode >> 21) & 0x1f) {
case 1: case 1:
/* rotr is decoded as srl on non-R2 CPUs */ /* rotr is decoded as srl on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS32R2) { if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTR; op1 = OPC_ROTR;
} }
/* Fallthrough */ /* Fallthrough */
@ -25010,7 +25010,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 6) & 0x1f) { switch ((ctx->opcode >> 6) & 0x1f) {
case 1: case 1:
/* rotrv is decoded as srlv on non-R2 CPUs */ /* rotrv is decoded as srlv on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS32R2) { if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTRV; op1 = OPC_ROTRV;
} }
/* Fallthrough */ /* Fallthrough */
@ -25083,7 +25083,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) { switch ((ctx->opcode >> 21) & 0x1f) {
case 1: case 1:
/* drotr is decoded as dsrl on non-R2 CPUs */ /* drotr is decoded as dsrl on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS32R2) { if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR; op1 = OPC_DROTR;
} }
/* Fallthrough */ /* Fallthrough */
@ -25101,7 +25101,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) { switch ((ctx->opcode >> 21) & 0x1f) {
case 1: case 1:
/* drotr32 is decoded as dsrl32 on non-R2 CPUs */ /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS32R2) { if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR32; op1 = OPC_DROTR32;
} }
/* Fallthrough */ /* Fallthrough */
@ -25133,7 +25133,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 6) & 0x1f) { switch ((ctx->opcode >> 6) & 0x1f) {
case 1: case 1:
/* drotrv is decoded as dsrlv on non-R2 CPUs */ /* drotrv is decoded as dsrlv on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS32R2) { if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTRV; op1 = OPC_DROTRV;
} }
/* Fallthrough */ /* Fallthrough */
@ -28594,7 +28594,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
switch (op1) { switch (op1) {
case OPC_EXT: case OPC_EXT:
case OPC_INS: case OPC_INS:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_bitops(ctx, op1, rt, rs, sa, rd); gen_bitops(ctx, op1, rt, rs, sa, rd);
break; break;
case OPC_BSHFL: case OPC_BSHFL:
@ -28609,7 +28609,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special3_r6(env, ctx); decode_opc_special3_r6(env, ctx);
break; break;
default: default:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_bshfl(ctx, op2, rt, rd); gen_bshfl(ctx, op2, rt, rd);
break; break;
} }
@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DINSM: case OPC_DINSM:
case OPC_DINSU: case OPC_DINSU:
case OPC_DINS: case OPC_DINS:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx); check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd); gen_bitops(ctx, op1, rt, rs, sa, rd);
break; break;
@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special3_r6(env, ctx); decode_opc_special3_r6(env, ctx);
break; break;
default: default:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx); check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode); op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd); gen_bshfl(ctx, op2, rt, rd);
@ -30741,7 +30741,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_SYNCI: case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
/* /*
* Break the TB to be able to sync copied instructions * Break the TB to be able to sync copied instructions
* immediately. * immediately.
@ -30858,7 +30858,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
case OPC_DI: case OPC_DI:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env); gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
@ -30869,7 +30869,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
break; break;
case OPC_EI: case OPC_EI:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env); gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
@ -30890,11 +30890,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */
break; break;
case OPC_RDPGPR: case OPC_RDPGPR:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rt, rd); gen_load_srsgpr(rt, rd);
break; break;
case OPC_WRPGPR: case OPC_WRPGPR:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rt, rd); gen_store_srsgpr(rt, rd);
break; break;
default: default:
@ -31056,7 +31056,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_MFHC1: case OPC_MFHC1:
case OPC_MTHC1: case OPC_MTHC1:
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS_R2);
/* fall through */ /* fall through */
case OPC_MFC1: case OPC_MFC1:
case OPC_CFC1: case OPC_CFC1:
@ -31250,21 +31250,21 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
switch (op1) { switch (op1) {
case OPC_LUXC1: case OPC_LUXC1:
case OPC_SUXC1: case OPC_SUXC1:
check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */ /* Fallthrough */
case OPC_LWXC1: case OPC_LWXC1:
case OPC_LDXC1: case OPC_LDXC1:
case OPC_SWXC1: case OPC_SWXC1:
case OPC_SDXC1: case OPC_SDXC1:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break; break;
case OPC_PREFX: case OPC_PREFX:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
/* Treat as NOP. */ /* Treat as NOP. */
break; break;
case OPC_ALNV_PS: case OPC_ALNV_PS:
check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */ /* Fallthrough */
case OPC_MADD_S: case OPC_MADD_S:
case OPC_MADD_D: case OPC_MADD_D:
@ -31278,7 +31278,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_NMSUB_S: case OPC_NMSUB_S:
case OPC_NMSUB_D: case OPC_NMSUB_D:
case OPC_NMSUB_PS: case OPC_NMSUB_PS:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_arith(ctx, op1, sa, rs, rd, rt); gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break; break;
default: default:

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