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Add a minimal PCI test device designed to exercise IOMMU translation (such as ARM SMMUv3) without requiring guest firmware or OS. The device provides MMIO registers to configure and trigger DMA operations with controllable attributes (security state, address space), enabling deterministic IOMMU testing. Key features: - Bare-metal IOMMU testing via simple MMIO interface - Configurable DMA attributes for security states and address spaces - Write-then-read verification pattern with automatic result checking The device performs a deterministic DMA test pattern: write a known value (0x12345678) to a configured GVA, read it back, and verify data integrity. Results are reported through a dedicated result register, eliminating the need for complex interrupt handling or driver infrastructure in tests. This is purely a test device and not intended for production use or machine realism. It complements existing test infrastructure like pci-testdev but focuses specifically on IOMMU translation path validation. Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20260119161112.3841386-4-tangtao1634@phytium.com.cn> [PMD: Add SPDX-License-Identifier: GPL-2.0-or-later tag] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>pull/316/head
Tao Tang
11 months ago
committed by
Philippe Mathieu-Daudé
Philippe Mathieu-Daudé
8 changed files with 569 additions and 0 deletions
@ -0,0 +1,140 @@ |
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.. SPDX-License-Identifier: GPL-2.0-or-later |
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|
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iommu-testdev — IOMMU test device for bare-metal testing |
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======================================================== |
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|
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Overview |
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-------- |
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``iommu-testdev`` is a minimal, test-only PCI device designed to exercise |
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IOMMU translation (such as ARM SMMUv3) without requiring firmware or a guest |
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OS. Tests can populate IOMMU translation tables with known values and trigger |
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DMA operations that flow through the IOMMU translation path. It is **not** a |
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faithful PCIe endpoint and must be considered a QEMU-internal test vehicle. |
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|
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Key Features |
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------------ |
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* **Bare-metal IOMMU testing**: No guest kernel or firmware required |
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* **Configurable DMA attributes**: Supports address space configuration via |
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MMIO registers |
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* **Deterministic verification**: Write-then-read DMA pattern with automatic |
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result checking |
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|
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Status |
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------ |
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* Location: ``hw/misc/iommu-testdev.c`` |
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* Header: ``include/hw/misc/iommu-testdev.h`` |
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* Build guard: ``CONFIG_IOMMU_TESTDEV`` |
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|
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Device Interface |
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---------------- |
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The device exposes a single PCI BAR0 with 32-bit MMIO registers: |
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|
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* ``ITD_REG_DMA_TRIGGERING`` (0x00): Read triggers DMA and consumes |
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the armed request |
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* ``ITD_REG_DMA_GVA_LO`` (0x04): DMA IOVA bits [31:0] |
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* ``ITD_REG_DMA_GVA_HI`` (0x08): DMA IOVA bits [63:32] |
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* ``ITD_REG_DMA_GPA_LO`` (0x1C): DMA GPA bits [31:0] for readback validation |
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* ``ITD_REG_DMA_GPA_HI`` (0x20): DMA GPA bits [63:32] for readback validation |
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* ``ITD_REG_DMA_LEN`` (0x0C): DMA transfer length |
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* ``ITD_REG_DMA_RESULT`` (0x10): DMA result |
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(0=success, 0xffffffff=idle, 0xfffffffe=armed) |
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* ``ITD_REG_DMA_DBELL`` (0x14): Write 1 to arm DMA, write 0 to disarm. |
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Arming only marks the request and sets BUSY (no latch/check), but it |
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provides an explicit gate for qtests and leaves room for async/latching. |
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* ``ITD_REG_DMA_ATTRS`` (0x18): DMA attributes which shadow some fields in |
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MemTxAttrs: |
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- bit[0]: secure (1=Secure, 0=Non-Secure) |
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- bits[2:1]: ArmSecuritySpace (0=Secure, 1=Non-Secure) |
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- bit[3]: space_valid (1=space is valid, 0=ignore space and default to Non-Secure) |
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``space`` field in MemTxAttrs is consumed only when ``space_valid`` is set. |
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For Secure/Non-Secure, ``secure`` and ``space`` must match; mismatches |
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return ``ITD_DMA_ERR_BAD_ATTRS``. Other bits are reserved but can be wired |
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up easily if future tests need to pass extra attributes. |
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|
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Translation Setup Workflow |
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-------------------------- |
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``iommu-testdev`` never builds SMMU/AMD-Vi/RISC-V IOMMU structures on its own. |
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Architecture-specific construction lives entirely in qtest/libqos helpers. |
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Those helpers populate guest memory with page tables/architecture-specific |
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structures and program the emulated IOMMU registers directly. See the |
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``qsmmu_setup_and_enable_translation()`` function in |
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``tests/qtest/libqos/qos-smmuv3.c`` for an example of how SMMUv3 translation |
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is set up for this device. |
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|
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DMA Operation Flow |
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------------------ |
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Arming semantics: |
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|
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* Writing ``DMA_DBELL`` with bit0=1 marks the request armed and sets |
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``DMA_RESULT`` to BUSY. It does not latch GVA/LEN/ATTRS; values are sampled |
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when ``DMA_TRIGGERING`` is read. |
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* Writing ``DMA_DBELL`` with bit0=0 disarms the request and sets |
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``DMA_RESULT`` to IDLE. |
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* Reading ``DMA_TRIGGERING`` consumes the armed request and clears the armed |
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state, even on error. |
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|
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The flow would be split into these steps, mainly for timing control and |
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debuggability: qtests can easily exercise and assert distinct paths |
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(NOT_ARMED, BAD_LEN, TX/RD failures, mismatch) instead of having all side |
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effects hidden behind a single step: |
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1. Test programs IOMMU translation tables |
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2. Test configures DMA IOVA (GVA_LO/HI), GPA for readback, length, and attributes |
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3. Test writes 1 to DMA_DBELL to arm the operation |
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4. Test reads DMA_TRIGGERING to execute DMA |
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5. Test polls DMA_RESULT: |
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|
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- 0x00000000: Success |
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- 0xFFFFFFFE: Armed (waiting for trigger). DMA runs synchronously, so |
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BUSY is not observed once the trigger read completes. |
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- 0xDEAD0006: Bad attrs (secure/space mismatch for S/NS) |
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- 0xDEAD000X: Various error codes |
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|
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The device performs a write-then-read sequence using a known pattern |
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(0x12345678) and verifies data integrity automatically. |
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|
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Running the qtest |
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----------------- |
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The SMMUv3 test suite uses this device and covers multiple translation modes:: |
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|
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cd build |
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QTEST_QEMU_BINARY=./qemu-system-aarch64 \\ |
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./tests/qtest/iommu-smmuv3-test --tap -k |
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This test suite exercises: |
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* Stage 1 only translation |
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* Stage 2 only translation |
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* Nested (Stage 1 + Stage 2) translation |
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Instantiation |
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------------- |
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The device is not wired into any board by default. Tests instantiate it |
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via QEMU command line:: |
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-device iommu-testdev |
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For ARM platforms with SMMUv3:: |
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-M virt,iommu=smmuv3 -device iommu-testdev |
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When the IOMMU sits on the same PCI root complex (``pci.0``), the device is |
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placed behind it automatically. For other PCI topologies, specify the bus |
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explicitly. |
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|
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Limitations |
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----------- |
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* No realistic PCIe enumeration, MSI/MSI-X, or interrupt handling |
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* No ATS/PRI support |
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* No actual device functionality beyond DMA test pattern |
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* Test-only; not suitable for production or machine realism |
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* Address space support (Secure/Root/Realm) is architecture-dependent and |
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gated by ``space_valid`` |
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* Readback uses the programmed GPA and reads via system memory, avoiding a |
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second IOMMU access for the readback step |
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|
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See also |
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-------- |
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* ``tests/qtest/iommu-smmuv3-test.c`` — SMMUv3 test suite |
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* ``tests/qtest/libqos/qos-smmuv3.{c,h}`` — SMMUv3 test library |
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* SMMUv3 emulation: ``hw/arm/smmu*`` |
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@ -0,0 +1,318 @@ |
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/*
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* A test device for IOMMU |
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* |
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* Copyright (c) 2026 Phytium Technology |
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* |
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* Author: |
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* Tao Tang <tangtao1634@phytium.com.cn> |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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|
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#include "qemu/osdep.h" |
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#include "system/address-spaces.h" |
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#include "system/memory.h" |
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#include "trace.h" |
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#include "hw/pci/pci_device.h" |
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#include "hw/core/qdev-properties.h" |
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#include "qom/object.h" |
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#include "hw/misc/iommu-testdev.h" |
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#define TYPE_IOMMU_TESTDEV "iommu-testdev" |
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OBJECT_DECLARE_SIMPLE_TYPE(IOMMUTestDevState, IOMMU_TESTDEV) |
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struct IOMMUTestDevState { |
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PCIDevice parent_obj; |
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MemoryRegion bar0; |
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uint64_t dma_vaddr; |
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uint64_t dma_paddr; |
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uint32_t dma_len; |
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uint32_t dma_result; |
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bool dma_armed; /* armed until a trigger consumes the request */ |
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AddressSpace *dma_as; /* IOMMU-mediated DMA AS for this device */ |
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uint32_t dma_attrs_cfg; /* bit0 secure, bits[2:1] space, bit3 valid */ |
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}; |
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static bool iommu_testdev_attrs_inconsistent(uint32_t cfg) |
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{ |
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uint32_t space; |
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bool secure; |
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if (!ITD_ATTRS_GET_SPACE_VALID(cfg)) { |
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return false; |
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} |
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space = ITD_ATTRS_GET_SPACE(cfg); |
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secure = ITD_ATTRS_GET_SECURE(cfg); |
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if (space == ITD_ATTRS_SPACE_SECURE || space == ITD_ATTRS_SPACE_NONSECURE) { |
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return secure != (space == ITD_ATTRS_SPACE_SECURE); |
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} |
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return false; |
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} |
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static void iommu_testdev_maybe_run_dma(IOMMUTestDevState *s) |
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{ |
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uint32_t expected_val, actual_val; |
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g_autofree uint8_t *write_buf = NULL; |
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g_autofree uint8_t *read_buf = NULL; |
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MemTxResult write_res, read_res; |
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MemTxAttrs attrs = {}; |
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AddressSpace *as; |
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bool space_valid; |
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if (!s->dma_armed) { |
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s->dma_result = ITD_DMA_ERR_NOT_ARMED; |
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trace_iommu_testdev_dma_result(s->dma_result); |
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return; |
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} |
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trace_iommu_testdev_dma_start(); |
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if (!s->dma_len) { |
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s->dma_result = ITD_DMA_ERR_BAD_LEN; |
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goto out; |
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} |
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write_buf = g_malloc(s->dma_len); |
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read_buf = g_malloc(s->dma_len); |
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/* Initialize MemTxAttrs from generic register. */ |
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attrs.secure = ITD_ATTRS_GET_SECURE(s->dma_attrs_cfg); |
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space_valid = ITD_ATTRS_GET_SPACE_VALID(s->dma_attrs_cfg); |
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if (space_valid) { |
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/* The 'space' field in MemTxAttrs is ARM-specific. */ |
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attrs.space = ITD_ATTRS_GET_SPACE(s->dma_attrs_cfg); |
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} else { |
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/* Default to Non-Secure when space is not valid. */ |
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attrs.space = ITD_ATTRS_SPACE_NONSECURE; |
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} |
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if (iommu_testdev_attrs_inconsistent(s->dma_attrs_cfg)) { |
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s->dma_result = ITD_DMA_ERR_BAD_ATTRS; |
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goto out; |
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} |
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as = s->dma_as; |
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/* Step 1: Write ITD_DMA_WRITE_VAL to DMA address */ |
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trace_iommu_testdev_dma_write(s->dma_vaddr, s->dma_len); |
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for (int i = 0; i < s->dma_len; i++) { |
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/* Data is written in little-endian order */ |
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write_buf[i] = (ITD_DMA_WRITE_VAL >> ((i % 4) * 8)) & 0xff; |
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} |
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write_res = dma_memory_write(as, s->dma_vaddr, write_buf, |
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s->dma_len, attrs); |
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if (write_res != MEMTX_OK) { |
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s->dma_result = ITD_DMA_ERR_TX_FAIL; |
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goto out; |
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} |
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/* Step 2: Read back from the same DMA address */ |
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trace_iommu_testdev_dma_read(s->dma_vaddr, s->dma_len); |
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read_res = address_space_read(&address_space_memory, s->dma_paddr, |
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attrs, read_buf, s->dma_len); |
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if (read_res != MEMTX_OK) { |
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s->dma_result = ITD_DMA_ERR_RD_FAIL; |
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goto out; |
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} |
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/* Step 3: Verify the read data matches what we wrote */ |
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for (int i = 0; i < s->dma_len; i += 4) { |
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int remaining_bytes = MIN(4, s->dma_len - i); |
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expected_val = 0; |
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actual_val = 0; |
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for (int j = 0; j < remaining_bytes; j++) { |
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expected_val |= ((uint32_t)write_buf[i + j]) << (j * 8); |
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actual_val |= ((uint32_t)read_buf[i + j]) << (j * 8); |
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} |
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trace_iommu_testdev_dma_verify(expected_val, actual_val); |
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if (expected_val != actual_val) { |
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s->dma_result = ITD_DMA_ERR_MISMATCH; |
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goto out; |
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} |
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} |
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/* All checks passed */ |
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s->dma_result = 0; |
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out: |
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trace_iommu_testdev_dma_result(s->dma_result); |
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s->dma_armed = false; |
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} |
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static uint64_t iommu_testdev_mmio_read(void *opaque, hwaddr addr, |
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unsigned size) |
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{ |
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IOMMUTestDevState *s = opaque; |
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uint64_t value = 0; |
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switch (addr) { |
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case ITD_REG_DMA_TRIGGERING: |
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/*
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* This lets tests poll ITD_REG_DMA_RESULT to observe BUSY before |
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* consuming the DMA. |
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*/ |
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iommu_testdev_maybe_run_dma(s); |
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value = 0; |
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break; |
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case ITD_REG_DMA_GVA_LO: |
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value = (uint32_t)(s->dma_vaddr & 0xffffffffu); |
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break; |
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case ITD_REG_DMA_GVA_HI: |
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value = (uint32_t)(s->dma_vaddr >> 32); |
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break; |
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case ITD_REG_DMA_GPA_LO: |
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value = (uint32_t)(s->dma_paddr & 0xffffffffu); |
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break; |
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case ITD_REG_DMA_GPA_HI: |
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value = (uint32_t)(s->dma_paddr >> 32); |
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break; |
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case ITD_REG_DMA_LEN: |
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value = s->dma_len; |
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break; |
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case ITD_REG_DMA_RESULT: |
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value = s->dma_result; |
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break; |
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case ITD_REG_DMA_ATTRS: |
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value = s->dma_attrs_cfg; |
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break; |
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default: |
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value = 0; |
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break; |
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} |
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trace_iommu_testdev_mmio_read(addr, value, size); |
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return value; |
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} |
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static void iommu_testdev_mmio_write(void *opaque, hwaddr addr, uint64_t val, |
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unsigned size) |
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{ |
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IOMMUTestDevState *s = opaque; |
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uint32_t data = val; |
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trace_iommu_testdev_mmio_write(addr, val, size); |
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switch (addr) { |
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case ITD_REG_DMA_GVA_LO: |
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s->dma_vaddr = (s->dma_vaddr & ~0xffffffffull) | data; |
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break; |
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case ITD_REG_DMA_GVA_HI: |
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s->dma_vaddr = (s->dma_vaddr & 0xffffffffull) | |
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((uint64_t)data << 32); |
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break; |
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case ITD_REG_DMA_GPA_LO: |
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s->dma_paddr = (s->dma_paddr & ~0xffffffffull) | data; |
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break; |
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case ITD_REG_DMA_GPA_HI: |
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s->dma_paddr = (s->dma_paddr & 0xffffffffull) | |
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((uint64_t)data << 32); |
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break; |
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case ITD_REG_DMA_LEN: |
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s->dma_len = data; |
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break; |
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case ITD_REG_DMA_RESULT: |
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s->dma_result = data; |
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break; |
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case ITD_REG_DMA_DBELL: |
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if (data & ITD_DMA_DBELL_ARM) { |
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/* Arm the DMA operation; repeated arm is idempotent. */ |
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s->dma_armed = true; |
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s->dma_result = ITD_DMA_RESULT_BUSY; |
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trace_iommu_testdev_dma_armed(true); |
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} else { |
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/* Disarm the DMA operation */ |
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s->dma_armed = false; |
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s->dma_result = ITD_DMA_RESULT_IDLE; |
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trace_iommu_testdev_dma_armed(false); |
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} |
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break; |
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case ITD_REG_DMA_ATTRS: |
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s->dma_attrs_cfg = data; |
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break; |
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default: |
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break; |
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} |
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} |
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static const MemoryRegionOps iommu_testdev_mmio_ops = { |
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.read = iommu_testdev_mmio_read, |
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.write = iommu_testdev_mmio_write, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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.valid = { |
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.min_access_size = 4, |
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.max_access_size = 4, |
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}, |
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}; |
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|
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static void iommu_testdev_realize(PCIDevice *pdev, Error **errp) |
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{ |
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IOMMUTestDevState *s = IOMMU_TESTDEV(pdev); |
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s->dma_vaddr = 0; |
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s->dma_paddr = 0; |
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s->dma_len = 0; |
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s->dma_result = ITD_DMA_RESULT_IDLE; |
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s->dma_armed = false; |
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s->dma_attrs_cfg = ITD_ATTRS_SET_SPACE(0, ITD_ATTRS_SPACE_NONSECURE); |
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s->dma_as = pci_device_iommu_address_space(pdev); |
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memory_region_init_io(&s->bar0, OBJECT(pdev), &iommu_testdev_mmio_ops, s, |
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TYPE_IOMMU_TESTDEV ".bar0", BAR0_SIZE); |
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pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
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} |
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|
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static void iommu_testdev_reset(DeviceState *dev) |
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{ |
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IOMMUTestDevState *s = IOMMU_TESTDEV(dev); |
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s->dma_vaddr = 0; |
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s->dma_paddr = 0; |
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s->dma_len = 0; |
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s->dma_result = ITD_DMA_RESULT_IDLE; |
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s->dma_armed = false; |
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s->dma_attrs_cfg = ITD_ATTRS_SET_SPACE(0, ITD_ATTRS_SPACE_NONSECURE); |
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} |
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|
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static void iommu_testdev_class_init(ObjectClass *klass, const void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); |
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|
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pc->realize = iommu_testdev_realize; |
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pc->vendor_id = IOMMU_TESTDEV_VENDOR_ID; |
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pc->device_id = IOMMU_TESTDEV_DEVICE_ID; |
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pc->revision = 0; |
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pc->class_id = PCI_CLASS_OTHERS; |
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dc->desc = "A test device for IOMMU"; |
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set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
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device_class_set_legacy_reset(dc, iommu_testdev_reset); |
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} |
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static const TypeInfo iommu_testdev_info = { |
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.name = TYPE_IOMMU_TESTDEV, |
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.parent = TYPE_PCI_DEVICE, |
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.instance_size = sizeof(IOMMUTestDevState), |
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.class_init = iommu_testdev_class_init, |
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.interfaces = (const InterfaceInfo[]) { |
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
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{ } |
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}, |
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}; |
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|
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static void iommu_testdev_register_types(void) |
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{ |
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type_register_static(&iommu_testdev_info); |
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} |
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type_init(iommu_testdev_register_types); |
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@ -0,0 +1,87 @@ |
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/*
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* A test device for IOMMU |
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* |
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* Copyright (c) 2026 Phytium Technology |
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* |
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* Author: |
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* Tao Tang <tangtao1634@phytium.com.cn> |
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* |
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* SPDX-License-Identifier: GPL-2.0-or-later |
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*/ |
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#ifndef HW_MISC_IOMMU_TESTDEV_H |
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#define HW_MISC_IOMMU_TESTDEV_H |
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#include "hw/pci/pci.h" |
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|
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#define IOMMU_TESTDEV_VENDOR_ID PCI_VENDOR_ID_REDHAT |
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#define IOMMU_TESTDEV_DEVICE_ID PCI_DEVICE_ID_REDHAT_TEST |
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|
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/* DMA_ATTRS register bit definitions which shadow some fields in MemTxAttrs */ |
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#define ITD_ATTRS_SECURE_SHIFT 0 |
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#define ITD_ATTRS_SECURE_MASK 0x1 |
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#define ITD_ATTRS_SPACE_SHIFT 1 |
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#define ITD_ATTRS_SPACE_MASK 0x3 |
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#define ITD_ATTRS_SPACE_VALID_SHIFT 3 |
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#define ITD_ATTRS_SPACE_VALID_MASK 0x1 |
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|
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#define ITD_ATTRS_SPACE_SECURE 0 |
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#define ITD_ATTRS_SPACE_NONSECURE 1 |
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|
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/* Helper macros for setting fields */ |
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#define ITD_ATTRS_SET_SECURE(attrs, val) \ |
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(((attrs) & ~(ITD_ATTRS_SECURE_MASK << ITD_ATTRS_SECURE_SHIFT)) | \ |
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(((val) & ITD_ATTRS_SECURE_MASK) << ITD_ATTRS_SECURE_SHIFT)) |
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|
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#define ITD_ATTRS_SET_SPACE(attrs, val) \ |
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(((attrs) & ~(ITD_ATTRS_SPACE_MASK << ITD_ATTRS_SPACE_SHIFT)) | \ |
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(((val) & ITD_ATTRS_SPACE_MASK) << ITD_ATTRS_SPACE_SHIFT)) |
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|
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#define ITD_ATTRS_SET_SPACE_VALID(attrs, val) \ |
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(((attrs) & ~(ITD_ATTRS_SPACE_VALID_MASK << \ |
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ITD_ATTRS_SPACE_VALID_SHIFT)) | \ |
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(((val) & ITD_ATTRS_SPACE_VALID_MASK) << \ |
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ITD_ATTRS_SPACE_VALID_SHIFT)) |
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|
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/* Helper macros for getting fields */ |
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#define ITD_ATTRS_GET_SECURE(attrs) \ |
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(((attrs) >> ITD_ATTRS_SECURE_SHIFT) & ITD_ATTRS_SECURE_MASK) |
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|
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#define ITD_ATTRS_GET_SPACE(attrs) \ |
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(((attrs) >> ITD_ATTRS_SPACE_SHIFT) & ITD_ATTRS_SPACE_MASK) |
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|
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#define ITD_ATTRS_GET_SPACE_VALID(attrs) \ |
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(((attrs) >> ITD_ATTRS_SPACE_VALID_SHIFT) & \ |
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ITD_ATTRS_SPACE_VALID_MASK) |
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|
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/* DMA result/status values shared with tests */ |
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#define ITD_DMA_RESULT_IDLE 0xffffffffu |
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#define ITD_DMA_RESULT_BUSY 0xfffffffeu |
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#define ITD_DMA_ERR_BAD_LEN 0xdead0001u |
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#define ITD_DMA_ERR_TX_FAIL 0xdead0002u |
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#define ITD_DMA_ERR_RD_FAIL 0xdead0003u |
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#define ITD_DMA_ERR_MISMATCH 0xdead0004u |
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#define ITD_DMA_ERR_NOT_ARMED 0xdead0005u |
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#define ITD_DMA_ERR_BAD_ATTRS 0xdead0006u |
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|
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#define ITD_DMA_WRITE_VAL 0x12345678u |
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|
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/* DMA doorbell bits */ |
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#define ITD_DMA_DBELL_ARM 0x1u |
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|
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/* BAR0 layout of iommu-testdev */ |
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enum { |
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ITD_REG_DMA_TRIGGERING = 0x00, |
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ITD_REG_DMA_GVA_LO = 0x04, |
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ITD_REG_DMA_GVA_HI = 0x08, |
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ITD_REG_DMA_LEN = 0x0c, |
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ITD_REG_DMA_RESULT = 0x10, |
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ITD_REG_DMA_DBELL = 0x14, |
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/* [0] secure,[2:1] ArmSecuritySpace,[3] space_valid */ |
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ITD_REG_DMA_ATTRS = 0x18, |
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ITD_REG_DMA_GPA_LO = 0x1c, |
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ITD_REG_DMA_GPA_HI = 0x20, |
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BAR0_SIZE = 0x1000, |
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}; |
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|
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#endif /* HW_MISC_IOMMU_TESTDEV_H */ |
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Reference in new issue