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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2143 c046a42c-6fe2-441c-8c8c-71466251a162stable-0.10
bellard
20 years ago
6 changed files with 338 additions and 173 deletions
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/*
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* QEMU Sparc32 DMA controller emulation |
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* |
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* Copyright (c) 2006 Fabrice Bellard |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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#include "vl.h" |
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/* debug DMA */ |
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//#define DEBUG_DMA
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/*
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* This is the DMA controller part of chip STP2000 (Master I/O), also |
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* produced as NCR89C100. See |
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and |
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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*/ |
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#ifdef DEBUG_DMA |
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#define DPRINTF(fmt, args...) \ |
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do { printf("DMA: " fmt , ##args); } while (0) |
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#define pic_set_irq_new(ctl, irq, level) \ |
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do { printf("DMA: set_irq(%d): %d\n", (irq), (level)); \ |
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pic_set_irq_new((ctl), (irq),(level));} while (0) |
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#else |
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#define DPRINTF(fmt, args...) |
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#endif |
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#define DMA_REGS 8 |
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#define DMA_MAXADDR (DMA_REGS * 4 - 1) |
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#define DMA_VER 0xa0000000 |
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#define DMA_INTR 1 |
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#define DMA_INTREN 0x10 |
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#define DMA_WRITE_MEM 0x100 |
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#define DMA_LOADED 0x04000000 |
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#define DMA_RESET 0x80 |
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typedef struct DMAState DMAState; |
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struct DMAState { |
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uint32_t dmaregs[DMA_REGS]; |
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int espirq, leirq; |
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void *iommu, *esp_opaque, *lance_opaque, *intctl; |
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}; |
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void ledma_set_irq(void *opaque, int isr) |
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{ |
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DMAState *s = opaque; |
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pic_set_irq_new(s->intctl, s->leirq, isr); |
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} |
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void ledma_memory_read(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len) |
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{ |
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DMAState *s = opaque; |
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n", |
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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sparc_iommu_memory_read(s->iommu, addr | s->dmaregs[7], buf, len); |
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} |
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void ledma_memory_write(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len) |
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{ |
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DMAState *s = opaque; |
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n", |
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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sparc_iommu_memory_write(s->iommu, addr | s->dmaregs[7], buf, len); |
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} |
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void espdma_raise_irq(void *opaque) |
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{ |
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DMAState *s = opaque; |
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s->dmaregs[0] |= DMA_INTR; |
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pic_set_irq_new(s->intctl, s->espirq, 1); |
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} |
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void espdma_clear_irq(void *opaque) |
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{ |
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DMAState *s = opaque; |
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s->dmaregs[0] &= ~DMA_INTR; |
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pic_set_irq_new(s->intctl, s->espirq, 0); |
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} |
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void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
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{ |
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DMAState *s = opaque; |
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n", |
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); |
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s->dmaregs[0] |= DMA_INTR; |
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s->dmaregs[1] += len; |
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} |
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void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
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{ |
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DMAState *s = opaque; |
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n", |
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); |
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s->dmaregs[0] |= DMA_INTR; |
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s->dmaregs[1] += len; |
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} |
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static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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DMAState *s = opaque; |
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uint32_t saddr; |
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saddr = (addr & DMA_MAXADDR) >> 2; |
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DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->dmaregs[saddr]); |
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return s->dmaregs[saddr]; |
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} |
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static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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DMAState *s = opaque; |
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uint32_t saddr; |
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saddr = (addr & DMA_MAXADDR) >> 2; |
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DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val); |
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switch (saddr) { |
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case 0: |
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if (!(val & DMA_INTREN)) |
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pic_set_irq_new(s->intctl, s->espirq, 0); |
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if (val & DMA_RESET) { |
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esp_reset(s->esp_opaque); |
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} else if (val & 0x40) { |
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val &= ~0x40; |
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} else if (val == 0) |
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val = 0x40; |
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val &= 0x0fffffff; |
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val |= DMA_VER; |
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break; |
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case 1: |
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s->dmaregs[0] |= DMA_LOADED; |
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break; |
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case 4: |
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if (!(val & DMA_INTREN)) |
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pic_set_irq_new(s->intctl, s->leirq, 0); |
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if (val & DMA_RESET) |
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pcnet_h_reset(s->lance_opaque); |
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val &= 0x0fffffff; |
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val |= DMA_VER; |
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break; |
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default: |
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break; |
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} |
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s->dmaregs[saddr] = val; |
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} |
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static CPUReadMemoryFunc *dma_mem_read[3] = { |
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dma_mem_readl, |
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dma_mem_readl, |
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dma_mem_readl, |
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}; |
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static CPUWriteMemoryFunc *dma_mem_write[3] = { |
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dma_mem_writel, |
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dma_mem_writel, |
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dma_mem_writel, |
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}; |
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static void dma_reset(void *opaque) |
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{ |
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DMAState *s = opaque; |
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memset(s->dmaregs, 0, DMA_REGS * 4); |
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s->dmaregs[0] = DMA_VER; |
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s->dmaregs[4] = DMA_VER; |
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} |
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static void dma_save(QEMUFile *f, void *opaque) |
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{ |
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DMAState *s = opaque; |
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unsigned int i; |
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for (i = 0; i < DMA_REGS; i++) |
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qemu_put_be32s(f, &s->dmaregs[i]); |
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} |
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static int dma_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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DMAState *s = opaque; |
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unsigned int i; |
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if (version_id != 1) |
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return -EINVAL; |
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for (i = 0; i < DMA_REGS; i++) |
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qemu_get_be32s(f, &s->dmaregs[i]); |
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return 0; |
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} |
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void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu, void *intctl) |
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{ |
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DMAState *s; |
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int dma_io_memory; |
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s = qemu_mallocz(sizeof(DMAState)); |
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if (!s) |
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return NULL; |
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s->espirq = espirq; |
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s->leirq = leirq; |
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s->iommu = iommu; |
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s->intctl = intctl; |
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dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s); |
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cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory); |
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register_savevm("sparc32_dma", daddr, 1, dma_save, dma_load, s); |
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qemu_register_reset(dma_reset, s); |
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return s; |
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} |
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void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque, |
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void *lance_opaque) |
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{ |
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DMAState *s = opaque; |
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s->esp_opaque = esp_opaque; |
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s->lance_opaque = lance_opaque; |
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} |
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