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@ -65,6 +65,7 @@ |
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#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) |
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typedef struct ParallelState { |
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MemoryRegion iomem; |
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uint8_t dataw; |
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uint8_t datar; |
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uint8_t status; |
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@ -555,24 +556,20 @@ static void parallel_mm_writel (void *opaque, |
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parallel_ioport_write_sw(s, addr >> s->it_shift, value); |
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} |
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static CPUReadMemoryFunc * const parallel_mm_read_sw[] = { |
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¶llel_mm_readb, |
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¶llel_mm_readw, |
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¶llel_mm_readl, |
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}; |
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static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = { |
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¶llel_mm_writeb, |
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¶llel_mm_writew, |
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¶llel_mm_writel, |
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static const MemoryRegionOps parallel_mm_ops = { |
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.old_mmio = { |
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.read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, |
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.write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, |
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}, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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/* If fd is zero, it means that the parallel device uses the console */ |
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bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, |
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bool parallel_mm_init(MemoryRegion *address_space, |
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target_phys_addr_t base, int it_shift, qemu_irq irq, |
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CharDriverState *chr) |
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{ |
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ParallelState *s; |
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int io_sw; |
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s = g_malloc0(sizeof(ParallelState)); |
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s->irq = irq; |
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@ -580,9 +577,9 @@ bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, |
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s->it_shift = it_shift; |
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qemu_register_reset(parallel_reset, s); |
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io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, |
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s, DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(base, 8 << it_shift, io_sw); |
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memory_region_init_io(&s->iomem, ¶llel_mm_ops, s, |
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"parallel", 8 << it_shift); |
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memory_region_add_subregion(address_space, base, &s->iomem); |
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return true; |
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} |
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