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This patch adds minimal support for AXP-209 PMU. Most important is chip ID since U-Boot SPL expects version 0x1. Besides the chip ID register, reset values for two more registers used by A10 U-Boot SPL are covered. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>pull/229/head
Strahinja Jankovic
4 years ago
committed by
Peter Maydell
Peter Maydell
5 changed files with 250 additions and 0 deletions
@ -0,0 +1,238 @@ |
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/*
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* AXP-209 PMU Emulation |
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* |
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* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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* DEALINGS IN THE SOFTWARE. |
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* |
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* SPDX-License-Identifier: MIT |
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*/ |
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#include "qemu/osdep.h" |
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#include "qemu/log.h" |
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#include "trace.h" |
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#include "hw/i2c/i2c.h" |
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#include "migration/vmstate.h" |
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#define TYPE_AXP209_PMU "axp209_pmu" |
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#define AXP209(obj) \ |
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OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU) |
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/* registers */ |
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enum { |
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REG_POWER_STATUS = 0x0u, |
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REG_OPERATING_MODE, |
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REG_OTG_VBUS_STATUS, |
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REG_CHIP_VERSION, |
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REG_DATA_CACHE_0, |
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REG_DATA_CACHE_1, |
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REG_DATA_CACHE_2, |
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REG_DATA_CACHE_3, |
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REG_DATA_CACHE_4, |
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REG_DATA_CACHE_5, |
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REG_DATA_CACHE_6, |
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REG_DATA_CACHE_7, |
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REG_DATA_CACHE_8, |
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REG_DATA_CACHE_9, |
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REG_DATA_CACHE_A, |
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REG_DATA_CACHE_B, |
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REG_POWER_OUTPUT_CTRL = 0x12u, |
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REG_DC_DC2_OUT_V_CTRL = 0x23u, |
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REG_DC_DC2_DVS_CTRL = 0x25u, |
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REG_DC_DC3_OUT_V_CTRL = 0x27u, |
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REG_LDO2_4_OUT_V_CTRL, |
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REG_LDO3_OUT_V_CTRL, |
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REG_VBUS_CH_MGMT = 0x30u, |
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REG_SHUTDOWN_V_CTRL, |
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REG_SHUTDOWN_CTRL, |
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REG_CHARGE_CTRL_1, |
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REG_CHARGE_CTRL_2, |
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REG_SPARE_CHARGE_CTRL, |
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REG_PEK_KEY_CTRL, |
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REG_DC_DC_FREQ_SET, |
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REG_CHR_TEMP_TH_SET, |
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REG_CHR_HIGH_TEMP_TH_CTRL, |
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REG_IPSOUT_WARN_L1, |
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REG_IPSOUT_WARN_L2, |
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REG_DISCHR_TEMP_TH_SET, |
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REG_DISCHR_HIGH_TEMP_TH_CTRL, |
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REG_IRQ_BANK_1_CTRL = 0x40u, |
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REG_IRQ_BANK_2_CTRL, |
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REG_IRQ_BANK_3_CTRL, |
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REG_IRQ_BANK_4_CTRL, |
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REG_IRQ_BANK_5_CTRL, |
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REG_IRQ_BANK_1_STAT = 0x48u, |
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REG_IRQ_BANK_2_STAT, |
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REG_IRQ_BANK_3_STAT, |
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REG_IRQ_BANK_4_STAT, |
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REG_IRQ_BANK_5_STAT, |
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REG_ADC_ACIN_V_H = 0x56u, |
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REG_ADC_ACIN_V_L, |
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REG_ADC_ACIN_CURR_H, |
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REG_ADC_ACIN_CURR_L, |
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REG_ADC_VBUS_V_H, |
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REG_ADC_VBUS_V_L, |
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REG_ADC_VBUS_CURR_H, |
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REG_ADC_VBUS_CURR_L, |
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REG_ADC_INT_TEMP_H, |
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REG_ADC_INT_TEMP_L, |
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REG_ADC_TEMP_SENS_V_H = 0x62u, |
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REG_ADC_TEMP_SENS_V_L, |
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REG_ADC_BAT_V_H = 0x78u, |
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REG_ADC_BAT_V_L, |
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REG_ADC_BAT_DISCHR_CURR_H, |
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REG_ADC_BAT_DISCHR_CURR_L, |
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REG_ADC_BAT_CHR_CURR_H, |
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REG_ADC_BAT_CHR_CURR_L, |
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REG_ADC_IPSOUT_V_H, |
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REG_ADC_IPSOUT_V_L, |
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REG_DC_DC_MOD_SEL = 0x80u, |
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REG_ADC_EN_1, |
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REG_ADC_EN_2, |
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REG_ADC_SR_CTRL, |
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REG_ADC_IN_RANGE, |
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REG_GPIO1_ADC_IRQ_RISING_TH, |
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REG_GPIO1_ADC_IRQ_FALLING_TH, |
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REG_TIMER_CTRL = 0x8au, |
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REG_VBUS_CTRL_MON_SRP, |
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REG_OVER_TEMP_SHUTDOWN = 0x8fu, |
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REG_GPIO0_FEAT_SET, |
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REG_GPIO_OUT_HIGH_SET, |
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REG_GPIO1_FEAT_SET, |
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REG_GPIO2_FEAT_SET, |
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REG_GPIO_SIG_STATE_SET_MON, |
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REG_GPIO3_SET, |
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REG_COULOMB_CNTR_CTRL = 0xb8u, |
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REG_POWER_MEAS_RES, |
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NR_REGS |
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}; |
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#define AXP209_CHIP_VERSION_ID (0x01) |
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#define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16) |
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#define AXP209_IRQ_BANK_1_CTRL_RESET (0xd8) |
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/* A simple I2C slave which returns values of ID or CNT register. */ |
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typedef struct AXP209I2CState { |
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/*< private >*/ |
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I2CSlave i2c; |
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/*< public >*/ |
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uint8_t regs[NR_REGS]; /* peripheral registers */ |
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uint8_t ptr; /* current register index */ |
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uint8_t count; /* counter used for tx/rx */ |
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} AXP209I2CState; |
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/* Reset all counters and load ID register */ |
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static void axp209_reset_enter(Object *obj, ResetType type) |
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{ |
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AXP209I2CState *s = AXP209(obj); |
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memset(s->regs, 0, NR_REGS); |
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s->ptr = 0; |
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s->count = 0; |
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s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID; |
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s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET; |
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s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET; |
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} |
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/* Handle events from master. */ |
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static int axp209_event(I2CSlave *i2c, enum i2c_event event) |
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{ |
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AXP209I2CState *s = AXP209(i2c); |
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s->count = 0; |
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return 0; |
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} |
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/* Called when master requests read */ |
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static uint8_t axp209_rx(I2CSlave *i2c) |
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{ |
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AXP209I2CState *s = AXP209(i2c); |
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uint8_t ret = 0xff; |
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if (s->ptr < NR_REGS) { |
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ret = s->regs[s->ptr++]; |
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} |
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trace_axp209_rx(s->ptr - 1, ret); |
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return ret; |
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} |
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/*
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* Called when master sends write. |
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* Update ptr with byte 0, then perform write with second byte. |
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*/ |
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static int axp209_tx(I2CSlave *i2c, uint8_t data) |
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{ |
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AXP209I2CState *s = AXP209(i2c); |
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if (s->count == 0) { |
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/* Store register address */ |
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s->ptr = data; |
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s->count++; |
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trace_axp209_select(data); |
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} else { |
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trace_axp209_tx(s->ptr, data); |
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if (s->ptr == REG_DC_DC2_OUT_V_CTRL) { |
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s->regs[s->ptr++] = data; |
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} |
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} |
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return 0; |
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} |
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static const VMStateDescription vmstate_axp209 = { |
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.name = TYPE_AXP209_PMU, |
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.version_id = 1, |
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.fields = (VMStateField[]) { |
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VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS), |
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VMSTATE_UINT8(count, AXP209I2CState), |
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VMSTATE_UINT8(ptr, AXP209I2CState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void axp209_class_init(ObjectClass *oc, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(oc); |
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I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc); |
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ResettableClass *rc = RESETTABLE_CLASS(oc); |
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rc->phases.enter = axp209_reset_enter; |
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dc->vmsd = &vmstate_axp209; |
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isc->event = axp209_event; |
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isc->recv = axp209_rx; |
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isc->send = axp209_tx; |
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} |
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static const TypeInfo axp209_info = { |
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.name = TYPE_AXP209_PMU, |
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.parent = TYPE_I2C_SLAVE, |
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.instance_size = sizeof(AXP209I2CState), |
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.class_init = axp209_class_init |
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}; |
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static void axp209_register_devices(void) |
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{ |
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type_register_static(&axp209_info); |
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} |
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type_init(axp209_register_devices); |
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