target/or1k: Rename from openrisc

This is the minimal change beginning with TARGET_ARCH in
configs/targets/or1k-* from openrisc to or1k, then adjust
TARGET_OR1K, QEMU_ARCH_OR1K, directory names,
and meson.build to match.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260205030244.266447-2-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

MAINTAINERS

@@ -303,7 +303,7 @@ OpenRISC TCG CPUs
 M: Stafford Horne <shorne@gmail.com>
 S: Odd Fixes
 F: docs/system/openrisc/cpu-features.rst
-F: target/openrisc/
+F: target/or1k/
 F: hw/openrisc/
 F: include/hw/openrisc/
 F: tests/functional/or1k/meson.build

configs/targets/or1k-linux-user.mak

@@ -1,4 +1,4 @@
-TARGET_ARCH=openrisc
+TARGET_ARCH=or1k
 TARGET_BIG_ENDIAN=y
 TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat
 TARGET_SYSTBL=syscall.tbl

configs/targets/or1k-softmmu.mak

@@ -1,4 +1,4 @@
-TARGET_ARCH=openrisc
+TARGET_ARCH=or1k
 TARGET_BIG_ENDIAN=y
 # needed by boot.c and all boards
 TARGET_NEED_FDT=y

hw/openrisc/Kconfig

@@ -1,7 +1,7 @@
 config OR1K_SIM
     bool
     default y
-    depends on OPENRISC
+    depends on OR1K
     select DEVICE_TREE
     select SERIAL_MM
     select OPENCORES_ETH
@@ -11,7 +11,7 @@ config OR1K_SIM
 config OR1K_VIRT
     bool
     default y
-    depends on OPENRISC
+    depends on OR1K
     imply PCI_DEVICES
     imply VIRTIO_VGA
     imply TEST_DEVICES

hw/openrisc/meson.build

@@ -4,4 +4,4 @@ openrisc_ss.add(files('boot.c'))
 openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c'))
 openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: files('virt.c'))
 
-hw_arch += {'openrisc': openrisc_ss}
+hw_arch += {'or1k': openrisc_ss}

include/exec/poison.h

@@ -21,7 +21,7 @@
 #pragma GCC poison TARGET_ABI_MIPSO32
 #pragma GCC poison TARGET_MIPS64
 #pragma GCC poison TARGET_ABI_MIPSN64
-#pragma GCC poison TARGET_OPENRISC
+#pragma GCC poison TARGET_OR1K
 #pragma GCC poison TARGET_PPC
 #pragma GCC poison TARGET_PPC64
 #pragma GCC poison TARGET_ABI32

include/system/arch_init.h

@@ -15,7 +15,7 @@ enum {
     QEMU_ARCH_SH4 = (1 << 10),
     QEMU_ARCH_SPARC = (1 << 11),
     QEMU_ARCH_XTENSA = (1 << 12),
-    QEMU_ARCH_OPENRISC = (1 << 13),
+    QEMU_ARCH_OR1K = (1 << 13),
     QEMU_ARCH_TRICORE = (1 << 16),
     QEMU_ARCH_HPPA = (1 << 18),
     QEMU_ARCH_RISCV = (1 << 19),

include/user/abitypes.h

@@ -22,7 +22,7 @@
 
 #if (defined(TARGET_I386) && !defined(TARGET_X86_64)) \
     || defined(TARGET_SH4) \
-    || defined(TARGET_OPENRISC) \
+    || defined(TARGET_OR1K) \
     || defined(TARGET_MICROBLAZE)
 #define ABI_LLONG_ALIGNMENT 4
 #endif

linux-user/meson.build

@@ -50,7 +50,7 @@ subdir('m68k')
 subdir('microblaze')
 subdir('mips64')
 subdir('mips')
-subdir('openrisc')
+subdir('or1k')
 subdir('ppc')
 subdir('riscv')
 subdir('s390x')

linux-user/openrisc/meson.build

@@ -1,5 +0,0 @@
-syscall_nr_generators += {
-  'openrisc': generator(sh,
-                      arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],
-                      output: '@BASENAME@_nr.h')
-}

linux-user/or1k/meson.build

@@ -0,0 +1,5 @@
+syscall_nr_generators += {
+  'or1k': generator(sh,
+                    arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],
+                    output: '@BASENAME@_nr.h')
+}

linux-user/syscall_defs.h

@@ -72,7 +72,7 @@
 
 #if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4)  \
     || defined(TARGET_M68K)                                             \
-    || defined(TARGET_S390X) || defined(TARGET_OPENRISC)                \
+    || defined(TARGET_S390X) || defined(TARGET_OR1K)                    \
     || defined(TARGET_RISCV)                                            \
     || defined(TARGET_XTENSA) || defined(TARGET_LOONGARCH64)
 
@@ -1976,7 +1976,7 @@ struct target_stat64  {
     abi_ulong __unused5;
 };
 
-#elif defined(TARGET_OPENRISC) \
+#elif defined(TARGET_OR1K) \
     || defined(TARGET_RISCV) || defined(TARGET_HEXAGON) || defined(TARGET_LOONGARCH)
 
 /* These are the asm-generic versions of the stat and stat64 structures */

system/qdev-monitor.c

@@ -62,7 +62,7 @@ typedef struct QDevAlias
                               QEMU_ARCH_I386 | \
                               QEMU_ARCH_LOONGARCH | \
                               QEMU_ARCH_MIPS | \
-                              QEMU_ARCH_OPENRISC | \
+                              QEMU_ARCH_OR1K | \
                               QEMU_ARCH_PPC | \
                               QEMU_ARCH_RISCV | \
                               QEMU_ARCH_SH4 | \

target/Kconfig

@@ -7,7 +7,7 @@ source loongarch/Kconfig
 source m68k/Kconfig
 source microblaze/Kconfig
 source mips/Kconfig
-source openrisc/Kconfig
+source or1k/Kconfig
 source ppc/Kconfig
 source riscv/Kconfig
 source rx/Kconfig

target/meson.build

@@ -8,7 +8,7 @@ subdir('loongarch')
 subdir('m68k')
 subdir('microblaze')
 subdir('mips')
-subdir('openrisc')
+subdir('or1k')
 subdir('ppc')
 subdir('riscv')
 subdir('rx')

target/openrisc/Kconfig → target/or1k/Kconfig

@@ -1,3 +1,3 @@
-config OPENRISC
+config OR1K
     bool
     select DEVICE_TREE # needed by boot.c

target/openrisc/meson.build → target/or1k/meson.build

@@ -21,5 +21,5 @@ openrisc_system_ss.add(files(
   'mmu.c',
 ))
 
-target_arch += {'openrisc': openrisc_ss}
-target_common_system_arch += {'openrisc': openrisc_system_ss}
+target_arch += {'or1k': openrisc_ss}
+target_common_system_arch += {'or1k': openrisc_system_ss}