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target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-85-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
pull/294/head
Richard Henderson 9 months ago
committed by Peter Maydell
parent
ab6bf3d93d
commit
5b334d17e6
4 changed files with 65 additions and 0 deletions
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  1. 15
      target/arm/tcg/helper-sve.h
  2. 5
      target/arm/tcg/sve.decode
  3. 42
      target/arm/tcg/sve_helper.c
  4. 3
      target/arm/tcg/translate-sve.c

15
target/arm/tcg/helper-sve.h
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@ -2955,3 +2955,18 @@ DEF_HELPER_FLAGS_4(sve2p1_uminqv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_uminqv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(pext, TCG_CALL_NO_RWG, void, ptr, i32, i32)
DEF_HELPER_FLAGS_4(sve2p1_orqv_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_orqv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_orqv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_orqv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_eorqv_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_eorqv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_eorqv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_eorqv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_andqv_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_andqv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_andqv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2p1_andqv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

5
target/arm/tcg/sve.decode
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@ -326,6 +326,11 @@ ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
# SVE2.1 bitwise logical reduction (quadwords)
ORQV 00000100 .. 011 100 001 ... ..... ..... @rd_pg_rn
EORQV 00000100 .. 011 101 001 ... ..... ..... @rd_pg_rn
ANDQV 00000100 .. 011 110 001 ... ..... ..... @rd_pg_rn
# SVE constructive prefix (predicated)
MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn

42
target/arm/tcg/sve_helper.c
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@ -123,6 +123,11 @@ static inline uint64_t expand_pred_s(uint8_t byte)
return word[byte & 0x11];
}
static inline uint64_t expand_pred_d(uint8_t byte)
{
return -(uint64_t)(byte & 1);
}
#define LOGICAL_PPPP(NAME, FUNC) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \
{ \
@ -206,6 +211,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \
#define DO_EOR(N, M) (N ^ M)
#define DO_ORR(N, M) (N | M)
#define DO_BIC(N, M) (N & ~M)
#define DO_ORC(N, M) (N | ~M)
#define DO_ADD(N, M) (N + M)
#define DO_SUB(N, M) (N - M)
#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
@ -1900,10 +1906,46 @@ DO_ZZI(sve_umini_d, uint64_t, DO_MIN)
#undef DO_ZZI
#define DO_LOGIC_QV(NAME, SUFF, INIT, VOP, POP) \
void HELPER(NAME ## _ ## SUFF)(void *vd, void *vn, void *vg, uint32_t desc) \
{ \
unsigned seg = simd_oprsz(desc) / 16; \
uint64_t r0 = INIT, r1 = INIT; \
for (unsigned s = 0; s < seg; s++) { \
uint64_t p0 = expand_pred_##SUFF(*(uint8_t *)(vg + H1(s * 2))); \
uint64_t p1 = expand_pred_##SUFF(*(uint8_t *)(vg + H1(s * 2 + 1))); \
uint64_t v0 = *(uint64_t *)(vn + s * 16); \
uint64_t v1 = *(uint64_t *)(vn + s * 16 + 8); \
v0 = POP(v0, p0), v1 = POP(v1, p1); \
r0 = VOP(r0, v0), r1 = VOP(r1, v1); \
} \
*(uint64_t *)(vd + 0) = r0; \
*(uint64_t *)(vd + 8) = r1; \
clear_tail(vd, 16, simd_maxsz(desc)); \
}
DO_LOGIC_QV(sve2p1_orqv, b, 0, DO_ORR, DO_AND)
DO_LOGIC_QV(sve2p1_orqv, h, 0, DO_ORR, DO_AND)
DO_LOGIC_QV(sve2p1_orqv, s, 0, DO_ORR, DO_AND)
DO_LOGIC_QV(sve2p1_orqv, d, 0, DO_ORR, DO_AND)
DO_LOGIC_QV(sve2p1_eorqv, b, 0, DO_EOR, DO_AND)
DO_LOGIC_QV(sve2p1_eorqv, h, 0, DO_EOR, DO_AND)
DO_LOGIC_QV(sve2p1_eorqv, s, 0, DO_EOR, DO_AND)
DO_LOGIC_QV(sve2p1_eorqv, d, 0, DO_EOR, DO_AND)
DO_LOGIC_QV(sve2p1_andqv, b, -1, DO_AND, DO_ORC)
DO_LOGIC_QV(sve2p1_andqv, h, -1, DO_AND, DO_ORC)
DO_LOGIC_QV(sve2p1_andqv, s, -1, DO_AND, DO_ORC)
DO_LOGIC_QV(sve2p1_andqv, d, -1, DO_AND, DO_ORC)
#undef DO_LOGIC_QV
#undef DO_AND
#undef DO_ORR
#undef DO_EOR
#undef DO_BIC
#undef DO_ORC
#undef DO_ADD
#undef DO_SUB
#undef DO_MAX

3
target/arm/tcg/translate-sve.c
View File

@ -778,6 +778,9 @@ DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz)
DO_ZPZ(ABS, aa64_sve, sve_abs)
DO_ZPZ(NEG, aa64_sve, sve_neg)
DO_ZPZ(RBIT, aa64_sve, sve_rbit)
DO_ZPZ(ORQV, aa64_sme2p1_or_sve2p1, sve2p1_orqv)
DO_ZPZ(EORQV, aa64_sme2p1_or_sve2p1, sve2p1_eorqv)
DO_ZPZ(ANDQV, aa64_sme2p1_or_sve2p1, sve2p1_andqv)
static gen_helper_gvec_3 * const fabs_fns[4] = {
NULL, gen_helper_sve_fabs_h,

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