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Add Artist graphics Fix main memory allocation Improve LDCW emulation wrt real hw -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAl4vMa8dHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/3PwgAmw+Q/rT2kT19vMHd 1XHjK1WJNx4SFRQWxwMsbxDoWyFslUZH5G0z0l7zB1eG7ONEZBttUVyOVnyPH5Q5 DUmfHMvS838lHkLU+OWPbfbwB8WZzfwUwHi3u8ljRBM52RZYf+m69/yMRd8H+PmF bDq3zCviAqvIIvWdSmPEfsx9v4WmrE2aULkKN2aZsHYHzkuHmPWfSYe2dzxTcO3z zDXoscUVmtVk29jpwHV4gM7zl9uk8jyvfeeB2fZ2/EY4qgZ+iHrhtnglfCdCCDr0 G1Q5vugJ70lFkYM2EzpyU+leHUREXN7xqYm5Iycv4neO+aS2FFkNpxCZvPofihHo rUFcOw== =kj86 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-pa-20200127' into staging Improve LASI emulation Add Artist graphics Fix main memory allocation Improve LDCW emulation wrt real hw # gpg: Signature made Mon 27 Jan 2020 18:53:35 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-pa-20200127: target/hppa: Allow, but diagnose, LDCW aligned only mod 4 hw/hppa/machine: Map the PDC memory region with higher priority hw/hppa/machine: Restrict the total memory size to 3GB hw/hppa/machine: Correctly check the firmware is in PDC range hppa: Add emulation of Artist graphics seabios-hppa: update to latest version hppa: Switch to tulip NIC by default hppa: add emulation of LASI PS2 controllers ps2: accept 'Set Key Make and Break' commands hppa: Add support for LASI chip with i82596 NIC hw/hppa/dino.c: Improve emulation of Dino PCI chip Signed-off-by: Peter Maydell <peter.maydell@linaro.org>pull/89/head
Peter Maydell
6 years ago
33 changed files with 3351 additions and 28 deletions
File diff suppressed because it is too large
@ -1 +1 @@ |
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obj-$(CONFIG_DINO) += pci.o machine.o dino.o |
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obj-$(CONFIG_DINO) += pci.o machine.o dino.o lasi.o |
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@ -0,0 +1,368 @@ |
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/*
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* HP-PARISC Lasi chipset emulation. |
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* |
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* (C) 2019 by Helge Deller <deller@gmx.de> |
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* |
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* This work is licensed under the GNU GPL license version 2 or later. |
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* |
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* Documentation available at: |
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* https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
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*/ |
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#include "qemu/osdep.h" |
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#include "qemu/units.h" |
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#include "qapi/error.h" |
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#include "cpu.h" |
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#include "trace.h" |
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#include "hw/hw.h" |
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#include "hw/irq.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/runstate.h" |
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#include "hppa_sys.h" |
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#include "hw/net/lasi_82596.h" |
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#include "hw/char/parallel.h" |
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#include "hw/char/serial.h" |
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#include "hw/input/lasips2.h" |
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#include "exec/address-spaces.h" |
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#include "migration/vmstate.h" |
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|
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#define TYPE_LASI_CHIP "lasi-chip" |
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|
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#define LASI_IRR 0x00 /* RO */ |
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#define LASI_IMR 0x04 |
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#define LASI_IPR 0x08 |
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#define LASI_ICR 0x0c |
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#define LASI_IAR 0x10 |
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|
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#define LASI_PCR 0x0C000 /* LASI Power Control register */ |
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#define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ |
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#define LASI_VER 0x0C008 /* LASI Version Control register */ |
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#define LASI_IORESET 0x0C00C /* LASI I/O Reset register */ |
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#define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */ |
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#define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */ |
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#define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */ |
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#define LASI_BIT(x) (1ul << (x)) |
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#define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \ |
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| LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \ |
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| LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \ |
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| LASI_BIT(26)) |
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#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */ |
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#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */ |
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#define LASI_CHIP(obj) \ |
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OBJECT_CHECK(LasiState, (obj), TYPE_LASI_CHIP) |
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#define LASI_RTC_HPA (LASI_HPA + 0x9000) |
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typedef struct LasiState { |
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PCIHostState parent_obj; |
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uint32_t irr; |
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uint32_t imr; |
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uint32_t ipr; |
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uint32_t icr; |
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uint32_t iar; |
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uint32_t errlog; |
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uint32_t amr; |
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uint32_t rtc; |
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time_t rtc_ref; |
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MemoryRegion this_mem; |
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} LasiState; |
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static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, |
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unsigned size, bool is_write, |
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MemTxAttrs attrs) |
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{ |
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bool ret = false; |
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switch (addr) { |
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case LASI_IRR: |
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case LASI_IMR: |
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case LASI_IPR: |
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case LASI_ICR: |
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case LASI_IAR: |
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case (LASI_LAN_HPA - LASI_HPA): |
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case (LASI_LPT_HPA - LASI_HPA): |
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case (LASI_UART_HPA - LASI_HPA): |
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case (LASI_RTC_HPA - LASI_HPA): |
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case LASI_PCR ... LASI_AMR: |
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ret = true; |
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} |
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trace_lasi_chip_mem_valid(addr, ret); |
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return ret; |
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} |
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static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, |
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uint64_t *data, unsigned size, |
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MemTxAttrs attrs) |
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{ |
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LasiState *s = opaque; |
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MemTxResult ret = MEMTX_OK; |
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uint32_t val; |
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switch (addr) { |
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case LASI_IRR: |
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val = s->irr; |
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break; |
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case LASI_IMR: |
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val = s->imr; |
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break; |
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case LASI_IPR: |
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val = s->ipr; |
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/* Any read to IPR clears the register. */ |
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s->ipr = 0; |
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break; |
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case LASI_ICR: |
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val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */ |
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break; |
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case LASI_IAR: |
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val = s->iar; |
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break; |
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case (LASI_LAN_HPA - LASI_HPA): |
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case (LASI_LPT_HPA - LASI_HPA): |
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case (LASI_UART_HPA - LASI_HPA): |
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val = 0; |
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break; |
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case (LASI_RTC_HPA - LASI_HPA): |
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val = time(NULL); |
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val += s->rtc_ref; |
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break; |
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case LASI_PCR: |
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case LASI_VER: /* only version 0 existed. */ |
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case LASI_IORESET: |
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val = 0; |
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break; |
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case LASI_ERRLOG: |
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val = s->errlog; |
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break; |
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case LASI_AMR: |
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val = s->amr; |
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break; |
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default: |
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/* Controlled by lasi_chip_mem_valid above. */ |
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g_assert_not_reached(); |
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} |
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trace_lasi_chip_read(addr, val); |
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*data = val; |
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return ret; |
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} |
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static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, |
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uint64_t val, unsigned size, |
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MemTxAttrs attrs) |
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{ |
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LasiState *s = opaque; |
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trace_lasi_chip_write(addr, val); |
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switch (addr) { |
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case LASI_IRR: |
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/* read-only. */ |
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break; |
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case LASI_IMR: |
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s->imr = val; /* 0x20 ?? */ |
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assert((val & LASI_IRQ_BITS) == val); |
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break; |
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case LASI_IPR: |
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/* Any write to IPR clears the register. */ |
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s->ipr = 0; |
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break; |
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case LASI_ICR: |
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s->icr = val; |
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/* if (val & ICR_TOC_BIT) issue_toc(); */ |
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break; |
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case LASI_IAR: |
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s->iar = val; |
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break; |
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case (LASI_LAN_HPA - LASI_HPA): |
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/* XXX: reset LAN card */ |
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break; |
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case (LASI_LPT_HPA - LASI_HPA): |
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/* XXX: reset parallel port */ |
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break; |
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case (LASI_UART_HPA - LASI_HPA): |
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/* XXX: reset serial port */ |
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break; |
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case (LASI_RTC_HPA - LASI_HPA): |
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s->rtc_ref = val - time(NULL); |
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break; |
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|
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case LASI_PCR: |
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if (val == 0x02) /* immediately power off */ |
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
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break; |
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case LASI_ERRLOG: |
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s->errlog = val; |
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break; |
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case LASI_VER: |
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/* read-only. */ |
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break; |
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case LASI_IORESET: |
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break; /* XXX: TODO: Reset various devices. */ |
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case LASI_AMR: |
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s->amr = val; |
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break; |
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default: |
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/* Controlled by lasi_chip_mem_valid above. */ |
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g_assert_not_reached(); |
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} |
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return MEMTX_OK; |
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} |
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static const MemoryRegionOps lasi_chip_ops = { |
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.read_with_attrs = lasi_chip_read_with_attrs, |
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.write_with_attrs = lasi_chip_write_with_attrs, |
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.endianness = DEVICE_BIG_ENDIAN, |
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.valid = { |
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.min_access_size = 1, |
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.max_access_size = 4, |
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.accepts = lasi_chip_mem_valid, |
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}, |
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.impl = { |
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.min_access_size = 1, |
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.max_access_size = 4, |
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}, |
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}; |
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static const VMStateDescription vmstate_lasi = { |
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.name = "Lasi", |
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.version_id = 1, |
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.minimum_version_id = 1, |
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32(irr, LasiState), |
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VMSTATE_UINT32(imr, LasiState), |
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VMSTATE_UINT32(ipr, LasiState), |
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VMSTATE_UINT32(icr, LasiState), |
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VMSTATE_UINT32(iar, LasiState), |
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VMSTATE_UINT32(errlog, LasiState), |
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VMSTATE_UINT32(amr, LasiState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void lasi_set_irq(void *opaque, int irq, int level) |
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{ |
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LasiState *s = opaque; |
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uint32_t bit = 1u << irq; |
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if (level) { |
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s->ipr |= bit; |
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if (bit & s->imr) { |
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uint32_t iar = s->iar; |
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s->irr |= bit; |
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if ((s->icr & ICR_BUS_ERROR_BIT) == 0) { |
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stl_be_phys(&address_space_memory, iar & -32, iar & 31); |
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} |
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} |
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} |
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} |
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static int lasi_get_irq(unsigned long hpa) |
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{ |
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switch (hpa) { |
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case LASI_HPA: |
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return 14; |
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case LASI_UART_HPA: |
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return 5; |
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case LASI_LPT_HPA: |
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return 7; |
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case LASI_LAN_HPA: |
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return 8; |
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case LASI_SCSI_HPA: |
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return 9; |
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case LASI_AUDIO_HPA: |
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return 13; |
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case LASI_PS2KBD_HPA: |
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case LASI_PS2MOU_HPA: |
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return 26; |
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default: |
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g_assert_not_reached(); |
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} |
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} |
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DeviceState *lasi_init(MemoryRegion *address_space) |
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{ |
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DeviceState *dev; |
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LasiState *s; |
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dev = qdev_create(NULL, TYPE_LASI_CHIP); |
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s = LASI_CHIP(dev); |
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s->iar = CPU_HPA + 3; |
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/* Lasi access from main memory. */ |
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memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops, |
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s, "lasi", 0x100000); |
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memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem); |
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qdev_init_nofail(dev); |
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/* LAN */ |
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if (enable_lasi_lan()) { |
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qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s, |
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lasi_get_irq(LASI_LAN_HPA)); |
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lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq); |
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} |
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/* Parallel port */ |
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qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s, |
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lasi_get_irq(LASI_LPT_HPA)); |
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parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0, |
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lpt_irq, parallel_hds[0]); |
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/* Real time clock (RTC), it's only one 32-bit counter @9000 */ |
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s->rtc = time(NULL); |
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s->rtc_ref = 0; |
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if (serial_hd(1)) { |
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/* Serial port */ |
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qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s, |
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lasi_get_irq(LASI_UART_HPA)); |
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serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0, |
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serial_irq, 8000000 / 16, |
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serial_hd(0), DEVICE_NATIVE_ENDIAN); |
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} |
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|
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/* PS/2 Keyboard/Mouse */ |
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qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s, |
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lasi_get_irq(LASI_PS2KBD_HPA)); |
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lasips2_init(address_space, LASI_PS2KBD_HPA, ps2kbd_irq); |
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return dev; |
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} |
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static void lasi_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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dc->vmsd = &vmstate_lasi; |
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} |
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static const TypeInfo lasi_pcihost_info = { |
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.name = TYPE_LASI_CHIP, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(LasiState), |
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.class_init = lasi_class_init, |
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}; |
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static void lasi_register_types(void) |
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{ |
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type_register_static(&lasi_pcihost_info); |
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} |
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type_init(lasi_register_types) |
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@ -0,0 +1,291 @@ |
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/*
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* QEMU HP Lasi PS/2 interface emulation |
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* |
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* Copyright (c) 2019 Sven Schnelle |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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#include "qemu/osdep.h" |
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#include "qemu/log.h" |
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#include "hw/qdev-properties.h" |
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#include "hw/hw.h" |
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#include "hw/input/ps2.h" |
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#include "hw/input/lasips2.h" |
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#include "hw/sysbus.h" |
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#include "exec/hwaddr.h" |
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#include "sysemu/sysemu.h" |
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#include "trace.h" |
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#include "exec/address-spaces.h" |
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#include "migration/vmstate.h" |
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#include "hw/irq.h" |
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struct LASIPS2State; |
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typedef struct LASIPS2Port { |
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struct LASIPS2State *parent; |
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MemoryRegion reg; |
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void *dev; |
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uint8_t id; |
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uint8_t control; |
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uint8_t buf; |
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bool loopback_rbne; |
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bool irq; |
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} LASIPS2Port; |
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typedef struct LASIPS2State { |
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LASIPS2Port kbd; |
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LASIPS2Port mouse; |
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qemu_irq irq; |
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} LASIPS2State; |
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static const VMStateDescription vmstate_lasips2 = { |
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.name = "lasips2", |
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.version_id = 0, |
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.minimum_version_id = 0, |
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.fields = (VMStateField[]) { |
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VMSTATE_UINT8(kbd.control, LASIPS2State), |
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VMSTATE_UINT8(kbd.id, LASIPS2State), |
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VMSTATE_BOOL(kbd.irq, LASIPS2State), |
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VMSTATE_UINT8(mouse.control, LASIPS2State), |
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VMSTATE_UINT8(mouse.id, LASIPS2State), |
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VMSTATE_BOOL(mouse.irq, LASIPS2State), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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typedef enum { |
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REG_PS2_ID = 0, |
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REG_PS2_RCVDATA = 4, |
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REG_PS2_CONTROL = 8, |
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REG_PS2_STATUS = 12, |
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} lasips2_read_reg_t; |
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typedef enum { |
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REG_PS2_RESET = 0, |
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REG_PS2_XMTDATA = 4, |
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} lasips2_write_reg_t; |
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typedef enum { |
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LASIPS2_CONTROL_ENABLE = 0x01, |
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LASIPS2_CONTROL_LOOPBACK = 0x02, |
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LASIPS2_CONTROL_DIAG = 0x20, |
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LASIPS2_CONTROL_DATDIR = 0x40, |
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LASIPS2_CONTROL_CLKDIR = 0x80, |
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} lasips2_control_reg_t; |
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typedef enum { |
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LASIPS2_STATUS_RBNE = 0x01, |
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LASIPS2_STATUS_TBNE = 0x02, |
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LASIPS2_STATUS_TERR = 0x04, |
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LASIPS2_STATUS_PERR = 0x08, |
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LASIPS2_STATUS_CMPINTR = 0x10, |
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LASIPS2_STATUS_DATSHD = 0x40, |
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LASIPS2_STATUS_CLKSHD = 0x80, |
|||
} lasips2_status_reg_t; |
|||
|
|||
static const char *artist_read_reg_name(uint64_t addr) |
|||
{ |
|||
switch (addr & 0xc) { |
|||
case REG_PS2_ID: |
|||
return " PS2_ID"; |
|||
|
|||
case REG_PS2_RCVDATA: |
|||
return " PS2_RCVDATA"; |
|||
|
|||
case REG_PS2_CONTROL: |
|||
return " PS2_CONTROL"; |
|||
|
|||
case REG_PS2_STATUS: |
|||
return " PS2_STATUS"; |
|||
|
|||
default: |
|||
return ""; |
|||
} |
|||
} |
|||
|
|||
static const char *artist_write_reg_name(uint64_t addr) |
|||
{ |
|||
switch (addr & 0x0c) { |
|||
case REG_PS2_RESET: |
|||
return " PS2_RESET"; |
|||
|
|||
case REG_PS2_XMTDATA: |
|||
return " PS2_XMTDATA"; |
|||
|
|||
case REG_PS2_CONTROL: |
|||
return " PS2_CONTROL"; |
|||
|
|||
default: |
|||
return ""; |
|||
} |
|||
} |
|||
|
|||
static void lasips2_update_irq(LASIPS2State *s) |
|||
{ |
|||
trace_lasips2_intr(s->kbd.irq | s->mouse.irq); |
|||
qemu_set_irq(s->irq, s->kbd.irq | s->mouse.irq); |
|||
} |
|||
|
|||
static void lasips2_reg_write(void *opaque, hwaddr addr, uint64_t val, |
|||
unsigned size) |
|||
{ |
|||
LASIPS2Port *port = opaque; |
|||
|
|||
trace_lasips2_reg_write(size, port->id, addr, |
|||
artist_write_reg_name(addr), val); |
|||
|
|||
switch (addr & 0xc) { |
|||
case REG_PS2_CONTROL: |
|||
port->control = val; |
|||
break; |
|||
|
|||
case REG_PS2_XMTDATA: |
|||
if (port->control & LASIPS2_CONTROL_LOOPBACK) { |
|||
port->buf = val; |
|||
port->irq = true; |
|||
port->loopback_rbne = true; |
|||
lasips2_update_irq(port->parent); |
|||
break; |
|||
} |
|||
|
|||
if (port->id) { |
|||
ps2_write_mouse(port->dev, val); |
|||
} else { |
|||
ps2_write_keyboard(port->dev, val); |
|||
} |
|||
break; |
|||
|
|||
case REG_PS2_RESET: |
|||
break; |
|||
|
|||
default: |
|||
qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", |
|||
__func__, addr); |
|||
break; |
|||
} |
|||
} |
|||
|
|||
static uint64_t lasips2_reg_read(void *opaque, hwaddr addr, unsigned size) |
|||
{ |
|||
LASIPS2Port *port = opaque; |
|||
uint64_t ret = 0; |
|||
|
|||
switch (addr & 0xc) { |
|||
case REG_PS2_ID: |
|||
ret = port->id; |
|||
break; |
|||
|
|||
case REG_PS2_RCVDATA: |
|||
if (port->control & LASIPS2_CONTROL_LOOPBACK) { |
|||
port->irq = false; |
|||
port->loopback_rbne = false; |
|||
lasips2_update_irq(port->parent); |
|||
ret = port->buf; |
|||
break; |
|||
} |
|||
|
|||
ret = ps2_read_data(port->dev); |
|||
break; |
|||
|
|||
case REG_PS2_CONTROL: |
|||
ret = port->control; |
|||
break; |
|||
|
|||
case REG_PS2_STATUS: |
|||
|
|||
ret = LASIPS2_STATUS_DATSHD | LASIPS2_STATUS_CLKSHD; |
|||
|
|||
if (port->control & LASIPS2_CONTROL_DIAG) { |
|||
if (!(port->control & LASIPS2_CONTROL_DATDIR)) { |
|||
ret &= ~LASIPS2_STATUS_DATSHD; |
|||
} |
|||
|
|||
if (!(port->control & LASIPS2_CONTROL_CLKDIR)) { |
|||
ret &= ~LASIPS2_STATUS_CLKSHD; |
|||
} |
|||
} |
|||
|
|||
if (port->control & LASIPS2_CONTROL_LOOPBACK) { |
|||
if (port->loopback_rbne) { |
|||
ret |= LASIPS2_STATUS_RBNE; |
|||
} |
|||
} else { |
|||
if (!ps2_queue_empty(port->dev)) { |
|||
ret |= LASIPS2_STATUS_RBNE; |
|||
} |
|||
} |
|||
|
|||
if (port->parent->kbd.irq || port->parent->mouse.irq) { |
|||
ret |= LASIPS2_STATUS_CMPINTR; |
|||
} |
|||
break; |
|||
|
|||
default: |
|||
qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", |
|||
__func__, addr); |
|||
break; |
|||
} |
|||
trace_lasips2_reg_read(size, port->id, addr, |
|||
artist_read_reg_name(addr), ret); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
static const MemoryRegionOps lasips2_reg_ops = { |
|||
.read = lasips2_reg_read, |
|||
.write = lasips2_reg_write, |
|||
.impl = { |
|||
.min_access_size = 1, |
|||
.max_access_size = 4, |
|||
}, |
|||
.endianness = DEVICE_NATIVE_ENDIAN, |
|||
}; |
|||
|
|||
static void ps2dev_update_irq(void *opaque, int level) |
|||
{ |
|||
LASIPS2Port *port = opaque; |
|||
port->irq = level; |
|||
lasips2_update_irq(port->parent); |
|||
} |
|||
|
|||
void lasips2_init(MemoryRegion *address_space, |
|||
hwaddr base, qemu_irq irq) |
|||
{ |
|||
LASIPS2State *s; |
|||
|
|||
s = g_malloc0(sizeof(LASIPS2State)); |
|||
|
|||
s->irq = irq; |
|||
s->mouse.id = 1; |
|||
s->kbd.parent = s; |
|||
s->mouse.parent = s; |
|||
|
|||
vmstate_register(NULL, base, &vmstate_lasips2, s); |
|||
|
|||
s->kbd.dev = ps2_kbd_init(ps2dev_update_irq, &s->kbd); |
|||
s->mouse.dev = ps2_mouse_init(ps2dev_update_irq, &s->mouse); |
|||
|
|||
memory_region_init_io(&s->kbd.reg, NULL, &lasips2_reg_ops, &s->kbd, |
|||
"lasips2-kbd", 0x100); |
|||
memory_region_add_subregion(address_space, base, &s->kbd.reg); |
|||
|
|||
memory_region_init_io(&s->mouse.reg, NULL, &lasips2_reg_ops, &s->mouse, |
|||
"lasips2-mouse", 0x100); |
|||
memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg); |
|||
} |
|||
@ -0,0 +1,734 @@ |
|||
/*
|
|||
* QEMU Intel i82596 (Apricot) emulation |
|||
* |
|||
* Copyright (c) 2019 Helge Deller <deller@gmx.de> |
|||
* This work is licensed under the GNU GPL license version 2 or later. |
|||
* |
|||
* This software was written to be compatible with the specification: |
|||
* https://www.intel.com/assets/pdf/general/82596ca.pdf
|
|||
*/ |
|||
|
|||
#include "qemu/osdep.h" |
|||
#include "qemu/timer.h" |
|||
#include "net/net.h" |
|||
#include "net/eth.h" |
|||
#include "sysemu/sysemu.h" |
|||
#include "hw/irq.h" |
|||
#include "hw/qdev-properties.h" |
|||
#include "migration/vmstate.h" |
|||
#include "qemu/module.h" |
|||
#include "trace.h" |
|||
#include "i82596.h" |
|||
#include <zlib.h> /* For crc32 */ |
|||
|
|||
#if defined(ENABLE_DEBUG) |
|||
#define DBG(x) x |
|||
#else |
|||
#define DBG(x) do { } while (0) |
|||
#endif |
|||
|
|||
#define USE_TIMER 0 |
|||
|
|||
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
|||
|
|||
#define PKT_BUF_SZ 1536 |
|||
#define MAX_MC_CNT 64 |
|||
|
|||
#define ISCP_BUSY 0x0001 |
|||
|
|||
#define I596_NULL ((uint32_t)0xffffffff) |
|||
|
|||
#define SCB_STATUS_CX 0x8000 /* CU finished command with I bit */ |
|||
#define SCB_STATUS_FR 0x4000 /* RU finished receiving a frame */ |
|||
#define SCB_STATUS_CNA 0x2000 /* CU left active state */ |
|||
#define SCB_STATUS_RNR 0x1000 /* RU left active state */ |
|||
|
|||
#define CU_IDLE 0 |
|||
#define CU_SUSPENDED 1 |
|||
#define CU_ACTIVE 2 |
|||
|
|||
#define RX_IDLE 0 |
|||
#define RX_SUSPENDED 1 |
|||
#define RX_READY 4 |
|||
|
|||
#define CMD_EOL 0x8000 /* The last command of the list, stop. */ |
|||
#define CMD_SUSP 0x4000 /* Suspend after doing cmd. */ |
|||
#define CMD_INTR 0x2000 /* Interrupt after doing cmd. */ |
|||
|
|||
#define CMD_FLEX 0x0008 /* Enable flexible memory model */ |
|||
|
|||
enum commands { |
|||
CmdNOp = 0, CmdSASetup = 1, CmdConfigure = 2, CmdMulticastList = 3, |
|||
CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7 |
|||
}; |
|||
|
|||
#define STAT_C 0x8000 /* Set to 0 after execution */ |
|||
#define STAT_B 0x4000 /* Command being executed */ |
|||
#define STAT_OK 0x2000 /* Command executed ok */ |
|||
#define STAT_A 0x1000 /* Command aborted */ |
|||
|
|||
#define I596_EOF 0x8000 |
|||
#define SIZE_MASK 0x3fff |
|||
|
|||
#define ETHER_TYPE_LEN 2 |
|||
#define VLAN_TCI_LEN 2 |
|||
#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) |
|||
|
|||
/* various flags in the chip config registers */ |
|||
#define I596_PREFETCH (s->config[0] & 0x80) |
|||
#define I596_PROMISC (s->config[8] & 0x01) |
|||
#define I596_BC_DISABLE (s->config[8] & 0x02) /* broadcast disable */ |
|||
#define I596_NOCRC_INS (s->config[8] & 0x08) |
|||
#define I596_CRCINM (s->config[11] & 0x04) /* CRC appended */ |
|||
#define I596_MC_ALL (s->config[11] & 0x20) |
|||
#define I596_MULTIIA (s->config[13] & 0x40) |
|||
|
|||
|
|||
static uint8_t get_byte(uint32_t addr) |
|||
{ |
|||
return ldub_phys(&address_space_memory, addr); |
|||
} |
|||
|
|||
static void set_byte(uint32_t addr, uint8_t c) |
|||
{ |
|||
return stb_phys(&address_space_memory, addr, c); |
|||
} |
|||
|
|||
static uint16_t get_uint16(uint32_t addr) |
|||
{ |
|||
return lduw_be_phys(&address_space_memory, addr); |
|||
} |
|||
|
|||
static void set_uint16(uint32_t addr, uint16_t w) |
|||
{ |
|||
return stw_be_phys(&address_space_memory, addr, w); |
|||
} |
|||
|
|||
static uint32_t get_uint32(uint32_t addr) |
|||
{ |
|||
uint32_t lo = lduw_be_phys(&address_space_memory, addr); |
|||
uint32_t hi = lduw_be_phys(&address_space_memory, addr + 2); |
|||
return (hi << 16) | lo; |
|||
} |
|||
|
|||
static void set_uint32(uint32_t addr, uint32_t val) |
|||
{ |
|||
set_uint16(addr, (uint16_t) val); |
|||
set_uint16(addr + 2, val >> 16); |
|||
} |
|||
|
|||
|
|||
struct qemu_ether_header { |
|||
uint8_t ether_dhost[6]; |
|||
uint8_t ether_shost[6]; |
|||
uint16_t ether_type; |
|||
}; |
|||
|
|||
#define PRINT_PKTHDR(txt, BUF) do { \ |
|||
struct qemu_ether_header *hdr = (void *)(BUF); \ |
|||
printf(txt ": packet dhost=" MAC_FMT ", shost=" MAC_FMT ", type=0x%04x\n",\ |
|||
MAC_ARG(hdr->ether_dhost), MAC_ARG(hdr->ether_shost), \ |
|||
be16_to_cpu(hdr->ether_type)); \ |
|||
} while (0) |
|||
|
|||
static void i82596_transmit(I82596State *s, uint32_t addr) |
|||
{ |
|||
uint32_t tdb_p; /* Transmit Buffer Descriptor */ |
|||
|
|||
/* TODO: Check flexible mode */ |
|||
tdb_p = get_uint32(addr + 8); |
|||
while (tdb_p != I596_NULL) { |
|||
uint16_t size, len; |
|||
uint32_t tba; |
|||
|
|||
size = get_uint16(tdb_p); |
|||
len = size & SIZE_MASK; |
|||
tba = get_uint32(tdb_p + 8); |
|||
trace_i82596_transmit(len, tba); |
|||
|
|||
if (s->nic && len) { |
|||
assert(len <= sizeof(s->tx_buffer)); |
|||
address_space_rw(&address_space_memory, tba, |
|||
MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, 0); |
|||
DBG(PRINT_PKTHDR("Send", &s->tx_buffer)); |
|||
DBG(printf("Sending %d bytes\n", len)); |
|||
qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len); |
|||
} |
|||
|
|||
/* was this the last package? */ |
|||
if (size & I596_EOF) { |
|||
break; |
|||
} |
|||
|
|||
/* get next buffer pointer */ |
|||
tdb_p = get_uint32(tdb_p + 4); |
|||
} |
|||
} |
|||
|
|||
static void set_individual_address(I82596State *s, uint32_t addr) |
|||
{ |
|||
NetClientState *nc; |
|||
uint8_t *m; |
|||
|
|||
nc = qemu_get_queue(s->nic); |
|||
m = s->conf.macaddr.a; |
|||
address_space_rw(&address_space_memory, addr + 8, |
|||
MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, 0); |
|||
qemu_format_nic_info_str(nc, m); |
|||
trace_i82596_new_mac(nc->info_str); |
|||
} |
|||
|
|||
static void set_multicast_list(I82596State *s, uint32_t addr) |
|||
{ |
|||
uint16_t mc_count, i; |
|||
|
|||
memset(&s->mult[0], 0, sizeof(s->mult)); |
|||
mc_count = get_uint16(addr + 8) / ETH_ALEN; |
|||
addr += 10; |
|||
if (mc_count > MAX_MC_CNT) { |
|||
mc_count = MAX_MC_CNT; |
|||
} |
|||
for (i = 0; i < mc_count; i++) { |
|||
uint8_t multicast_addr[ETH_ALEN]; |
|||
address_space_rw(&address_space_memory, |
|||
addr + i * ETH_ALEN, MEMTXATTRS_UNSPECIFIED, |
|||
multicast_addr, ETH_ALEN, 0); |
|||
DBG(printf("Add multicast entry " MAC_FMT "\n", |
|||
MAC_ARG(multicast_addr))); |
|||
unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & |
|||
BITS(7, 2)) >> 2; |
|||
assert(mcast_idx < 8 * sizeof(s->mult)); |
|||
s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); |
|||
} |
|||
trace_i82596_set_multicast(mc_count); |
|||
} |
|||
|
|||
void i82596_set_link_status(NetClientState *nc) |
|||
{ |
|||
I82596State *d = qemu_get_nic_opaque(nc); |
|||
|
|||
d->lnkst = nc->link_down ? 0 : 0x8000; |
|||
} |
|||
|
|||
static void update_scb_status(I82596State *s) |
|||
{ |
|||
s->scb_status = (s->scb_status & 0xf000) |
|||
| (s->cu_status << 8) | (s->rx_status << 4); |
|||
set_uint16(s->scb, s->scb_status); |
|||
} |
|||
|
|||
|
|||
static void i82596_s_reset(I82596State *s) |
|||
{ |
|||
trace_i82596_s_reset(s); |
|||
s->scp = 0; |
|||
s->scb_status = 0; |
|||
s->cu_status = CU_IDLE; |
|||
s->rx_status = RX_SUSPENDED; |
|||
s->cmd_p = I596_NULL; |
|||
s->lnkst = 0x8000; /* initial link state: up */ |
|||
s->ca = s->ca_active = 0; |
|||
s->send_irq = 0; |
|||
} |
|||
|
|||
|
|||
static void command_loop(I82596State *s) |
|||
{ |
|||
uint16_t cmd; |
|||
uint16_t status; |
|||
uint8_t byte_cnt; |
|||
|
|||
DBG(printf("STARTING COMMAND LOOP cmd_p=%08x\n", s->cmd_p)); |
|||
|
|||
while (s->cmd_p != I596_NULL) { |
|||
/* set status */ |
|||
status = STAT_B; |
|||
set_uint16(s->cmd_p, status); |
|||
status = STAT_C | STAT_OK; /* update, but write later */ |
|||
|
|||
cmd = get_uint16(s->cmd_p + 2); |
|||
DBG(printf("Running command %04x at %08x\n", cmd, s->cmd_p)); |
|||
|
|||
switch (cmd & 0x07) { |
|||
case CmdNOp: |
|||
break; |
|||
case CmdSASetup: |
|||
set_individual_address(s, s->cmd_p); |
|||
break; |
|||
case CmdConfigure: |
|||
byte_cnt = get_byte(s->cmd_p + 8) & 0x0f; |
|||
byte_cnt = MAX(byte_cnt, 4); |
|||
byte_cnt = MIN(byte_cnt, sizeof(s->config)); |
|||
/* copy byte_cnt max. */ |
|||
address_space_rw(&address_space_memory, s->cmd_p + 8, |
|||
MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt, 0); |
|||
/* config byte according to page 35ff */ |
|||
s->config[2] &= 0x82; /* mask valid bits */ |
|||
s->config[2] |= 0x40; |
|||
s->config[7] &= 0xf7; /* clear zero bit */ |
|||
assert(I596_NOCRC_INS == 0); /* do CRC insertion */ |
|||
s->config[10] = MAX(s->config[10], 5); /* min frame length */ |
|||
s->config[12] &= 0x40; /* only full duplex field valid */ |
|||
s->config[13] |= 0x3f; /* set ones in byte 13 */ |
|||
break; |
|||
case CmdTDR: |
|||
/* get signal LINK */ |
|||
set_uint32(s->cmd_p + 8, s->lnkst); |
|||
break; |
|||
case CmdTx: |
|||
i82596_transmit(s, s->cmd_p); |
|||
break; |
|||
case CmdMulticastList: |
|||
set_multicast_list(s, s->cmd_p); |
|||
break; |
|||
case CmdDump: |
|||
case CmdDiagnose: |
|||
printf("FIXME Command %d !!\n", cmd & 7); |
|||
assert(0); |
|||
} |
|||
|
|||
/* update status */ |
|||
set_uint16(s->cmd_p, status); |
|||
|
|||
s->cmd_p = get_uint32(s->cmd_p + 4); /* get link address */ |
|||
DBG(printf("NEXT addr would be %08x\n", s->cmd_p)); |
|||
if (s->cmd_p == 0) { |
|||
s->cmd_p = I596_NULL; |
|||
} |
|||
|
|||
/* Stop when last command of the list. */ |
|||
if (cmd & CMD_EOL) { |
|||
s->cmd_p = I596_NULL; |
|||
} |
|||
/* Suspend after doing cmd? */ |
|||
if (cmd & CMD_SUSP) { |
|||
s->cu_status = CU_SUSPENDED; |
|||
printf("FIXME SUSPEND !!\n"); |
|||
} |
|||
/* Interrupt after doing cmd? */ |
|||
if (cmd & CMD_INTR) { |
|||
s->scb_status |= SCB_STATUS_CX; |
|||
} else { |
|||
s->scb_status &= ~SCB_STATUS_CX; |
|||
} |
|||
update_scb_status(s); |
|||
|
|||
/* Interrupt after doing cmd? */ |
|||
if (cmd & CMD_INTR) { |
|||
s->send_irq = 1; |
|||
} |
|||
|
|||
if (s->cu_status != CU_ACTIVE) { |
|||
break; |
|||
} |
|||
} |
|||
DBG(printf("FINISHED COMMAND LOOP\n")); |
|||
qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
|||
} |
|||
|
|||
static void i82596_flush_queue_timer(void *opaque) |
|||
{ |
|||
I82596State *s = opaque; |
|||
if (0) { |
|||
timer_del(s->flush_queue_timer); |
|||
qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
|||
timer_mod(s->flush_queue_timer, |
|||
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); |
|||
} |
|||
} |
|||
|
|||
static void examine_scb(I82596State *s) |
|||
{ |
|||
uint16_t command, cuc, ruc; |
|||
|
|||
/* get the scb command word */ |
|||
command = get_uint16(s->scb + 2); |
|||
cuc = (command >> 8) & 0x7; |
|||
ruc = (command >> 4) & 0x7; |
|||
DBG(printf("MAIN COMMAND %04x cuc %02x ruc %02x\n", command, cuc, ruc)); |
|||
/* and clear the scb command word */ |
|||
set_uint16(s->scb + 2, 0); |
|||
|
|||
if (command & BIT(31)) /* ACK-CX */ |
|||
s->scb_status &= ~SCB_STATUS_CX; |
|||
if (command & BIT(30)) /*ACK-FR */ |
|||
s->scb_status &= ~SCB_STATUS_FR; |
|||
if (command & BIT(29)) /*ACK-CNA */ |
|||
s->scb_status &= ~SCB_STATUS_CNA; |
|||
if (command & BIT(28)) /*ACK-RNR */ |
|||
s->scb_status &= ~SCB_STATUS_RNR; |
|||
|
|||
switch (cuc) { |
|||
case 0: /* no change */ |
|||
break; |
|||
case 1: /* CUC_START */ |
|||
s->cu_status = CU_ACTIVE; |
|||
break; |
|||
case 4: /* CUC_ABORT */ |
|||
s->cu_status = CU_SUSPENDED; |
|||
s->scb_status |= SCB_STATUS_CNA; /* CU left active state */ |
|||
break; |
|||
default: |
|||
printf("WARNING: Unknown CUC %d!\n", cuc); |
|||
} |
|||
|
|||
switch (ruc) { |
|||
case 0: /* no change */ |
|||
break; |
|||
case 1: /* RX_START */ |
|||
case 2: /* RX_RESUME */ |
|||
s->rx_status = RX_IDLE; |
|||
if (USE_TIMER) { |
|||
timer_mod(s->flush_queue_timer, qemu_clock_get_ms( |
|||
QEMU_CLOCK_VIRTUAL) + 1000); |
|||
} |
|||
break; |
|||
case 3: /* RX_SUSPEND */ |
|||
case 4: /* RX_ABORT */ |
|||
s->rx_status = RX_SUSPENDED; |
|||
s->scb_status |= SCB_STATUS_RNR; /* RU left active state */ |
|||
break; |
|||
default: |
|||
printf("WARNING: Unknown RUC %d!\n", ruc); |
|||
} |
|||
|
|||
if (command & 0x80) { /* reset bit set? */ |
|||
i82596_s_reset(s); |
|||
} |
|||
|
|||
/* execute commands from SCBL */ |
|||
if (s->cu_status != CU_SUSPENDED) { |
|||
if (s->cmd_p == I596_NULL) { |
|||
s->cmd_p = get_uint32(s->scb + 4); |
|||
} |
|||
} |
|||
|
|||
/* update scb status */ |
|||
update_scb_status(s); |
|||
|
|||
command_loop(s); |
|||
} |
|||
|
|||
static void signal_ca(I82596State *s) |
|||
{ |
|||
uint32_t iscp = 0; |
|||
|
|||
/* trace_i82596_channel_attention(s); */ |
|||
if (s->scp) { |
|||
/* CA after reset -> do init with new scp. */ |
|||
s->sysbus = get_byte(s->scp + 3); /* big endian */ |
|||
DBG(printf("SYSBUS = %08x\n", s->sysbus)); |
|||
if (((s->sysbus >> 1) & 0x03) != 2) { |
|||
printf("WARNING: NO LINEAR MODE !!\n"); |
|||
} |
|||
if ((s->sysbus >> 7)) { |
|||
printf("WARNING: 32BIT LINMODE IN B-STEPPING NOT SUPPORTED !!\n"); |
|||
} |
|||
iscp = get_uint32(s->scp + 8); |
|||
s->scb = get_uint32(iscp + 4); |
|||
set_byte(iscp + 1, 0); /* clear BUSY flag in iscp */ |
|||
s->scp = 0; |
|||
} |
|||
|
|||
s->ca++; /* count ca() */ |
|||
if (!s->ca_active) { |
|||
s->ca_active = 1; |
|||
while (s->ca) { |
|||
examine_scb(s); |
|||
s->ca--; |
|||
} |
|||
s->ca_active = 0; |
|||
} |
|||
|
|||
if (s->send_irq) { |
|||
s->send_irq = 0; |
|||
qemu_set_irq(s->irq, 1); |
|||
} |
|||
} |
|||
|
|||
void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
|||
{ |
|||
I82596State *s = opaque; |
|||
/* printf("i82596_ioport_writew addr=0x%08x val=0x%04x\n", addr, val); */ |
|||
switch (addr) { |
|||
case PORT_RESET: /* Reset */ |
|||
i82596_s_reset(s); |
|||
break; |
|||
case PORT_ALTSCP: |
|||
s->scp = val; |
|||
break; |
|||
case PORT_CA: |
|||
signal_ca(s); |
|||
break; |
|||
} |
|||
} |
|||
|
|||
uint32_t i82596_ioport_readw(void *opaque, uint32_t addr) |
|||
{ |
|||
return -1; |
|||
} |
|||
|
|||
void i82596_h_reset(void *opaque) |
|||
{ |
|||
I82596State *s = opaque; |
|||
|
|||
i82596_s_reset(s); |
|||
} |
|||
|
|||
int i82596_can_receive(NetClientState *nc) |
|||
{ |
|||
I82596State *s = qemu_get_nic_opaque(nc); |
|||
|
|||
if (s->rx_status == RX_SUSPENDED) { |
|||
return 0; |
|||
} |
|||
|
|||
if (!s->lnkst) { |
|||
return 0; |
|||
} |
|||
|
|||
if (USE_TIMER && !timer_pending(s->flush_queue_timer)) { |
|||
return 1; |
|||
} |
|||
|
|||
return 1; |
|||
} |
|||
|
|||
#define MIN_BUF_SIZE 60 |
|||
|
|||
ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz) |
|||
{ |
|||
I82596State *s = qemu_get_nic_opaque(nc); |
|||
uint32_t rfd_p; |
|||
uint32_t rbd; |
|||
uint16_t is_broadcast = 0; |
|||
size_t len = sz; |
|||
uint32_t crc; |
|||
uint8_t *crc_ptr; |
|||
uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; |
|||
static const uint8_t broadcast_macaddr[6] = { |
|||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
|||
|
|||
DBG(printf("i82596_receive() start\n")); |
|||
|
|||
if (USE_TIMER && timer_pending(s->flush_queue_timer)) { |
|||
return 0; |
|||
} |
|||
|
|||
/* first check if receiver is enabled */ |
|||
if (s->rx_status == RX_SUSPENDED) { |
|||
trace_i82596_receive_analysis(">>> Receiving suspended"); |
|||
return -1; |
|||
} |
|||
|
|||
if (!s->lnkst) { |
|||
trace_i82596_receive_analysis(">>> Link down"); |
|||
return -1; |
|||
} |
|||
|
|||
/* Received frame smaller than configured "min frame len"? */ |
|||
if (sz < s->config[10]) { |
|||
printf("Received frame too small, %zu vs. %u bytes\n", |
|||
sz, s->config[10]); |
|||
return -1; |
|||
} |
|||
|
|||
DBG(printf("Received %lu bytes\n", sz)); |
|||
|
|||
if (I596_PROMISC) { |
|||
|
|||
/* promiscuous: receive all */ |
|||
trace_i82596_receive_analysis( |
|||
">>> packet received in promiscuous mode"); |
|||
|
|||
} else { |
|||
|
|||
if (!memcmp(buf, broadcast_macaddr, 6)) { |
|||
/* broadcast address */ |
|||
if (I596_BC_DISABLE) { |
|||
trace_i82596_receive_analysis(">>> broadcast packet rejected"); |
|||
|
|||
return len; |
|||
} |
|||
|
|||
trace_i82596_receive_analysis(">>> broadcast packet received"); |
|||
is_broadcast = 1; |
|||
|
|||
} else if (buf[0] & 0x01) { |
|||
/* multicast */ |
|||
if (!I596_MC_ALL) { |
|||
trace_i82596_receive_analysis(">>> multicast packet rejected"); |
|||
|
|||
return len; |
|||
} |
|||
|
|||
int mcast_idx = (net_crc32(buf, ETH_ALEN) & BITS(7, 2)) >> 2; |
|||
assert(mcast_idx < 8 * sizeof(s->mult)); |
|||
|
|||
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { |
|||
trace_i82596_receive_analysis(">>> multicast address mismatch"); |
|||
|
|||
return len; |
|||
} |
|||
|
|||
trace_i82596_receive_analysis(">>> multicast packet received"); |
|||
is_broadcast = 1; |
|||
|
|||
} else if (!memcmp(s->conf.macaddr.a, buf, 6)) { |
|||
|
|||
/* match */ |
|||
trace_i82596_receive_analysis( |
|||
">>> physical address matching packet received"); |
|||
|
|||
} else { |
|||
|
|||
trace_i82596_receive_analysis(">>> unknown packet"); |
|||
|
|||
return len; |
|||
} |
|||
} |
|||
|
|||
/* if too small buffer, then expand it */ |
|||
if (len < MIN_BUF_SIZE + VLAN_HLEN) { |
|||
memcpy(buf1, buf, len); |
|||
memset(buf1 + len, 0, MIN_BUF_SIZE + VLAN_HLEN - len); |
|||
buf = buf1; |
|||
if (len < MIN_BUF_SIZE) { |
|||
len = MIN_BUF_SIZE; |
|||
} |
|||
} |
|||
|
|||
/* Calculate the ethernet checksum (4 bytes) */ |
|||
len += 4; |
|||
crc = cpu_to_be32(crc32(~0, buf, sz)); |
|||
crc_ptr = (uint8_t *) &crc; |
|||
|
|||
rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */ |
|||
assert(rfd_p && rfd_p != I596_NULL); |
|||
|
|||
/* get first Receive Buffer Descriptor Address */ |
|||
rbd = get_uint32(rfd_p + 8); |
|||
assert(rbd && rbd != I596_NULL); |
|||
|
|||
trace_i82596_receive_packet(len); |
|||
/* PRINT_PKTHDR("Receive", buf); */ |
|||
|
|||
while (len) { |
|||
uint16_t command, status; |
|||
uint32_t next_rfd; |
|||
|
|||
command = get_uint16(rfd_p + 2); |
|||
assert(command & CMD_FLEX); /* assert Flex Mode */ |
|||
/* get first Receive Buffer Descriptor Address */ |
|||
rbd = get_uint32(rfd_p + 8); |
|||
assert(get_uint16(rfd_p + 14) == 0); |
|||
|
|||
/* printf("Receive: rfd is %08x\n", rfd_p); */ |
|||
|
|||
while (len) { |
|||
uint16_t buffer_size, num; |
|||
uint32_t rba; |
|||
|
|||
/* printf("Receive: rbd is %08x\n", rbd); */ |
|||
buffer_size = get_uint16(rbd + 12); |
|||
/* printf("buffer_size is 0x%x\n", buffer_size); */ |
|||
assert(buffer_size != 0); |
|||
|
|||
num = buffer_size & SIZE_MASK; |
|||
if (num > len) { |
|||
num = len; |
|||
} |
|||
rba = get_uint32(rbd + 8); |
|||
/* printf("rba is 0x%x\n", rba); */ |
|||
address_space_rw(&address_space_memory, rba, |
|||
MEMTXATTRS_UNSPECIFIED, (void *)buf, num, 1); |
|||
rba += num; |
|||
buf += num; |
|||
len -= num; |
|||
if (len == 0) { /* copy crc */ |
|||
address_space_rw(&address_space_memory, rba - 4, |
|||
MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, 1); |
|||
} |
|||
|
|||
num |= 0x4000; /* set F BIT */ |
|||
if (len == 0) { |
|||
num |= I596_EOF; /* set EOF BIT */ |
|||
} |
|||
set_uint16(rbd + 0, num); /* write actual count with flags */ |
|||
|
|||
/* get next rbd */ |
|||
rbd = get_uint32(rbd + 4); |
|||
/* printf("Next Receive: rbd is %08x\n", rbd); */ |
|||
|
|||
if (buffer_size & I596_EOF) /* last entry */ |
|||
break; |
|||
} |
|||
|
|||
/* Housekeeping, see pg. 18 */ |
|||
next_rfd = get_uint32(rfd_p + 4); |
|||
set_uint32(next_rfd + 8, rbd); |
|||
|
|||
status = STAT_C | STAT_OK | is_broadcast; |
|||
set_uint16(rfd_p, status); |
|||
|
|||
if (command & CMD_SUSP) { /* suspend after command? */ |
|||
s->rx_status = RX_SUSPENDED; |
|||
s->scb_status |= SCB_STATUS_RNR; /* RU left active state */ |
|||
break; |
|||
} |
|||
if (command & CMD_EOL) /* was it last Frame Descriptor? */ |
|||
break; |
|||
|
|||
assert(len == 0); |
|||
} |
|||
|
|||
assert(len == 0); |
|||
|
|||
s->scb_status |= SCB_STATUS_FR; /* set "RU finished receiving frame" bit. */ |
|||
update_scb_status(s); |
|||
|
|||
/* send IRQ that we received data */ |
|||
qemu_set_irq(s->irq, 1); |
|||
/* s->send_irq = 1; */ |
|||
|
|||
if (0) { |
|||
DBG(printf("Checking:\n")); |
|||
rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */ |
|||
DBG(printf("Next Receive: rfd is %08x\n", rfd_p)); |
|||
rfd_p = get_uint32(rfd_p + 4); /* get Next Receive Frame Descriptor */ |
|||
DBG(printf("Next Receive: rfd is %08x\n", rfd_p)); |
|||
/* get first Receive Buffer Descriptor Address */ |
|||
rbd = get_uint32(rfd_p + 8); |
|||
DBG(printf("Next Receive: rbd is %08x\n", rbd)); |
|||
} |
|||
|
|||
return sz; |
|||
} |
|||
|
|||
|
|||
const VMStateDescription vmstate_i82596 = { |
|||
.name = "i82596", |
|||
.version_id = 1, |
|||
.minimum_version_id = 1, |
|||
.fields = (VMStateField[]) { |
|||
VMSTATE_UINT16(lnkst, I82596State), |
|||
VMSTATE_TIMER_PTR(flush_queue_timer, I82596State), |
|||
VMSTATE_END_OF_LIST() |
|||
} |
|||
}; |
|||
|
|||
void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info) |
|||
{ |
|||
if (s->conf.macaddr.a[0] == 0) { |
|||
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
|||
} |
|||
s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)), |
|||
dev->id, s); |
|||
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
|||
|
|||
if (USE_TIMER) { |
|||
s->flush_queue_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
|||
i82596_flush_queue_timer, s); |
|||
} |
|||
s->lnkst = 0x8000; /* initial link state: up */ |
|||
} |
|||
@ -0,0 +1,55 @@ |
|||
#ifndef HW_I82596_H |
|||
#define HW_I82596_H |
|||
|
|||
#define I82596_IOPORT_SIZE 0x20 |
|||
|
|||
#include "exec/memory.h" |
|||
#include "exec/address-spaces.h" |
|||
|
|||
#define PORT_RESET 0x00 /* reset 82596 */ |
|||
#define PORT_SELFTEST 0x01 /* selftest */ |
|||
#define PORT_ALTSCP 0x02 /* alternate SCB address */ |
|||
#define PORT_ALTDUMP 0x03 /* Alternate DUMP address */ |
|||
#define PORT_CA 0x10 /* QEMU-internal CA signal */ |
|||
|
|||
typedef struct I82596State_st I82596State; |
|||
|
|||
struct I82596State_st { |
|||
MemoryRegion mmio; |
|||
MemoryRegion *as; |
|||
qemu_irq irq; |
|||
NICState *nic; |
|||
NICConf conf; |
|||
QEMUTimer *flush_queue_timer; |
|||
|
|||
hwaddr scp; /* pointer to SCP */ |
|||
uint8_t sysbus; |
|||
uint32_t scb; /* SCB */ |
|||
uint16_t scb_status; |
|||
uint8_t cu_status, rx_status; |
|||
uint16_t lnkst; |
|||
|
|||
uint32_t cmd_p; /* addr of current command */ |
|||
int ca; |
|||
int ca_active; |
|||
int send_irq; |
|||
|
|||
/* Hash register (multicast mask array, multiple individual addresses). */ |
|||
uint8_t mult[8]; |
|||
uint8_t config[14]; /* config bytes from CONFIGURE command */ |
|||
|
|||
uint8_t tx_buffer[0x4000]; |
|||
}; |
|||
|
|||
void i82596_h_reset(void *opaque); |
|||
void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val); |
|||
uint32_t i82596_ioport_readw(void *opaque, uint32_t addr); |
|||
void i82596_ioport_writel(void *opaque, uint32_t addr, uint32_t val); |
|||
uint32_t i82596_ioport_readl(void *opaque, uint32_t addr); |
|||
uint32_t i82596_bcr_readw(I82596State *s, uint32_t rap); |
|||
ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t size_); |
|||
int i82596_can_receive(NetClientState *nc); |
|||
void i82596_set_link_status(NetClientState *nc); |
|||
void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info); |
|||
extern const VMStateDescription vmstate_i82596; |
|||
#endif |
|||
@ -0,0 +1,188 @@ |
|||
/*
|
|||
* QEMU LASI NIC i82596 emulation |
|||
* |
|||
* Copyright (c) 2019 Helge Deller <deller@gmx.de> |
|||
* This work is licensed under the GNU GPL license version 2 or later. |
|||
* |
|||
* |
|||
* On PA-RISC, this is the Network part of LASI chip. |
|||
* See: |
|||
* https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
|
|||
*/ |
|||
|
|||
#include "qemu/osdep.h" |
|||
#include "qemu/timer.h" |
|||
#include "hw/sysbus.h" |
|||
#include "net/eth.h" |
|||
#include "hw/net/lasi_82596.h" |
|||
#include "hw/net/i82596.h" |
|||
#include "trace.h" |
|||
#include "sysemu/sysemu.h" |
|||
#include "hw/qdev-properties.h" |
|||
#include "migration/vmstate.h" |
|||
|
|||
#define PA_I82596_RESET 0 /* Offsets relative to LASI-LAN-Addr.*/ |
|||
#define PA_CPU_PORT_L_ACCESS 4 |
|||
#define PA_CHANNEL_ATTENTION 8 |
|||
#define PA_GET_MACADDR 12 |
|||
|
|||
#define SWAP32(x) (((uint32_t)(x) << 16) | ((((uint32_t)(x))) >> 16)) |
|||
|
|||
static void lasi_82596_mem_write(void *opaque, hwaddr addr, |
|||
uint64_t val, unsigned size) |
|||
{ |
|||
SysBusI82596State *d = opaque; |
|||
|
|||
trace_lasi_82596_mem_writew(addr, val); |
|||
switch (addr) { |
|||
case PA_I82596_RESET: |
|||
i82596_h_reset(&d->state); |
|||
break; |
|||
case PA_CPU_PORT_L_ACCESS: |
|||
d->val_index++; |
|||
if (d->val_index == 0) { |
|||
uint32_t v = d->last_val | (val << 16); |
|||
v = v & ~0xff; |
|||
i82596_ioport_writew(&d->state, d->last_val & 0xff, v); |
|||
} |
|||
d->last_val = val; |
|||
break; |
|||
case PA_CHANNEL_ATTENTION: |
|||
i82596_ioport_writew(&d->state, PORT_CA, val); |
|||
break; |
|||
case PA_GET_MACADDR: |
|||
/*
|
|||
* Provided for SeaBIOS only. Write MAC of Network card to addr @val. |
|||
* Needed for the PDC_LAN_STATION_ID_READ PDC call. |
|||
*/ |
|||
address_space_rw(&address_space_memory, val, |
|||
MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a, ETH_ALEN, 1); |
|||
break; |
|||
} |
|||
} |
|||
|
|||
static uint64_t lasi_82596_mem_read(void *opaque, hwaddr addr, |
|||
unsigned size) |
|||
{ |
|||
SysBusI82596State *d = opaque; |
|||
uint32_t val; |
|||
|
|||
if (addr == PA_GET_MACADDR) { |
|||
val = 0xBEEFBABE; |
|||
} else { |
|||
val = i82596_ioport_readw(&d->state, addr); |
|||
} |
|||
trace_lasi_82596_mem_readw(addr, val); |
|||
return val; |
|||
} |
|||
|
|||
static const MemoryRegionOps lasi_82596_mem_ops = { |
|||
.read = lasi_82596_mem_read, |
|||
.write = lasi_82596_mem_write, |
|||
.endianness = DEVICE_BIG_ENDIAN, |
|||
.valid = { |
|||
.min_access_size = 4, |
|||
.max_access_size = 4, |
|||
}, |
|||
}; |
|||
|
|||
static NetClientInfo net_lasi_82596_info = { |
|||
.type = NET_CLIENT_DRIVER_NIC, |
|||
.size = sizeof(NICState), |
|||
.can_receive = i82596_can_receive, |
|||
.receive = i82596_receive, |
|||
.link_status_changed = i82596_set_link_status, |
|||
}; |
|||
|
|||
static const VMStateDescription vmstate_lasi_82596 = { |
|||
.name = "i82596", |
|||
.version_id = 1, |
|||
.minimum_version_id = 1, |
|||
.fields = (VMStateField[]) { |
|||
VMSTATE_STRUCT(state, SysBusI82596State, 0, vmstate_i82596, |
|||
I82596State), |
|||
VMSTATE_END_OF_LIST() |
|||
} |
|||
}; |
|||
|
|||
static void lasi_82596_realize(DeviceState *dev, Error **errp) |
|||
{ |
|||
SysBusI82596State *d = SYSBUS_I82596(dev); |
|||
I82596State *s = &d->state; |
|||
|
|||
memory_region_init_io(&s->mmio, OBJECT(d), &lasi_82596_mem_ops, d, |
|||
"lasi_82596-mmio", PA_GET_MACADDR + 4); |
|||
|
|||
i82596_common_init(dev, s, &net_lasi_82596_info); |
|||
} |
|||
|
|||
SysBusI82596State *lasi_82596_init(MemoryRegion *addr_space, |
|||
hwaddr hpa, qemu_irq lan_irq) |
|||
{ |
|||
DeviceState *dev; |
|||
SysBusI82596State *s; |
|||
static const MACAddr HP_MAC = { |
|||
.a = { 0x08, 0x00, 0x09, 0xef, 0x34, 0xf6 } }; |
|||
|
|||
qemu_check_nic_model(&nd_table[0], TYPE_LASI_82596); |
|||
dev = qdev_create(NULL, TYPE_LASI_82596); |
|||
s = SYSBUS_I82596(dev); |
|||
s->state.irq = lan_irq; |
|||
qdev_set_nic_properties(dev, &nd_table[0]); |
|||
qdev_init_nofail(dev); |
|||
s->state.conf.macaddr = HP_MAC; /* set HP MAC prefix */ |
|||
|
|||
/* LASI 82596 ports in main memory. */ |
|||
memory_region_add_subregion(addr_space, hpa, &s->state.mmio); |
|||
return s; |
|||
} |
|||
|
|||
static void lasi_82596_reset(DeviceState *dev) |
|||
{ |
|||
SysBusI82596State *d = SYSBUS_I82596(dev); |
|||
|
|||
i82596_h_reset(&d->state); |
|||
} |
|||
|
|||
static void lasi_82596_instance_init(Object *obj) |
|||
{ |
|||
SysBusI82596State *d = SYSBUS_I82596(obj); |
|||
I82596State *s = &d->state; |
|||
|
|||
device_add_bootindex_property(obj, &s->conf.bootindex, |
|||
"bootindex", "/ethernet-phy@0", |
|||
DEVICE(obj), NULL); |
|||
} |
|||
|
|||
static Property lasi_82596_properties[] = { |
|||
DEFINE_NIC_PROPERTIES(SysBusI82596State, state.conf), |
|||
DEFINE_PROP_END_OF_LIST(), |
|||
}; |
|||
|
|||
static void lasi_82596_class_init(ObjectClass *klass, void *data) |
|||
{ |
|||
DeviceClass *dc = DEVICE_CLASS(klass); |
|||
|
|||
dc->realize = lasi_82596_realize; |
|||
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
|||
dc->fw_name = "ethernet"; |
|||
dc->reset = lasi_82596_reset; |
|||
dc->vmsd = &vmstate_lasi_82596; |
|||
dc->user_creatable = false; |
|||
device_class_set_props(dc, lasi_82596_properties); |
|||
} |
|||
|
|||
static const TypeInfo lasi_82596_info = { |
|||
.name = TYPE_LASI_82596, |
|||
.parent = TYPE_SYS_BUS_DEVICE, |
|||
.instance_size = sizeof(SysBusI82596State), |
|||
.class_init = lasi_82596_class_init, |
|||
.instance_init = lasi_82596_instance_init, |
|||
}; |
|||
|
|||
static void lasi_82596_register_types(void) |
|||
{ |
|||
type_register_static(&lasi_82596_info); |
|||
} |
|||
|
|||
type_init(lasi_82596_register_types) |
|||
@ -0,0 +1,16 @@ |
|||
/*
|
|||
* QEMU LASI PS/2 emulation |
|||
* |
|||
* Copyright (c) 2019 Sven Schnelle |
|||
* |
|||
*/ |
|||
#ifndef HW_INPUT_LASIPS2_H |
|||
#define HW_INPUT_LASIPS2_H |
|||
|
|||
#include "exec/hwaddr.h" |
|||
|
|||
#define TYPE_LASIPS2 "lasips2" |
|||
|
|||
void lasips2_init(MemoryRegion *address_space, hwaddr base, qemu_irq irq); |
|||
|
|||
#endif /* HW_INPUT_LASIPS2_H */ |
|||
@ -0,0 +1,29 @@ |
|||
/*
|
|||
* QEMU LASI i82596 device emulation |
|||
* |
|||
* Copyright (c) 201 Helge Deller <deller@gmx.de> |
|||
* |
|||
*/ |
|||
|
|||
#ifndef LASI_82596_H |
|||
#define LASI_82596_H |
|||
|
|||
#include "net/net.h" |
|||
#include "hw/net/i82596.h" |
|||
|
|||
#define TYPE_LASI_82596 "lasi_82596" |
|||
#define SYSBUS_I82596(obj) \ |
|||
OBJECT_CHECK(SysBusI82596State, (obj), TYPE_LASI_82596) |
|||
|
|||
typedef struct { |
|||
SysBusDevice parent_obj; |
|||
|
|||
I82596State state; |
|||
uint16_t last_val; |
|||
int val_index:1; |
|||
} SysBusI82596State; |
|||
|
|||
SysBusI82596State *lasi_82596_init(MemoryRegion *addr_space, |
|||
hwaddr hpa, qemu_irq irq); |
|||
|
|||
#endif |
|||
Binary file not shown.
@ -1 +1 @@ |
|||
Subproject commit 0f4fe84658165e96ce35870fd19fc634e182e77b |
|||
Subproject commit 1630ac7d65c4a09218cc677f1fa56cd5b3140447 |
|||
Loading…
Reference in new issue