@ -297,7 +297,7 @@ struct iommu_ioas_unmap {
* ioctl ( IOMMU_OPTION_HUGE_PAGES )
* @ IOMMU_OPTION_RLIMIT_MODE :
* Change how RLIMIT_MEMLOCK accounting works . The caller must have privilege
* to invoke this . Value 0 ( default ) is user based accouting , 1 uses process
* to invoke this . Value 0 ( default ) is user based accoun ting , 1 uses process
* based accounting . Global option , object_id must be 0
* @ IOMMU_OPTION_HUGE_PAGES :
* Value 1 ( default ) allows contiguous pages to be combined when generating
@ -390,7 +390,7 @@ struct iommu_vfio_ioas {
* @ IOMMU_HWPT_ALLOC_PASID : Requests a domain that can be used with PASID . The
* domain can be attached to any PASID on the device .
* Any domain attached to the non - PASID part of the
* device must also be flaged , otherwise attaching a
* device must also be flagg ed , otherwise attaching a
* PASID will blocked .
* If IOMMU does not support PASID it will return
* error ( - EOPNOTSUPP ) .
@ -558,16 +558,25 @@ struct iommu_hw_info_vtd {
* For the details of @ idr , @ iidr and @ aidr , please refer to the chapters
* from 6.3 .1 to 6.3 .6 in the SMMUv3 Spec .
*
* User space should read the underlying ARM SMMUv3 hardware information for
* the list of supported features .
* This reports the raw HW capability , and not all bits are meaningful to be
* read by userspace . Only the following fields should be used :
*
* Note that these values reflect the raw HW capability , without any insight if
* any required kernel driver support is present . Bits may be set indicating the
* HW has functionality that is lacking kernel software support , such as BTM . If
* a VMM is using this information to construct emulated copies of these
* registers it should only forward bits that it knows it can support .
* idr [ 0 ] : ST_LEVEL , TERM_MODEL , STALL_MODEL , TTENDIAN , CD2L , ASID16 , TTF
* idr [ 1 ] : SIDSIZE , SSIDSIZE
* idr [ 3 ] : BBML , RIL
* idr [ 5 ] : VAX , GRAN64K , GRAN16K , GRAN4K
*
* In future , presence of required kernel support will be indicated in flags .
* - S1P should be assumed to be true if a NESTED HWPT can be created
* - VFIO / iommufd only support platforms with COHACC , it should be assumed to be
* true .
* - ATS is a per - device property . If the VMM describes any devices as ATS
* capable in ACPI / DT it should set the corresponding idr .
*
* This list may expand in future ( eg E0PD , AIE , PBHA , D128 , DS etc ) . It is
* important that VMMs do not read bits outside the list to allow for
* compatibility with future kernels . Several features in the SMMUv3
* architecture are not currently supported by the kernel for nesting : HTTU ,
* BTM , MPAM and others .
*/
struct iommu_hw_info_arm_smmuv3 {
__u32 flags ;
@ -766,7 +775,7 @@ struct iommu_hwpt_vtd_s1_invalidate {
} ;
/**
* struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cah ce invalidation
* struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cach e invalidation
* ( IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 )
* @ cmd : 128 - bit cache invalidation command that runs in SMMU CMDQ .
* Must be little - endian .
@ -859,6 +868,7 @@ enum iommu_hwpt_pgfault_perm {
* @ pasid : Process Address Space ID
* @ grpid : Page Request Group Index
* @ perm : Combination of enum iommu_hwpt_pgfault_perm
* @ __reserved : Must be 0.
* @ addr : Fault address
* @ length : a hint of how much data the requestor is expecting to fetch . For
* example , if the PRI initiator knows it is going to do a 10 MB
@ -874,7 +884,8 @@ struct iommu_hwpt_pgfault {
__u32 pasid ;
__u32 grpid ;
__u32 perm ;
__u64 addr ;
__u32 __reserved ;
__aligned_u64 addr ;
__u32 length ;
__u32 cookie ;
} ;