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@ -688,13 +688,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) |
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t0 = *tb_ptr++; |
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t1 = tci_read_ri32(&tb_ptr); |
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t2 = tci_read_ri32(&tb_ptr); |
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tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2))); |
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tci_write_reg32(t0, rol32(t1, t2)); |
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break; |
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case INDEX_op_rotr_i32: |
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t0 = *tb_ptr++; |
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t1 = tci_read_ri32(&tb_ptr); |
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t2 = tci_read_ri32(&tb_ptr); |
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tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2))); |
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tci_write_reg32(t0, ror32(t1, t2)); |
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break; |
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#endif |
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#if TCG_TARGET_HAS_deposit_i32 |
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@ -955,13 +955,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) |
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t0 = *tb_ptr++; |
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t1 = tci_read_ri64(&tb_ptr); |
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t2 = tci_read_ri64(&tb_ptr); |
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tci_write_reg64(t0, (t1 << t2) | (t1 >> (64 - t2))); |
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tci_write_reg64(t0, rol64(t1, t2)); |
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break; |
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case INDEX_op_rotr_i64: |
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t0 = *tb_ptr++; |
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t1 = tci_read_ri64(&tb_ptr); |
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t2 = tci_read_ri64(&tb_ptr); |
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tci_write_reg64(t0, (t1 >> t2) | (t1 << (64 - t2))); |
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tci_write_reg64(t0, ror64(t1, t2)); |
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break; |
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#endif |
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#if TCG_TARGET_HAS_deposit_i64 |
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