diff --git a/MAINTAINERS b/MAINTAINERS
index 65ac60b86b..29f88d48f3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -302,12 +302,12 @@ F: tests/tcg/mips/
 OpenRISC TCG CPUs
 M: Stafford Horne <shorne@gmail.com>
 S: Odd Fixes
-F: docs/system/openrisc/cpu-features.rst
-F: target/openrisc/
-F: hw/openrisc/
-F: include/hw/openrisc/
+F: docs/system/or1k/cpu-features.rst
+F: target/or1k/
+F: hw/or1k/
+F: include/hw/or1k/
 F: tests/functional/or1k/meson.build
-F: tests/tcg/openrisc/
+F: tests/tcg/or1k/
 
 PowerPC TCG CPUs
 M: Nicholas Piggin <npiggin@gmail.com>
@@ -1493,9 +1493,9 @@ OpenRISC Machines
 or1k-sim
 M: Jia Liu <proljc@gmail.com>
 S: Maintained
-F: docs/system/openrisc/or1k-sim.rst
+F: docs/system/or1k/or1k-sim.rst
 F: hw/intc/ompic.c
-F: hw/openrisc/openrisc_sim.c
+F: hw/or1k/or1k-sim.c
 F: tests/functional/or1k/test_sim.py
 
 PowerPC Machines
diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak
index e9d89e8ab4..19ef4a6690 100644
--- a/configs/targets/i386-softmmu.mak
+++ b/configs/targets/i386-softmmu.mak
@@ -3,3 +3,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y
 TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
 TARGET_XML_FILES= gdb-xml/i386-32bit.xml
 TARGET_LONG_BITS=32
+TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/configs/targets/or1k-linux-user.mak b/configs/targets/or1k-linux-user.mak
index 97d7cb1046..0ee3a05884 100644
--- a/configs/targets/or1k-linux-user.mak
+++ b/configs/targets/or1k-linux-user.mak
@@ -1,4 +1,4 @@
-TARGET_ARCH=openrisc
+TARGET_ARCH=or1k
 TARGET_BIG_ENDIAN=y
 TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat
 TARGET_SYSTBL=syscall.tbl
diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak
index c53408a2bf..204283d604 100644
--- a/configs/targets/or1k-softmmu.mak
+++ b/configs/targets/or1k-softmmu.mak
@@ -1,4 +1,4 @@
-TARGET_ARCH=openrisc
+TARGET_ARCH=or1k
 TARGET_BIG_ENDIAN=y
 # needed by boot.c and all boards
 TARGET_NEED_FDT=y
diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak
index 4ff4b7287d..d3f0716ca2 100644
--- a/configs/targets/sparc-linux-user.mak
+++ b/configs/targets/sparc-linux-user.mak
@@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,32
 TARGET_SYSTBL=syscall.tbl
 TARGET_BIG_ENDIAN=y
 TARGET_LONG_BITS=32
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 57801faf1f..c4c38946d5 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,3 +1,5 @@
 TARGET_ARCH=sparc
 TARGET_BIG_ENDIAN=y
 TARGET_LONG_BITS=32
+TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/sparc32plus-linux-user.mak
index 7a16934fd1..3e6c72e793 100644
--- a/configs/targets/sparc32plus-linux-user.mak
+++ b/configs/targets/sparc32plus-linux-user.mak
@@ -6,3 +6,4 @@ TARGET_SYSTBL_ABI=common,32
 TARGET_SYSTBL=syscall.tbl
 TARGET_BIG_ENDIAN=y
 TARGET_LONG_BITS=64
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak
index 7c2ecb7be0..3bbd849521 100644
--- a/configs/targets/sparc64-linux-user.mak
+++ b/configs/targets/sparc64-linux-user.mak
@@ -6,3 +6,4 @@ TARGET_SYSTBL=syscall.tbl
 TARGET_BIG_ENDIAN=y
 TARGET_XML_FILES=gdb-xml/sparc64-core.xml
 TARGET_LONG_BITS=64
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index 8ee6d05768..8a0290c209 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -4,3 +4,4 @@ TARGET_BIG_ENDIAN=y
 TARGET_XML_FILES=gdb-xml/sparc64-core.xml
 TARGET_LONG_BITS=64
 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak
index 5180560d4d..151862158c 100644
--- a/configs/targets/x86_64-softmmu.mak
+++ b/configs/targets/x86_64-softmmu.mak
@@ -4,3 +4,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y
 TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
 TARGET_XML_FILES= gdb-xml/i386-64bit.xml gdb-xml/i386-64bit-apx.xml
 TARGET_LONG_BITS=64
+TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/or1k/cpu-features.rst
similarity index 100%
rename from docs/system/openrisc/cpu-features.rst
rename to docs/system/or1k/cpu-features.rst
diff --git a/docs/system/openrisc/emulation.rst b/docs/system/or1k/emulation.rst
similarity index 100%
rename from docs/system/openrisc/emulation.rst
rename to docs/system/or1k/emulation.rst
diff --git a/docs/system/openrisc/or1k-sim.rst b/docs/system/or1k/or1k-sim.rst
similarity index 100%
rename from docs/system/openrisc/or1k-sim.rst
rename to docs/system/or1k/or1k-sim.rst
diff --git a/docs/system/openrisc/virt.rst b/docs/system/or1k/virt.rst
similarity index 100%
rename from docs/system/openrisc/virt.rst
rename to docs/system/or1k/virt.rst
diff --git a/docs/system/target-openrisc.rst b/docs/system/target-or1k.rst
similarity index 96%
rename from docs/system/target-openrisc.rst
rename to docs/system/target-or1k.rst
index 22cb2217a6..b1ee2a34a2 100644
--- a/docs/system/target-openrisc.rst
+++ b/docs/system/target-or1k.rst
@@ -55,17 +55,17 @@ Board-specific documentation
 .. toctree::
    :maxdepth: 1
 
-   openrisc/or1k-sim
-   openrisc/virt
+   or1k/or1k-sim
+   or1k/virt
 
 Emulated CPU architecture support
 =================================
 
 .. toctree::
-   openrisc/emulation
+   or1k/emulation
 
 OpenRISC CPU features
 =====================
 
 .. toctree::
-   openrisc/cpu-features
+   or1k/cpu-features
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 38e2418801..5b12858b21 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targets.rst
@@ -21,8 +21,8 @@ Contents:
    target-loongarch
    target-m68k
    target-mips
+   target-or1k
    target-ppc
-   target-openrisc
    target-riscv
    target-rx
    target-s390x
diff --git a/hw/Kconfig b/hw/Kconfig
index 9e6c789ae7..f8f92b5d03 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -58,7 +58,7 @@ source loongarch/Kconfig
 source m68k/Kconfig
 source microblaze/Kconfig
 source mips/Kconfig
-source openrisc/Kconfig
+source or1k/Kconfig
 source ppc/Kconfig
 source riscv/Kconfig
 source rx/Kconfig
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index dd8c77f818..8766ed00b9 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -1108,7 +1108,7 @@ static const MemoryRegionOps apic_io_ops = {
     .impl.max_access_size = 4,
     .valid.min_access_size = 1,
     .valid.max_access_size = 4,
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void apic_realize(DeviceState *dev, Error **errp)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 98de6ca810..1b3f1e824a 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -141,7 +141,8 @@ static void ioapic_service(IOAPICCommonState *s)
                  * the IOAPIC message into a MSI one, and its
                  * address space will decide whether we need a
                  * translation. */
-                stl_le_phys(ioapic_as, info.addr, info.data);
+                address_space_stl_le(ioapic_as, info.addr, info.data,
+                                     MEMTXATTRS_UNSPECIFIED, NULL);
             }
         }
     }
@@ -429,7 +430,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 static const MemoryRegionOps ioapic_io_ops = {
     .read = ioapic_mem_read,
     .write = ioapic_mem_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void ioapic_machine_done_notify(Notifier *notifier, void *data)
diff --git a/hw/meson.build b/hw/meson.build
index 1022bdb806..66e46b8090 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -9,7 +9,7 @@ subdir('loongarch')
 subdir('m68k')
 subdir('microblaze')
 subdir('mips')
-subdir('openrisc')
+subdir('or1k')
 subdir('ppc')
 subdir('remote')
 subdir('riscv')
diff --git a/hw/openrisc/Kconfig b/hw/or1k/Kconfig
similarity index 89%
rename from hw/openrisc/Kconfig
rename to hw/or1k/Kconfig
index 0702f622a5..b5c2e5655b 100644
--- a/hw/openrisc/Kconfig
+++ b/hw/or1k/Kconfig
@@ -1,7 +1,7 @@
 config OR1K_SIM
     bool
     default y
-    depends on OPENRISC
+    depends on OR1K
     select DEVICE_TREE
     select SERIAL_MM
     select OPENCORES_ETH
@@ -11,7 +11,7 @@ config OR1K_SIM
 config OR1K_VIRT
     bool
     default y
-    depends on OPENRISC
+    depends on OR1K
     imply PCI_DEVICES
     imply VIRTIO_VGA
     imply TEST_DEVICES
diff --git a/hw/openrisc/boot.c b/hw/or1k/boot.c
similarity index 99%
rename from hw/openrisc/boot.c
rename to hw/or1k/boot.c
index 6256babc42..c18f4a6a9f 100644
--- a/hw/openrisc/boot.c
+++ b/hw/or1k/boot.c
@@ -12,7 +12,7 @@
 #include "exec/target_page.h"
 #include "elf.h"
 #include "hw/core/loader.h"
-#include "hw/openrisc/boot.h"
+#include "hw/or1k/boot.h"
 #include "system/device_tree.h"
 #include "system/qtest.h"
 #include "system/reset.h"
diff --git a/hw/openrisc/cputimer.c b/hw/or1k/cputimer.c
similarity index 100%
rename from hw/openrisc/cputimer.c
rename to hw/or1k/cputimer.c
diff --git a/hw/openrisc/meson.build b/hw/or1k/meson.build
similarity index 60%
rename from hw/openrisc/meson.build
rename to hw/or1k/meson.build
index 82f1f0ef1c..a5c23f4f5a 100644
--- a/hw/openrisc/meson.build
+++ b/hw/or1k/meson.build
@@ -1,7 +1,7 @@
 openrisc_ss = ss.source_set()
 openrisc_ss.add(files('cputimer.c'))
 openrisc_ss.add(files('boot.c'))
-openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c'))
+openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('or1k-sim.c'))
 openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: files('virt.c'))
 
-hw_arch += {'openrisc': openrisc_ss}
+hw_arch += {'or1k': openrisc_ss}
diff --git a/hw/openrisc/openrisc_sim.c b/hw/or1k/or1k-sim.c
similarity index 99%
rename from hw/openrisc/openrisc_sim.c
rename to hw/or1k/or1k-sim.c
index 603d8ca0d9..f1b1f63274 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/or1k/or1k-sim.c
@@ -26,7 +26,7 @@
 #include "hw/core/boards.h"
 #include "hw/char/serial-mm.h"
 #include "net/net.h"
-#include "hw/openrisc/boot.h"
+#include "hw/or1k/boot.h"
 #include "hw/core/qdev-properties.h"
 #include "system/address-spaces.h"
 #include "system/device_tree.h"
diff --git a/hw/openrisc/virt.c b/hw/or1k/virt.c
similarity index 99%
rename from hw/openrisc/virt.c
rename to hw/or1k/virt.c
index 54ce96666e..39f54058ab 100644
--- a/hw/openrisc/virt.c
+++ b/hw/or1k/virt.c
@@ -16,7 +16,7 @@
 #include "hw/core/boards.h"
 #include "hw/char/serial-mm.h"
 #include "hw/core/split-irq.h"
-#include "hw/openrisc/boot.h"
+#include "hw/or1k/boot.h"
 #include "hw/misc/sifive_test.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
diff --git a/include/exec/poison.h b/include/exec/poison.h
index a779adbb7a..21eed4c54f 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -21,7 +21,7 @@
 #pragma GCC poison TARGET_ABI_MIPSO32
 #pragma GCC poison TARGET_MIPS64
 #pragma GCC poison TARGET_ABI_MIPSN64
-#pragma GCC poison TARGET_OPENRISC
+#pragma GCC poison TARGET_OR1K
 #pragma GCC poison TARGET_PPC
 #pragma GCC poison TARGET_PPC64
 #pragma GCC poison TARGET_ABI32
diff --git a/include/hw/openrisc/boot.h b/include/hw/or1k/boot.h
similarity index 93%
rename from include/hw/openrisc/boot.h
rename to include/hw/or1k/boot.h
index 3c481bdea6..2e6131580c 100644
--- a/include/hw/openrisc/boot.h
+++ b/include/hw/or1k/boot.h
@@ -16,8 +16,8 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef OPENRISC_BOOT_H
-#define OPENRISC_BOOT_H
+#ifndef OR1K_BOOT_H
+#define OR1K_BOOT_H
 
 #include "exec/cpu-defs.h"
 #include "hw/core/boards.h"
@@ -32,4 +32,4 @@ hwaddr openrisc_load_initrd(void *fdt, const char *filename,
 uint32_t openrisc_load_fdt(MachineState *ms, void *fdt, hwaddr load_start,
                            uint64_t mem_size);
 
-#endif /* OPENRISC_BOOT_H */
+#endif /* OR1K_BOOT_H */
diff --git a/include/system/arch_init.h b/include/system/arch_init.h
index 51e24c3091..f2f909d540 100644
--- a/include/system/arch_init.h
+++ b/include/system/arch_init.h
@@ -15,7 +15,7 @@ enum {
     QEMU_ARCH_SH4 = (1 << 10),
     QEMU_ARCH_SPARC = (1 << 11),
     QEMU_ARCH_XTENSA = (1 << 12),
-    QEMU_ARCH_OPENRISC = (1 << 13),
+    QEMU_ARCH_OR1K = (1 << 13),
     QEMU_ARCH_TRICORE = (1 << 16),
     QEMU_ARCH_HPPA = (1 << 18),
     QEMU_ARCH_RISCV = (1 << 19),
diff --git a/include/user/abitypes.h b/include/user/abitypes.h
index be7a876523..534a29bc12 100644
--- a/include/user/abitypes.h
+++ b/include/user/abitypes.h
@@ -22,7 +22,7 @@
 
 #if (defined(TARGET_I386) && !defined(TARGET_X86_64)) \
     || defined(TARGET_SH4) \
-    || defined(TARGET_OPENRISC) \
+    || defined(TARGET_OR1K) \
     || defined(TARGET_MICROBLAZE)
 #define ABI_LLONG_ALIGNMENT 4
 #endif
diff --git a/linux-user/meson.build b/linux-user/meson.build
index efca843369..332847a621 100644
--- a/linux-user/meson.build
+++ b/linux-user/meson.build
@@ -50,7 +50,7 @@ subdir('m68k')
 subdir('microblaze')
 subdir('mips64')
 subdir('mips')
-subdir('openrisc')
+subdir('or1k')
 subdir('ppc')
 subdir('riscv')
 subdir('s390x')
diff --git a/linux-user/openrisc/meson.build b/linux-user/openrisc/meson.build
deleted file mode 100644
index 273e7a0c38..0000000000
--- a/linux-user/openrisc/meson.build
+++ /dev/null
@@ -1,5 +0,0 @@
-syscall_nr_generators += {
-  'openrisc': generator(sh,
-                      arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],
-                      output: '@BASENAME@_nr.h')
-}
diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/or1k/cpu_loop.c
similarity index 100%
rename from linux-user/openrisc/cpu_loop.c
rename to linux-user/or1k/cpu_loop.c
diff --git a/linux-user/openrisc/elfload.c b/linux-user/or1k/elfload.c
similarity index 100%
rename from linux-user/openrisc/elfload.c
rename to linux-user/or1k/elfload.c
diff --git a/linux-user/or1k/meson.build b/linux-user/or1k/meson.build
new file mode 100644
index 0000000000..bb7c2ee6ba
--- /dev/null
+++ b/linux-user/or1k/meson.build
@@ -0,0 +1,5 @@
+syscall_nr_generators += {
+  'or1k': generator(sh,
+                    arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],
+                    output: '@BASENAME@_nr.h')
+}
diff --git a/linux-user/openrisc/signal.c b/linux-user/or1k/signal.c
similarity index 100%
rename from linux-user/openrisc/signal.c
rename to linux-user/or1k/signal.c
diff --git a/linux-user/openrisc/sockbits.h b/linux-user/or1k/sockbits.h
similarity index 100%
rename from linux-user/openrisc/sockbits.h
rename to linux-user/or1k/sockbits.h
diff --git a/linux-user/openrisc/syscall.tbl b/linux-user/or1k/syscall.tbl
similarity index 100%
rename from linux-user/openrisc/syscall.tbl
rename to linux-user/or1k/syscall.tbl
diff --git a/linux-user/openrisc/syscallhdr.sh b/linux-user/or1k/syscallhdr.sh
similarity index 100%
rename from linux-user/openrisc/syscallhdr.sh
rename to linux-user/or1k/syscallhdr.sh
diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/or1k/target_cpu.h
similarity index 100%
rename from linux-user/openrisc/target_cpu.h
rename to linux-user/or1k/target_cpu.h
diff --git a/linux-user/openrisc/target_elf.h b/linux-user/or1k/target_elf.h
similarity index 100%
rename from linux-user/openrisc/target_elf.h
rename to linux-user/or1k/target_elf.h
diff --git a/linux-user/openrisc/target_errno_defs.h b/linux-user/or1k/target_errno_defs.h
similarity index 100%
rename from linux-user/openrisc/target_errno_defs.h
rename to linux-user/or1k/target_errno_defs.h
diff --git a/linux-user/openrisc/target_fcntl.h b/linux-user/or1k/target_fcntl.h
similarity index 100%
rename from linux-user/openrisc/target_fcntl.h
rename to linux-user/or1k/target_fcntl.h
diff --git a/linux-user/openrisc/target_mman.h b/linux-user/or1k/target_mman.h
similarity index 100%
rename from linux-user/openrisc/target_mman.h
rename to linux-user/or1k/target_mman.h
diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/or1k/target_prctl.h
similarity index 100%
rename from linux-user/openrisc/target_prctl.h
rename to linux-user/or1k/target_prctl.h
diff --git a/linux-user/openrisc/target_proc.h b/linux-user/or1k/target_proc.h
similarity index 100%
rename from linux-user/openrisc/target_proc.h
rename to linux-user/or1k/target_proc.h
diff --git a/linux-user/openrisc/target_ptrace.h b/linux-user/or1k/target_ptrace.h
similarity index 100%
rename from linux-user/openrisc/target_ptrace.h
rename to linux-user/or1k/target_ptrace.h
diff --git a/linux-user/openrisc/target_resource.h b/linux-user/or1k/target_resource.h
similarity index 100%
rename from linux-user/openrisc/target_resource.h
rename to linux-user/or1k/target_resource.h
diff --git a/linux-user/openrisc/target_signal.h b/linux-user/or1k/target_signal.h
similarity index 100%
rename from linux-user/openrisc/target_signal.h
rename to linux-user/or1k/target_signal.h
diff --git a/linux-user/openrisc/target_structs.h b/linux-user/or1k/target_structs.h
similarity index 100%
rename from linux-user/openrisc/target_structs.h
rename to linux-user/or1k/target_structs.h
diff --git a/linux-user/openrisc/target_syscall.h b/linux-user/or1k/target_syscall.h
similarity index 100%
rename from linux-user/openrisc/target_syscall.h
rename to linux-user/or1k/target_syscall.h
diff --git a/linux-user/openrisc/termbits.h b/linux-user/or1k/termbits.h
similarity index 100%
rename from linux-user/openrisc/termbits.h
rename to linux-user/or1k/termbits.h
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 6ae6e1fa13..20d862fd8b 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -72,7 +72,7 @@
 
 #if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4)  \
     || defined(TARGET_M68K)                                             \
-    || defined(TARGET_S390X) || defined(TARGET_OPENRISC)                \
+    || defined(TARGET_S390X) || defined(TARGET_OR1K)                    \
     || defined(TARGET_RISCV)                                            \
     || defined(TARGET_XTENSA) || defined(TARGET_LOONGARCH64)
 
@@ -1976,7 +1976,7 @@ struct target_stat64  {
     abi_ulong __unused5;
 };
 
-#elif defined(TARGET_OPENRISC) \
+#elif defined(TARGET_OR1K) \
     || defined(TARGET_RISCV) || defined(TARGET_HEXAGON) || defined(TARGET_LOONGARCH)
 
 /* These are the asm-generic versions of the stat and stat64 structures */
diff --git a/meson.build b/meson.build
index 8c6c0a9a32..2d114e9018 100644
--- a/meson.build
+++ b/meson.build
@@ -3263,7 +3263,7 @@ host_kconfig = \
   (hv_balloon ? ['CONFIG_HV_BALLOON_POSSIBLE=y'] : []) + \
   (have_rust ? ['CONFIG_HAVE_RUST=y'] : [])
 
-ignored = [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR', 'TARGET_ARCH' ]
+ignored = [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR' ]
 
 default_targets = 'CONFIG_DEFAULT_TARGETS' in config_host
 actual_target_dirs = []
@@ -3353,6 +3353,8 @@ foreach target : target_dirs
       # do nothing
     elif ignored.contains(k)
       # do nothing
+    elif k == 'TARGET_ARCH'
+      config_target_data.set(k, v.to_upper())
     elif k == 'TARGET_BASE_ARCH'
       # Note that TARGET_BASE_ARCH ends up in config-target.h but it is
       # not used to select files from sourcesets.
diff --git a/qapi/machine.json b/qapi/machine.json
index 907cb25f75..ef8575b6eb 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -28,6 +28,8 @@
 #
 # @loongarch64: since 7.1
 #
+# @hexagon: since 11.0
+#
 # .. note:: The resulting QMP strings can be appended to the
 #    "qemu-system-" prefix to produce the corresponding QEMU
 #    executable name.  This is true even for "qemu-system-x86_64".
@@ -35,7 +37,7 @@
 # Since: 3.0
 ##
 { 'enum' : 'SysEmuTarget',
-  'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'hppa', 'i386',
+  'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'hexagon', 'hppa', 'i386',
              'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
              'mips64el', 'mipsel', 'or1k', 'ppc',
              'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c
index be18902bb2..1ac6d9a857 100644
--- a/system/qdev-monitor.c
+++ b/system/qdev-monitor.c
@@ -62,7 +62,7 @@ typedef struct QDevAlias
                               QEMU_ARCH_I386 | \
                               QEMU_ARCH_LOONGARCH | \
                               QEMU_ARCH_MIPS | \
-                              QEMU_ARCH_OPENRISC | \
+                              QEMU_ARCH_OR1K | \
                               QEMU_ARCH_PPC | \
                               QEMU_ARCH_RISCV | \
                               QEMU_ARCH_SH4 | \
diff --git a/target-info-stub.c b/target-info-stub.c
index 8392d81e8f..65220cc782 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -18,7 +18,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
 
 static const TargetInfo target_info_stub = {
     .target_name = TARGET_NAME,
-    .target_arch = SYS_EMU_TARGET__MAX,
+    .target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),
     .long_bits = TARGET_LONG_BITS,
     .cpu_type = CPU_RESOLVING_TYPE,
     .machine_typename = TYPE_MACHINE,
diff --git a/target-info.c b/target-info.c
index 5a6d728252..a26532f660 100644
--- a/target-info.c
+++ b/target-info.c
@@ -24,13 +24,7 @@ unsigned target_long_bits(void)
 
 SysEmuTarget target_arch(void)
 {
-    SysEmuTarget arch = target_info()->target_arch;
-
-    if (arch == SYS_EMU_TARGET__MAX) {
-        arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1,
-                               &error_abort);
-    }
-    return arch;
+    return target_info()->target_arch;
 }
 
 const char *target_cpu_type(void)
diff --git a/target/Kconfig b/target/Kconfig
index d0c7b59d9c..3c73e3bae0 100644
--- a/target/Kconfig
+++ b/target/Kconfig
@@ -7,7 +7,7 @@ source loongarch/Kconfig
 source m68k/Kconfig
 source microblaze/Kconfig
 source mips/Kconfig
-source openrisc/Kconfig
+source or1k/Kconfig
 source ppc/Kconfig
 source riscv/Kconfig
 source rx/Kconfig
diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c
index 45df15de78..83ec95c290 100644
--- a/target/arm/arm-qmp-cmds.c
+++ b/target/arm/arm-qmp-cmds.c
@@ -43,29 +43,6 @@ static GICCapability *gic_cap_new(int version)
     return cap;
 }
 
-static inline void gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3)
-{
-#ifdef CONFIG_KVM
-    int fdarray[3];
-
-    if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL)) {
-        return;
-    }
-
-    /* Test KVM GICv2 */
-    if (kvm_device_supported(fdarray[1], KVM_DEV_TYPE_ARM_VGIC_V2)) {
-        v2->kernel = true;
-    }
-
-    /* Test KVM GICv3 */
-    if (kvm_device_supported(fdarray[1], KVM_DEV_TYPE_ARM_VGIC_V3)) {
-        v3->kernel = true;
-    }
-
-    kvm_arm_destroy_scratch_host_vcpu(fdarray);
-#endif
-}
-
 GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
 {
     GICCapabilityList *head = NULL;
@@ -74,7 +51,9 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
     v2->emulated = true;
     v3->emulated = true;
 
-    gic_cap_kvm_probe(v2, v3);
+    if (kvm_enabled()) {
+        arm_gic_cap_kvm_probe(v2, v3);
+    }
 
     QAPI_LIST_PREPEND(head, v2);
     QAPI_LIST_PREPEND(head, v3);
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index c93462c5b9..ea67deea52 100644
--- a/target/arm/kvm-stub.c
+++ b/target/arm/kvm-stub.c
@@ -124,3 +124,8 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu)
 {
     g_assert_not_reached();
 }
+
+void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3)
+{
+    g_assert_not_reached();
+}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 3e35570f15..ded582e0da 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -2580,3 +2580,24 @@ void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level)
     }
     kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
 }
+
+void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3)
+{
+    int fdarray[3];
+
+    if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL)) {
+        return;
+    }
+
+    /* Test KVM GICv2 */
+    if (kvm_device_supported(fdarray[1], KVM_DEV_TYPE_ARM_VGIC_V2)) {
+        v2->kernel = true;
+    }
+
+    /* Test KVM GICv3 */
+    if (kvm_device_supported(fdarray[1], KVM_DEV_TYPE_ARM_VGIC_V3)) {
+        v3->kernel = true;
+    }
+
+    kvm_arm_destroy_scratch_host_vcpu(fdarray);
+}
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 6a9b6374a6..cc0b374254 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -11,6 +11,7 @@
 #ifndef QEMU_KVM_ARM_H
 #define QEMU_KVM_ARM_H
 
+#include "qapi/qapi-types-misc-arm.h"
 #include "system/kvm.h"
 #include "target/arm/cpu-qom.h"
 
@@ -263,4 +264,6 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp);
 
 void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level);
 
+void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3);
+
 #endif
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 462c71148d..1a1bcde260 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -16,7 +16,7 @@ arm_common_ss.add(files(
   'mmuidx.c',
 ))
 
-arm_system_ss.add(files(
+arm_common_system_ss.add(files(
   'arm-qmp-cmds.c',
 ))
 arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'))
diff --git a/target/i386/helper.c b/target/i386/helper.c
index f9f9488eb4..c397a6fde5 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -669,7 +669,7 @@ uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
     MemTxAttrs attrs = cpu_get_mem_attrs(env);
     AddressSpace *as = cpu_addressspace(cs, attrs);
 
-    return address_space_lduw(as, addr, attrs, NULL);
+    return address_space_lduw_le(as, addr, attrs, NULL);
 }
 
 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
@@ -679,7 +679,7 @@ uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
     MemTxAttrs attrs = cpu_get_mem_attrs(env);
     AddressSpace *as = cpu_addressspace(cs, attrs);
 
-    return address_space_ldl(as, addr, attrs, NULL);
+    return address_space_ldl_le(as, addr, attrs, NULL);
 }
 
 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
@@ -689,7 +689,7 @@ uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
     MemTxAttrs attrs = cpu_get_mem_attrs(env);
     AddressSpace *as = cpu_addressspace(cs, attrs);
 
-    return address_space_ldq(as, addr, attrs, NULL);
+    return address_space_ldq_le(as, addr, attrs, NULL);
 }
 
 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
@@ -709,7 +709,7 @@ void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
     MemTxAttrs attrs = cpu_get_mem_attrs(env);
     AddressSpace *as = cpu_addressspace(cs, attrs);
 
-    address_space_stw(as, addr, val, attrs, NULL);
+    address_space_stw_le(as, addr, val, attrs, NULL);
 }
 
 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
@@ -719,7 +719,7 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
     MemTxAttrs attrs = cpu_get_mem_attrs(env);
     AddressSpace *as = cpu_addressspace(cs, attrs);
 
-    address_space_stl(as, addr, val, attrs, NULL);
+    address_space_stl_le(as, addr, val, attrs, NULL);
 }
 
 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
@@ -729,6 +729,6 @@ void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
     MemTxAttrs attrs = cpu_get_mem_attrs(env);
     AddressSpace *as = cpu_addressspace(cs, attrs);
 
-    address_space_stq(as, addr, val, attrs, NULL);
+    address_space_stq_le(as, addr, val, attrs, NULL);
 }
 #endif
diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c
index 0c32424d36..bb79d4e470 100644
--- a/target/i386/tcg/system/misc_helper.c
+++ b/target/i386/tcg/system/misc_helper.c
@@ -42,26 +42,26 @@ target_ulong helper_inb(CPUX86State *env, uint32_t port)
 
 void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
 {
-    address_space_stw(&address_space_io, port, data,
-                      cpu_get_mem_attrs(env), NULL);
+    address_space_stw_le(&address_space_io, port, data,
+                         cpu_get_mem_attrs(env), NULL);
 }
 
 target_ulong helper_inw(CPUX86State *env, uint32_t port)
 {
-    return address_space_lduw(&address_space_io, port,
-                              cpu_get_mem_attrs(env), NULL);
+    return address_space_lduw_le(&address_space_io, port,
+                                 cpu_get_mem_attrs(env), NULL);
 }
 
 void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
 {
-    address_space_stl(&address_space_io, port, data,
-                      cpu_get_mem_attrs(env), NULL);
+    address_space_stl_le(&address_space_io, port, data,
+                         cpu_get_mem_attrs(env), NULL);
 }
 
 target_ulong helper_inl(CPUX86State *env, uint32_t port)
 {
-    return address_space_ldl(&address_space_io, port,
-                             cpu_get_mem_attrs(env), NULL);
+    return address_space_ldl_le(&address_space_io, port,
+                                cpu_get_mem_attrs(env), NULL);
 }
 
 target_ulong helper_read_cr8(CPUX86State *env)
diff --git a/target/meson.build b/target/meson.build
index b29598e7c5..d891ef9ee0 100644
--- a/target/meson.build
+++ b/target/meson.build
@@ -8,7 +8,7 @@ subdir('loongarch')
 subdir('m68k')
 subdir('microblaze')
 subdir('mips')
-subdir('openrisc')
+subdir('or1k')
 subdir('ppc')
 subdir('riscv')
 subdir('rx')
diff --git a/target/openrisc/Kconfig b/target/or1k/Kconfig
similarity index 76%
rename from target/openrisc/Kconfig
rename to target/or1k/Kconfig
index cd66c2e3b6..b2693067b1 100644
--- a/target/openrisc/Kconfig
+++ b/target/or1k/Kconfig
@@ -1,3 +1,3 @@
-config OPENRISC
+config OR1K
     bool
     select DEVICE_TREE # needed by boot.c
diff --git a/target/openrisc/cpu-param.h b/target/or1k/cpu-param.h
similarity index 100%
rename from target/openrisc/cpu-param.h
rename to target/or1k/cpu-param.h
diff --git a/target/openrisc/cpu-qom.h b/target/or1k/cpu-qom.h
similarity index 100%
rename from target/openrisc/cpu-qom.h
rename to target/or1k/cpu-qom.h
diff --git a/target/openrisc/cpu.c b/target/or1k/cpu.c
similarity index 100%
rename from target/openrisc/cpu.c
rename to target/or1k/cpu.c
diff --git a/target/openrisc/cpu.h b/target/or1k/cpu.h
similarity index 100%
rename from target/openrisc/cpu.h
rename to target/or1k/cpu.h
diff --git a/target/openrisc/disas.c b/target/or1k/disas.c
similarity index 100%
rename from target/openrisc/disas.c
rename to target/or1k/disas.c
diff --git a/target/openrisc/exception.c b/target/or1k/exception.c
similarity index 100%
rename from target/openrisc/exception.c
rename to target/or1k/exception.c
diff --git a/target/openrisc/exception.h b/target/or1k/exception.h
similarity index 100%
rename from target/openrisc/exception.h
rename to target/or1k/exception.h
diff --git a/target/openrisc/exception_helper.c b/target/or1k/exception_helper.c
similarity index 100%
rename from target/openrisc/exception_helper.c
rename to target/or1k/exception_helper.c
diff --git a/target/openrisc/fpu_helper.c b/target/or1k/fpu_helper.c
similarity index 100%
rename from target/openrisc/fpu_helper.c
rename to target/or1k/fpu_helper.c
diff --git a/target/openrisc/gdbstub.c b/target/or1k/gdbstub.c
similarity index 100%
rename from target/openrisc/gdbstub.c
rename to target/or1k/gdbstub.c
diff --git a/target/openrisc/helper.h b/target/or1k/helper.h
similarity index 100%
rename from target/openrisc/helper.h
rename to target/or1k/helper.h
diff --git a/target/openrisc/insns.decode b/target/or1k/insns.decode
similarity index 100%
rename from target/openrisc/insns.decode
rename to target/or1k/insns.decode
diff --git a/target/openrisc/interrupt.c b/target/or1k/interrupt.c
similarity index 100%
rename from target/openrisc/interrupt.c
rename to target/or1k/interrupt.c
diff --git a/target/openrisc/interrupt_helper.c b/target/or1k/interrupt_helper.c
similarity index 100%
rename from target/openrisc/interrupt_helper.c
rename to target/or1k/interrupt_helper.c
diff --git a/target/openrisc/machine.c b/target/or1k/machine.c
similarity index 100%
rename from target/openrisc/machine.c
rename to target/or1k/machine.c
diff --git a/target/openrisc/meson.build b/target/or1k/meson.build
similarity index 79%
rename from target/openrisc/meson.build
rename to target/or1k/meson.build
index d51ea1ab75..cad8c1b1ae 100644
--- a/target/openrisc/meson.build
+++ b/target/or1k/meson.build
@@ -21,5 +21,5 @@ openrisc_system_ss.add(files(
   'mmu.c',
 ))
 
-target_arch += {'openrisc': openrisc_ss}
-target_common_system_arch += {'openrisc': openrisc_system_ss}
+target_arch += {'or1k': openrisc_ss}
+target_common_system_arch += {'or1k': openrisc_system_ss}
diff --git a/target/openrisc/mmu.c b/target/or1k/mmu.c
similarity index 100%
rename from target/openrisc/mmu.c
rename to target/or1k/mmu.c
diff --git a/target/openrisc/sys_helper.c b/target/or1k/sys_helper.c
similarity index 100%
rename from target/openrisc/sys_helper.c
rename to target/or1k/sys_helper.c
diff --git a/target/openrisc/translate.c b/target/or1k/translate.c
similarity index 100%
rename from target/openrisc/translate.c
rename to target/or1k/translate.c
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index a6c89ed0af..667d4a0da7 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -43,7 +43,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
 {
     S390CPU *cpu = S390_CPU(cs);
     CPUS390XState *env = &cpu->env;
-    target_ulong raddr;
+    hwaddr raddr;
     int prot;
     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
     uint64_t tec;
@@ -68,14 +68,14 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
     return raddr;
 }
 
-hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
+hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr v_addr)
 {
     hwaddr phys_addr;
-    target_ulong page;
+    vaddr page;
 
-    page = vaddr & TARGET_PAGE_MASK;
+    page = v_addr & TARGET_PAGE_MASK;
     phys_addr = cpu_get_phys_page_debug(cs, page);
-    phys_addr += (vaddr & ~TARGET_PAGE_MASK);
+    phys_addr += (v_addr & ~TARGET_PAGE_MASK);
 
     return phys_addr;
 }
diff --git a/target/s390x/kvm/pv.h b/target/s390x/kvm/pv.h
index e266fc3d54..ea4b4ec340 100644
--- a/target/s390x/kvm/pv.h
+++ b/target/s390x/kvm/pv.h
@@ -20,7 +20,6 @@ struct S390PVResponse {
     uint16_t rc;
 };
 
-#ifdef CONFIG_KVM
 bool s390_is_pv(void);
 int s390_pv_query_info(void);
 int s390_pv_vm_enable(void);
@@ -43,31 +42,5 @@ int kvm_s390_dump_init(void);
 int kvm_s390_dump_cpu(S390CPU *cpu, void *buff);
 int kvm_s390_dump_mem_state(uint64_t addr, size_t len, void *dest);
 int kvm_s390_dump_completion_data(void *buff);
-#else /* CONFIG_KVM */
-static inline bool s390_is_pv(void) { return false; }
-static inline int s390_pv_query_info(void) { return 0; }
-static inline int s390_pv_vm_enable(void) { return 0; }
-static inline void s390_pv_vm_disable(void) {}
-static inline bool s390_pv_vm_try_disable_async(S390CcwMachineState *ms) { return false; }
-static inline int s390_pv_set_sec_parms(uint64_t origin, uint64_t length,
-                                        struct S390PVResponse *pv_resp,
-                                        Error **errp) { return 0; }
-static inline int s390_pv_unpack(uint64_t addr, uint64_t size, uint64_t tweak,
-                                 struct S390PVResponse *pv_resp) { return 0; }
-static inline void s390_pv_prep_reset(void) {}
-static inline int s390_pv_verify(struct S390PVResponse *pv_resp) { return 0; }
-static inline void s390_pv_unshare(void) {}
-static inline void s390_pv_inject_reset_error(CPUState *cs,
-                                              struct S390PVResponse pv_resp) {};
-static inline uint64_t kvm_s390_pv_dmp_get_size_cpu(void) { return 0; }
-static inline uint64_t kvm_s390_pv_dmp_get_size_mem_state(void) { return 0; }
-static inline uint64_t kvm_s390_pv_dmp_get_size_completion_data(void) { return 0; }
-static inline bool kvm_s390_pv_info_basic_valid(void) { return false; }
-static inline int kvm_s390_dump_init(void) { return 0; }
-static inline int kvm_s390_dump_cpu(S390CPU *cpu, void *buff) { return 0; }
-static inline int kvm_s390_dump_mem_state(uint64_t addr, size_t len,
-                                          void *dest) { return 0; }
-static inline int kvm_s390_dump_completion_data(void *buff) { return 0; }
-#endif /* CONFIG_KVM */
 
 #endif /* HW_S390_PV_H */
diff --git a/target/s390x/kvm/stubs.c b/target/s390x/kvm/stubs.c
index 5fd63b9a7e..196127baa5 100644
--- a/target/s390x/kvm/stubs.c
+++ b/target/s390x/kvm/stubs.c
@@ -4,9 +4,177 @@
 
 #include "qemu/osdep.h"
 
-#include "kvm_s390x.h"
+#include "target/s390x/kvm/kvm_s390x.h"
+#include "target/s390x/kvm/pv.h"
+#include "target/s390x/cpu_models.h"
 
 int kvm_s390_get_protected_dump(void)
 {
     return false;
 }
+
+bool s390_is_pv(void)
+{
+    return false;
+}
+
+int s390_pv_query_info(void)
+{
+    return 0;
+}
+
+int s390_pv_vm_enable(void)
+{
+    return 0;
+}
+
+void s390_pv_vm_disable(void)
+{
+}
+
+bool s390_pv_vm_try_disable_async(S390CcwMachineState *ms)
+{
+    return false;
+}
+
+int s390_pv_set_sec_parms(uint64_t origin, uint64_t length,
+                          struct S390PVResponse *pv_resp, Error **errp)
+{
+    return 0;
+}
+
+int s390_pv_unpack(uint64_t addr, uint64_t size, uint64_t tweak,
+                   struct S390PVResponse *pv_resp)
+{
+    return 0;
+}
+
+void s390_pv_prep_reset(void)
+{
+}
+
+int s390_pv_verify(struct S390PVResponse *pv_resp)
+{
+    return 0;
+}
+
+void s390_pv_unshare(void)
+{
+}
+
+void s390_pv_inject_reset_error(CPUState *cs, struct S390PVResponse pv_resp)
+{
+}
+
+uint64_t kvm_s390_pv_dmp_get_size_cpu(void)
+{
+    return 0;
+}
+
+uint64_t kvm_s390_pv_dmp_get_size_mem_state(void)
+{
+    return 0;
+}
+
+uint64_t kvm_s390_pv_dmp_get_size_completion_data(void)
+{
+    return 0;
+}
+
+bool kvm_s390_pv_info_basic_valid(void)
+{
+    return false;
+}
+
+int kvm_s390_dump_init(void)
+{
+    return 0;
+}
+
+int kvm_s390_dump_cpu(S390CPU *cpu, void *buff)
+{
+    return 0;
+}
+
+int kvm_s390_dump_mem_state(uint64_t addr, size_t len, void *dest)
+{
+    return 0;
+}
+
+int kvm_s390_dump_completion_data(void *buff)
+{
+    return 0;
+}
+
+bool kvm_s390_apply_cpu_model(const S390CPUModel *model,  Error **errp)
+{
+    g_assert_not_reached();
+}
+
+void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
+                    int len, bool is_write)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_mem_op_pv(S390CPU *cpu, vaddr addr, void *hostbuf, int len,
+                       bool is_write)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
+{
+    g_assert_not_reached();
+}
+
+void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_get_hpage_1m(void)
+{
+    g_assert_not_reached();
+}
+
+void kvm_s390_enable_css_support(S390CPU *cpu)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
+                                    int vq, bool assign)
+{
+    g_assert_not_reached();
+}
+
+void kvm_s390_cmma_reset(void)
+{
+    g_assert_not_reached();
+}
+
+void kvm_s390_crypto_reset(void)
+{
+    g_assert_not_reached();
+}
+
+void kvm_s390_set_diag318(CPUState *cs, uint64_t diag318_info)
+{
+    g_assert_not_reached();
+}
+
+int kvm_s390_topology_set_mtcr(uint64_t attr)
+{
+    g_assert_not_reached();
+}
diff --git a/target/s390x/meson.build b/target/s390x/meson.build
index 3b34ae034c..096b7dcc42 100644
--- a/target/s390x/meson.build
+++ b/target/s390x/meson.build
@@ -20,10 +20,15 @@ s390x_ss.add(gen_features_h)
 
 s390x_system_ss = ss.source_set()
 s390x_system_ss.add(files(
+  'ioinst.c',
+))
+
+s390x_common_system_ss = ss.source_set()
+s390x_common_system_ss.add(gen_features_h)
+s390x_common_system_ss.add(files(
   'helper.c',
   'arch_dump.c',
   'diag.c',
-  'ioinst.c',
   'machine.c',
   'mmu_helper.c',
   'sigp.c',
@@ -41,4 +46,5 @@ subdir('kvm')
 
 target_arch += {'s390x': s390x_ss}
 target_system_arch += {'s390x': s390x_system_ss}
+target_common_system_arch += {'s390x': s390x_common_system_ss}
 target_user_arch += {'s390x': s390x_user_ss}
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index 026502a3e4..246573ff64 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -86,7 +86,7 @@ static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
  * Translate real address to absolute (= physical)
  * address by taking care of the prefix mapping.
  */
-target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
+hwaddr mmu_real2abs(CPUS390XState *env, hwaddr raddr)
 {
     if (raddr < 0x2000) {
         return raddr + env->psa;    /* Map the lowcore. */
@@ -96,7 +96,7 @@ target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
     return raddr;
 }
 
-bool mmu_absolute_addr_valid(target_ulong addr, bool is_write)
+bool mmu_absolute_addr_valid(hwaddr addr, bool is_write)
 {
     return address_space_access_valid(&address_space_memory,
                                       addr & TARGET_PAGE_MASK,
@@ -108,6 +108,7 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
                                     uint64_t *entry)
 {
     CPUState *cs = env_cpu(env);
+    MemTxResult ret;
 
     /*
      * According to the PoP, these table addresses are "unpredictably real
@@ -116,17 +117,13 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
      *
      * We treat them as absolute addresses and don't wrap them.
      */
-    if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
-                                    entry, sizeof(*entry)) !=
-                 MEMTX_OK)) {
-        return false;
-    }
-    *entry = be64_to_cpu(*entry);
-    return true;
+    *entry = address_space_ldq_be(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, &ret);
+
+    return ret == MEMTX_OK;
 }
 
-static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
-                              uint64_t asc, uint64_t asce, target_ulong *raddr,
+static int mmu_translate_asce(CPUS390XState *env, vaddr vaddr,
+                              uint64_t asc, uint64_t asce, hwaddr *raddr,
                               int *flags)
 {
     const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
@@ -299,7 +296,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
     return 0;
 }
 
-static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
+static void mmu_handle_skey(hwaddr addr, int rw, int *flags)
 {
     static S390SKeysClass *skeyclass;
     static S390SKeysState *ss;
@@ -384,8 +381,8 @@ static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
  *               there is an exception to raise
  * @return       0 = success, != 0, the exception to raise
  */
-int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
-                  target_ulong *raddr, int *flags, uint64_t *tec)
+int mmu_translate(CPUS390XState *env, vaddr vaddr, int rw, uint64_t asc,
+                  hwaddr *raddr, int *flags, uint64_t *tec)
 {
     uint64_t asce;
     int r;
@@ -475,7 +472,7 @@ nodat:
  * the MEMOP interface.
  */
 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
-                           target_ulong *pages, bool is_write, uint64_t *tec)
+                           hwaddr *pages, bool is_write, uint64_t *tec)
 {
     uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
     CPUS390XState *env = &cpu->env;
@@ -526,7 +523,7 @@ int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 {
     const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
     int currlen, nr_pages, i;
-    target_ulong *pages;
+    hwaddr *pages;
     uint64_t tec;
     int ret;
 
@@ -587,8 +584,8 @@ void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
  * @return       0 = success, != 0, the exception to raise
  */
-int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
-                       target_ulong *addr, int *flags, uint64_t *tec)
+int mmu_translate_real(CPUS390XState *env, hwaddr raddr, int rw,
+                       hwaddr *addr, int *flags, uint64_t *tec)
 {
     const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
 
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index a4b54dc441..40850bcdc4 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -10,6 +10,8 @@
 #ifndef S390X_INTERNAL_H
 #define S390X_INTERNAL_H
 
+#include "exec/hwaddr.h"
+#include "exec/vaddr.h"
 #include "cpu.h"
 #include "fpu/softfloat.h"
 
@@ -367,19 +369,19 @@ void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
 
 
 /* mem_helper.c */
-target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);
 void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
                         uintptr_t ra);
 
 
 /* mmu_helper.c */
-bool mmu_absolute_addr_valid(target_ulong addr, bool is_write);
+hwaddr mmu_real2abs(CPUS390XState *env, hwaddr raddr);
+bool mmu_absolute_addr_valid(hwaddr addr, bool is_write);
 /* Special access mode only valid for mmu_translate() */
 #define MMU_S390_LRA        -1
-int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
-                  target_ulong *raddr, int *flags, uint64_t *tec);
-int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
-                       target_ulong *addr, int *flags, uint64_t *tec);
+int mmu_translate(CPUS390XState *env, vaddr vaddr, int rw, uint64_t asc,
+                  hwaddr *raddr, int *flags, uint64_t *tec);
+int mmu_translate_real(CPUS390XState *env, hwaddr raddr, int rw,
+                       hwaddr *addr, int *flags, uint64_t *tec);
 
 
 /* misc_helper.c */
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index 019eb4fba1..41b0017d76 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -147,7 +147,8 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        bool probe, uintptr_t retaddr)
 {
     CPUS390XState *env = cpu_env(cs);
-    target_ulong vaddr, raddr;
+    vaddr vaddr;
+    hwaddr raddr;
     uint64_t asc, tec;
     int prot, excp;
 
diff --git a/target/s390x/tcg/meson.build b/target/s390x/tcg/meson.build
index 515cb8b473..17c9374d09 100644
--- a/target/s390x/tcg/meson.build
+++ b/target/s390x/tcg/meson.build
@@ -12,6 +12,6 @@ s390x_ss.add(when: 'CONFIG_TCG', if_true: files(
   'vec_int_helper.c',
   'vec_string_helper.c',
 ))
-s390x_system_ss.add(when: 'CONFIG_TCG', if_true: files(
+s390x_common_system_ss.add(when: 'CONFIG_TCG', if_true: files(
   'debug.c',
 ))
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 540c5a569c..203afe265b 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -217,9 +217,9 @@ void s390x_translate_init(void)
 
     for (i = 0; i < 16; i++) {
         snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
-        regs[i] = tcg_global_mem_new(tcg_env,
-                                     offsetof(CPUS390XState, regs[i]),
-                                     cpu_reg_names[i]);
+        regs[i] = tcg_global_mem_new_i64(tcg_env,
+                                         offsetof(CPUS390XState, regs[i]),
+                                         cpu_reg_names[i]);
     }
 }
 
@@ -1259,7 +1259,7 @@ static DisasJumpType op_asi(DisasContext *s, DisasOps *o)
 
     o->in1 = tcg_temp_new_i64();
     if (non_atomic) {
-        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);
     } else {
         /* Perform the atomic addition in memory. */
         tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
@@ -1270,7 +1270,7 @@ static DisasJumpType op_asi(DisasContext *s, DisasOps *o)
     tcg_gen_add_i64(o->out, o->in1, o->in2);
 
     if (non_atomic) {
-        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);
     }
     return DISAS_NEXT;
 }
@@ -1281,7 +1281,7 @@ static DisasJumpType op_asiu64(DisasContext *s, DisasOps *o)
 
     o->in1 = tcg_temp_new_i64();
     if (non_atomic) {
-        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);
     } else {
         /* Perform the atomic addition in memory. */
         tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
@@ -1293,7 +1293,7 @@ static DisasJumpType op_asiu64(DisasContext *s, DisasOps *o)
     tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);
 
     if (non_atomic) {
-        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);
     }
     return DISAS_NEXT;
 }
@@ -1374,7 +1374,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
     o->in1 = tcg_temp_new_i64();
 
     if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
-        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);
     } else {
         /* Perform the atomic operation in memory. */
         tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
@@ -1385,7 +1385,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
     tcg_gen_and_i64(o->out, o->in1, o->in2);
 
     if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
-        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);
     }
     return DISAS_NEXT;
 }
@@ -1917,8 +1917,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
         mop = ctz32(l + 1) | MO_BE;
         /* Do not update cc_src yet: loading cc_dst may cause an exception. */
         src = tcg_temp_new_i64();
-        tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop);
-        tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);
+        tcg_gen_qemu_ld_i64(src, o->addr1, get_mem_index(s), mop);
+        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), mop);
         gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, src, cc_dst);
         return DISAS_NEXT;
     default:
@@ -2747,15 +2747,15 @@ static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)
 
 static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
-                       MO_BESL | s->insn->data);
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),
+                        MO_BESL | s->insn->data);
     return DISAS_NEXT;
 }
 
 static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
-                       MO_BEUL | s->insn->data);
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),
+                        MO_BEUL | s->insn->data);
     return DISAS_NEXT;
 }
 
@@ -3087,7 +3087,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
 #ifndef CONFIG_USER_ONLY
 static DisasJumpType op_lura(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld_tl(o->out, o->in2, MMU_REAL_IDX, s->insn->data);
+    tcg_gen_qemu_ld_i64(o->out, o->in2, MMU_REAL_IDX, s->insn->data);
     return DISAS_NEXT;
 }
 #endif
@@ -3142,7 +3142,7 @@ static DisasJumpType op_mov2(DisasContext *s, DisasOps *o)
 static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
 {
     int b2 = get_field(s, b2);
-    TCGv ar1 = tcg_temp_new_i64();
+    TCGv_i64 ar1 = tcg_temp_new_i64();
     int r1 = get_field(s, r1);
 
     o->out = o->in2;
@@ -3506,7 +3506,7 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o)
     o->in1 = tcg_temp_new_i64();
 
     if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
-        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);
     } else {
         /* Perform the atomic operation in memory. */
         tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
@@ -3517,7 +3517,7 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o)
     tcg_gen_or_i64(o->out, o->in1, o->in2);
 
     if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
-        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);
     }
     return DISAS_NEXT;
 }
@@ -4334,7 +4334,7 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
 
 static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);
+    tcg_gen_qemu_st_i64(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);
 
     if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) {
         update_cc_op(s);
@@ -4367,8 +4367,8 @@ static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
 
 static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s),
-                       MO_BEUL | s->insn->data);
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s),
+                        MO_BEUL | s->insn->data);
     return DISAS_NEXT;
 }
 
@@ -4836,7 +4836,7 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o)
     o->in1 = tcg_temp_new_i64();
 
     if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
-        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);
     } else {
         /* Perform the atomic operation in memory. */
         tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
@@ -4847,7 +4847,7 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o)
     tcg_gen_xor_i64(o->out, o->in1, o->in2);
 
     if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
-        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
+        tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);
     }
     return DISAS_NEXT;
 }
@@ -5291,7 +5291,7 @@ static void wout_m1_16(DisasContext *s, DisasOps *o)
 #ifndef CONFIG_USER_ONLY
 static void wout_m1_16a(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_ALIGN);
+    tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_ALIGN);
 }
 #define SPEC_wout_m1_16a 0
 #endif
@@ -5305,7 +5305,7 @@ static void wout_m1_32(DisasContext *s, DisasOps *o)
 #ifndef CONFIG_USER_ONLY
 static void wout_m1_32a(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_ALIGN);
+    tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_ALIGN);
 }
 #define SPEC_wout_m1_32a 0
 #endif
@@ -5743,9 +5743,9 @@ static void in2_a2(DisasContext *s, DisasOps *o)
 }
 #define SPEC_in2_a2 0
 
-static TCGv gen_ri2(DisasContext *s)
+static TCGv_i64 gen_ri2(DisasContext *s)
 {
-    TCGv ri2 = NULL;
+    TCGv_i64 ri2 = NULL;
     bool is_imm;
     int imm;
 
@@ -5816,7 +5816,7 @@ static void in2_m2_32u(DisasContext *s, DisasOps *o)
 static void in2_m2_32ua(DisasContext *s, DisasOps *o)
 {
     in2_a2(s, o);
-    tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIGN);
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIGN);
 }
 #define SPEC_in2_m2_32ua 0
 #endif
@@ -5862,16 +5862,16 @@ static void in2_mri2_16u(DisasContext *s, DisasOps *o)
 static void in2_mri2_32s(DisasContext *s, DisasOps *o)
 {
     o->in2 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s),
-                       MO_BESL | MO_ALIGN);
+    tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s),
+                        MO_BESL | MO_ALIGN);
 }
 #define SPEC_in2_mri2_32s 0
 
 static void in2_mri2_32u(DisasContext *s, DisasOps *o)
 {
     o->in2 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s),
-                       MO_BEUL | MO_ALIGN);
+    tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s),
+                        MO_BEUL | MO_ALIGN);
 }
 #define SPEC_in2_mri2_32u 0
 
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 3bc6a6827a..4ec8799d1f 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1169,27 +1169,18 @@ uint64_t helper_ld_code(CPUSPARCState *env, target_ulong addr, uint32_t oi)
         break;
     case MO_16:
         ret = cpu_ldw_code_mmu(env, addr, oi, ra);
-        if ((mop & MO_BSWAP) != MO_TE) {
-            ret = bswap16(ret);
-        }
         if (mop & MO_SIGN) {
             ret = (int16_t)ret;
         }
         break;
     case MO_32:
         ret = cpu_ldl_code_mmu(env, addr, oi, ra);
-        if ((mop & MO_BSWAP) != MO_TE) {
-            ret = bswap32(ret);
-        }
         if (mop & MO_SIGN) {
             ret = (int32_t)ret;
         }
         break;
     case MO_64:
         ret = cpu_ldq_code_mmu(env, addr, oi, ra);
-        if ((mop & MO_BSWAP) != MO_TE) {
-            ret = bswap64(ret);
-        }
         break;
     default:
         g_assert_not_reached();
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 5a58239d65..a6f76a1ab7 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -190,7 +190,9 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
         if (is_dirty) {
             pde |= PG_MODIFIED_MASK;
         }
-        stl_be_phys(cs->as, pde_ptr, pde);
+        address_space_stl_be(cs->as, pde_ptr, pde,
+                             MEMTXATTRS_UNSPECIFIED, &result);
+        assert(result == MEMTX_OK);
     }
 
     /* the page can be put in the TLB */
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 1a7e5cc3d7..57b50ff8b9 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1764,7 +1764,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop)
         case ASI_FL16_SL:
         case ASI_FL16_P:
         case ASI_FL16_PL:
-            memop = MO_TEUW;
+            memop = MO_BEUW;
             type = GET_ASI_SHORT;
             break;
         }
@@ -2215,7 +2215,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
              * byte swapped.  We perform one 128-bit LE load, so must swap
              * the order of the writebacks.
              */
-            if ((mop & MO_BSWAP) == MO_TE) {
+            if ((mop & MO_BSWAP) == MO_BE) {
                 tcg_gen_extr_i128_i64(lo, hi, t);
             } else {
                 tcg_gen_extr_i128_i64(hi, lo, t);
@@ -2235,7 +2235,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
             /* Note that LE ldda acts as if each 32-bit register
                result is byte swapped.  Having just performed one
                64-bit bswap, we need now to swap the writebacks.  */
-            if ((da->memop & MO_BSWAP) == MO_TE) {
+            if ((da->memop & MO_BSWAP) == MO_BE) {
                 tcg_gen_extr_i64_tl(lo, hi, tmp);
             } else {
                 tcg_gen_extr_i64_tl(hi, lo, tmp);
@@ -2252,7 +2252,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
             gen_helper_ld_code(tmp, tcg_env, addr, tcg_constant_i32(oi));
 
             /* See above.  */
-            if ((da->memop & MO_BSWAP) == MO_TE) {
+            if ((da->memop & MO_BSWAP) == MO_BE) {
                 tcg_gen_extr_i64_tl(lo, hi, tmp);
             } else {
                 tcg_gen_extr_i64_tl(hi, lo, tmp);
@@ -2277,7 +2277,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
             gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);
 
             /* See above.  */
-            if ((da->memop & MO_BSWAP) == MO_TE) {
+            if ((da->memop & MO_BSWAP) == MO_BE) {
                 tcg_gen_extr_i64_tl(lo, hi, tmp);
             } else {
                 tcg_gen_extr_i64_tl(hi, lo, tmp);
@@ -2310,7 +2310,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
              * byte swapped.  We perform one 128-bit LE store, so must swap
              * the order of the construction.
              */
-            if ((mop & MO_BSWAP) == MO_TE) {
+            if ((mop & MO_BSWAP) == MO_BE) {
                 tcg_gen_concat_i64_i128(t, lo, hi);
             } else {
                 tcg_gen_concat_i64_i128(t, hi, lo);
@@ -2329,7 +2329,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
             /* Note that LE stda acts as if each 32-bit register result is
                byte swapped.  We will perform one 64-bit LE store, so now
                we must swap the order of the construction.  */
-            if ((da->memop & MO_BSWAP) == MO_TE) {
+            if ((da->memop & MO_BSWAP) == MO_BE) {
                 tcg_gen_concat_tl_i64(t64, lo, hi);
             } else {
                 tcg_gen_concat_tl_i64(t64, hi, lo);
@@ -2345,7 +2345,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
          * See comments for GET_ASI_COPY above.
          */
         {
-            MemOp mop = MO_TE | MO_128 | MO_ATOM_IFALIGN_PAIR;
+            MemOp mop = MO_BE | MO_128 | MO_ATOM_IFALIGN_PAIR;
             TCGv_i64 t8 = tcg_temp_new_i64();
             TCGv_i128 t16 = tcg_temp_new_i128();
             TCGv daddr = tcg_temp_new();
@@ -2368,7 +2368,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
             TCGv_i64 t64 = tcg_temp_new_i64();
 
             /* See above.  */
-            if ((da->memop & MO_BSWAP) == MO_TE) {
+            if ((da->memop & MO_BSWAP) == MO_BE) {
                 tcg_gen_concat_tl_i64(t64, lo, hi);
             } else {
                 tcg_gen_concat_tl_i64(t64, hi, lo);
@@ -4428,13 +4428,13 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
     return advance_pc(dc);
 }
 
-TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL)
+TRANS(LDUW, ALL, do_ld_gpr, a, MO_BEUL)
 TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB)
-TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW)
+TRANS(LDUH, ALL, do_ld_gpr, a, MO_BEUW)
 TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB)
-TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW)
-TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL)
-TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ)
+TRANS(LDSH, ALL, do_ld_gpr, a, MO_BESW)
+TRANS(LDSW, 64, do_ld_gpr, a, MO_BESL)
+TRANS(LDX, 64, do_ld_gpr, a, MO_BEUQ)
 
 static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
 {
@@ -4451,10 +4451,10 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
     return advance_pc(dc);
 }
 
-TRANS(STW, ALL, do_st_gpr, a, MO_TEUL)
+TRANS(STW, ALL, do_st_gpr, a, MO_BEUL)
 TRANS(STB, ALL, do_st_gpr, a, MO_UB)
-TRANS(STH, ALL, do_st_gpr, a, MO_TEUW)
-TRANS(STX, 64, do_st_gpr, a, MO_TEUQ)
+TRANS(STH, ALL, do_st_gpr, a, MO_BEUW)
+TRANS(STX, 64, do_st_gpr, a, MO_BEUQ)
 
 static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a)
 {
@@ -4468,7 +4468,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a)
     if (addr == NULL) {
         return false;
     }
-    da = resolve_asi(dc, a->asi, MO_TEUQ);
+    da = resolve_asi(dc, a->asi, MO_BEUQ);
     gen_ldda_asi(dc, &da, addr, a->rd);
     return advance_pc(dc);
 }
@@ -4485,7 +4485,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a)
     if (addr == NULL) {
         return false;
     }
-    da = resolve_asi(dc, a->asi, MO_TEUQ);
+    da = resolve_asi(dc, a->asi, MO_BEUQ);
     gen_stda_asi(dc, &da, addr, a->rd);
     return advance_pc(dc);
 }
@@ -4516,7 +4516,7 @@ static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a)
     if (addr == NULL) {
         return false;
     }
-    da = resolve_asi(dc, a->asi, MO_TEUL);
+    da = resolve_asi(dc, a->asi, MO_BEUL);
 
     dst = gen_dest_gpr(dc, a->rd);
     src = gen_load_gpr(dc, a->rd);
@@ -4544,8 +4544,8 @@ static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
     return advance_pc(dc);
 }
 
-TRANS(CASA, CASA, do_casa, a, MO_TEUL)
-TRANS(CASXA, 64, do_casa, a, MO_TEUQ)
+TRANS(CASA, CASA, do_casa, a, MO_BEUL)
+TRANS(CASXA, 64, do_casa, a, MO_BEUQ)
 
 static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
 {
@@ -4561,7 +4561,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
     if (sz == MO_128 && gen_trap_float128(dc)) {
         return true;
     }
-    da = resolve_asi(dc, a->asi, MO_TE | sz);
+    da = resolve_asi(dc, a->asi, MO_BE | sz);
     gen_ldf_asi(dc, &da, sz, addr, a->rd);
     gen_update_fprs_dirty(dc, a->rd);
     return advance_pc(dc);
@@ -4590,7 +4590,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
     if (sz == MO_128 && gen_trap_float128(dc)) {
         return true;
     }
-    da = resolve_asi(dc, a->asi, MO_TE | sz);
+    da = resolve_asi(dc, a->asi, MO_BE | sz);
     gen_stf_asi(dc, &da, sz, addr, a->rd);
     return advance_pc(dc);
 }
@@ -4629,7 +4629,7 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
     /* Store the single element from the queue. */
     TCGv_i64 fq = tcg_temp_new_i64();
     tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d));
-    tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4);
+    tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_BEUQ | MO_ALIGN_4);
 
     /* Mark the queue empty, transitioning to fp_execute state. */
     tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,
@@ -4655,7 +4655,7 @@ static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)
     }
 
     tmp = tcg_temp_new_i32();
-    tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN);
+    tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_BEUL | MO_ALIGN);
 
     tcg_gen_extract_i32(cpu_fcc[0], tmp, FSR_FCC0_SHIFT, 2);
     /* LDFSR does not change FCC[1-3]. */
@@ -4679,7 +4679,7 @@ static bool do_ldxfsr(DisasContext *dc, arg_r_r_ri *a, bool entire)
     }
 
     t64 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN);
+    tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_BEUQ | MO_ALIGN);
 
     lo = tcg_temp_new_i32();
     hi = cpu_fcc[3];
@@ -4722,8 +4722,8 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)
     return advance_pc(dc);
 }
 
-TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL)
-TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ)
+TRANS(STFSR, ALL, do_stfsr, a, MO_BEUL)
+TRANS(STXFSR, 64, do_stfsr, a, MO_BEUQ)
 
 static bool do_fc(DisasContext *dc, int rd, int32_t c)
 {
diff --git a/tests/functional/riscv64/test_boston.py b/tests/functional/riscv64/test_boston.py
index 2582df96f2..ec09544095 100755
--- a/tests/functional/riscv64/test_boston.py
+++ b/tests/functional/riscv64/test_boston.py
@@ -66,25 +66,6 @@ class RiscvBostonTest(QemuSystemTest):
         """
         self._boot_linux_test(smp_count=2)
 
-    def test_boston_boot_linux_7_cpus(self):
-        """
-        Test Linux kernel boot with 7 CPUs
-
-        7 CPUs is a special configuration that tests odd CPU count
-        handling and ensures proper core distribution across clusters.
-        """
-        self._boot_linux_test(smp_count=7)
-
-    def test_boston_boot_linux_35_cpus(self):
-        """
-        Test Linux kernel boot with 35 CPUs
-
-        35 CPUs is a special configuration that tests a non-power-of-2
-        CPU count above 32, validating proper handling of larger
-        asymmetric SMP configurations.
-        """
-        self._boot_linux_test(smp_count=35)
-
     def test_boston_boot_linux_max_cpus(self):
         """
         Test Linux kernel boot with maximum supported CPU count (64)
diff --git a/tests/tcg/openrisc/Makefile b/tests/tcg/or1k/Makefile
similarity index 100%
rename from tests/tcg/openrisc/Makefile
rename to tests/tcg/or1k/Makefile
diff --git a/tests/tcg/openrisc/test_add.c b/tests/tcg/or1k/test_add.c
similarity index 100%
rename from tests/tcg/openrisc/test_add.c
rename to tests/tcg/or1k/test_add.c
diff --git a/tests/tcg/openrisc/test_addc.c b/tests/tcg/or1k/test_addc.c
similarity index 100%
rename from tests/tcg/openrisc/test_addc.c
rename to tests/tcg/or1k/test_addc.c
diff --git a/tests/tcg/openrisc/test_addi.c b/tests/tcg/or1k/test_addi.c
similarity index 100%
rename from tests/tcg/openrisc/test_addi.c
rename to tests/tcg/or1k/test_addi.c
diff --git a/tests/tcg/openrisc/test_addic.c b/tests/tcg/or1k/test_addic.c
similarity index 100%
rename from tests/tcg/openrisc/test_addic.c
rename to tests/tcg/or1k/test_addic.c
diff --git a/tests/tcg/openrisc/test_and_or.c b/tests/tcg/or1k/test_and_or.c
similarity index 100%
rename from tests/tcg/openrisc/test_and_or.c
rename to tests/tcg/or1k/test_and_or.c
diff --git a/tests/tcg/openrisc/test_bf.c b/tests/tcg/or1k/test_bf.c
similarity index 100%
rename from tests/tcg/openrisc/test_bf.c
rename to tests/tcg/or1k/test_bf.c
diff --git a/tests/tcg/openrisc/test_bnf.c b/tests/tcg/or1k/test_bnf.c
similarity index 100%
rename from tests/tcg/openrisc/test_bnf.c
rename to tests/tcg/or1k/test_bnf.c
diff --git a/tests/tcg/openrisc/test_div.c b/tests/tcg/or1k/test_div.c
similarity index 100%
rename from tests/tcg/openrisc/test_div.c
rename to tests/tcg/or1k/test_div.c
diff --git a/tests/tcg/openrisc/test_divu.c b/tests/tcg/or1k/test_divu.c
similarity index 100%
rename from tests/tcg/openrisc/test_divu.c
rename to tests/tcg/or1k/test_divu.c
diff --git a/tests/tcg/openrisc/test_extx.c b/tests/tcg/or1k/test_extx.c
similarity index 100%
rename from tests/tcg/openrisc/test_extx.c
rename to tests/tcg/or1k/test_extx.c
diff --git a/tests/tcg/openrisc/test_fx.c b/tests/tcg/or1k/test_fx.c
similarity index 100%
rename from tests/tcg/openrisc/test_fx.c
rename to tests/tcg/or1k/test_fx.c
diff --git a/tests/tcg/openrisc/test_j.c b/tests/tcg/or1k/test_j.c
similarity index 100%
rename from tests/tcg/openrisc/test_j.c
rename to tests/tcg/or1k/test_j.c
diff --git a/tests/tcg/openrisc/test_jal.c b/tests/tcg/or1k/test_jal.c
similarity index 100%
rename from tests/tcg/openrisc/test_jal.c
rename to tests/tcg/or1k/test_jal.c
diff --git a/tests/tcg/openrisc/test_lf_add.c b/tests/tcg/or1k/test_lf_add.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_add.c
rename to tests/tcg/or1k/test_lf_add.c
diff --git a/tests/tcg/openrisc/test_lf_div.c b/tests/tcg/or1k/test_lf_div.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_div.c
rename to tests/tcg/or1k/test_lf_div.c
diff --git a/tests/tcg/openrisc/test_lf_eqs.c b/tests/tcg/or1k/test_lf_eqs.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_eqs.c
rename to tests/tcg/or1k/test_lf_eqs.c
diff --git a/tests/tcg/openrisc/test_lf_ges.c b/tests/tcg/or1k/test_lf_ges.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_ges.c
rename to tests/tcg/or1k/test_lf_ges.c
diff --git a/tests/tcg/openrisc/test_lf_gts.c b/tests/tcg/or1k/test_lf_gts.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_gts.c
rename to tests/tcg/or1k/test_lf_gts.c
diff --git a/tests/tcg/openrisc/test_lf_les.c b/tests/tcg/or1k/test_lf_les.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_les.c
rename to tests/tcg/or1k/test_lf_les.c
diff --git a/tests/tcg/openrisc/test_lf_lts.c b/tests/tcg/or1k/test_lf_lts.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_lts.c
rename to tests/tcg/or1k/test_lf_lts.c
diff --git a/tests/tcg/openrisc/test_lf_mul.c b/tests/tcg/or1k/test_lf_mul.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_mul.c
rename to tests/tcg/or1k/test_lf_mul.c
diff --git a/tests/tcg/openrisc/test_lf_nes.c b/tests/tcg/or1k/test_lf_nes.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_nes.c
rename to tests/tcg/or1k/test_lf_nes.c
diff --git a/tests/tcg/openrisc/test_lf_rem.c b/tests/tcg/or1k/test_lf_rem.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_rem.c
rename to tests/tcg/or1k/test_lf_rem.c
diff --git a/tests/tcg/openrisc/test_lf_sub.c b/tests/tcg/or1k/test_lf_sub.c
similarity index 100%
rename from tests/tcg/openrisc/test_lf_sub.c
rename to tests/tcg/or1k/test_lf_sub.c
diff --git a/tests/tcg/openrisc/test_logic.c b/tests/tcg/or1k/test_logic.c
similarity index 100%
rename from tests/tcg/openrisc/test_logic.c
rename to tests/tcg/or1k/test_logic.c
diff --git a/tests/tcg/openrisc/test_lx.c b/tests/tcg/or1k/test_lx.c
similarity index 100%
rename from tests/tcg/openrisc/test_lx.c
rename to tests/tcg/or1k/test_lx.c
diff --git a/tests/tcg/openrisc/test_movhi.c b/tests/tcg/or1k/test_movhi.c
similarity index 100%
rename from tests/tcg/openrisc/test_movhi.c
rename to tests/tcg/or1k/test_movhi.c
diff --git a/tests/tcg/openrisc/test_mul.c b/tests/tcg/or1k/test_mul.c
similarity index 100%
rename from tests/tcg/openrisc/test_mul.c
rename to tests/tcg/or1k/test_mul.c
diff --git a/tests/tcg/openrisc/test_muli.c b/tests/tcg/or1k/test_muli.c
similarity index 100%
rename from tests/tcg/openrisc/test_muli.c
rename to tests/tcg/or1k/test_muli.c
diff --git a/tests/tcg/openrisc/test_mulu.c b/tests/tcg/or1k/test_mulu.c
similarity index 100%
rename from tests/tcg/openrisc/test_mulu.c
rename to tests/tcg/or1k/test_mulu.c
diff --git a/tests/tcg/openrisc/test_sfeq.c b/tests/tcg/or1k/test_sfeq.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfeq.c
rename to tests/tcg/or1k/test_sfeq.c
diff --git a/tests/tcg/openrisc/test_sfeqi.c b/tests/tcg/or1k/test_sfeqi.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfeqi.c
rename to tests/tcg/or1k/test_sfeqi.c
diff --git a/tests/tcg/openrisc/test_sfges.c b/tests/tcg/or1k/test_sfges.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfges.c
rename to tests/tcg/or1k/test_sfges.c
diff --git a/tests/tcg/openrisc/test_sfgesi.c b/tests/tcg/or1k/test_sfgesi.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgesi.c
rename to tests/tcg/or1k/test_sfgesi.c
diff --git a/tests/tcg/openrisc/test_sfgeu.c b/tests/tcg/or1k/test_sfgeu.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgeu.c
rename to tests/tcg/or1k/test_sfgeu.c
diff --git a/tests/tcg/openrisc/test_sfgeui.c b/tests/tcg/or1k/test_sfgeui.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgeui.c
rename to tests/tcg/or1k/test_sfgeui.c
diff --git a/tests/tcg/openrisc/test_sfgts.c b/tests/tcg/or1k/test_sfgts.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgts.c
rename to tests/tcg/or1k/test_sfgts.c
diff --git a/tests/tcg/openrisc/test_sfgtsi.c b/tests/tcg/or1k/test_sfgtsi.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgtsi.c
rename to tests/tcg/or1k/test_sfgtsi.c
diff --git a/tests/tcg/openrisc/test_sfgtu.c b/tests/tcg/or1k/test_sfgtu.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgtu.c
rename to tests/tcg/or1k/test_sfgtu.c
diff --git a/tests/tcg/openrisc/test_sfgtui.c b/tests/tcg/or1k/test_sfgtui.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfgtui.c
rename to tests/tcg/or1k/test_sfgtui.c
diff --git a/tests/tcg/openrisc/test_sfles.c b/tests/tcg/or1k/test_sfles.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfles.c
rename to tests/tcg/or1k/test_sfles.c
diff --git a/tests/tcg/openrisc/test_sflesi.c b/tests/tcg/or1k/test_sflesi.c
similarity index 100%
rename from tests/tcg/openrisc/test_sflesi.c
rename to tests/tcg/or1k/test_sflesi.c
diff --git a/tests/tcg/openrisc/test_sfleu.c b/tests/tcg/or1k/test_sfleu.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfleu.c
rename to tests/tcg/or1k/test_sfleu.c
diff --git a/tests/tcg/openrisc/test_sfleui.c b/tests/tcg/or1k/test_sfleui.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfleui.c
rename to tests/tcg/or1k/test_sfleui.c
diff --git a/tests/tcg/openrisc/test_sflts.c b/tests/tcg/or1k/test_sflts.c
similarity index 100%
rename from tests/tcg/openrisc/test_sflts.c
rename to tests/tcg/or1k/test_sflts.c
diff --git a/tests/tcg/openrisc/test_sfltsi.c b/tests/tcg/or1k/test_sfltsi.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfltsi.c
rename to tests/tcg/or1k/test_sfltsi.c
diff --git a/tests/tcg/openrisc/test_sfltu.c b/tests/tcg/or1k/test_sfltu.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfltu.c
rename to tests/tcg/or1k/test_sfltu.c
diff --git a/tests/tcg/openrisc/test_sfltui.c b/tests/tcg/or1k/test_sfltui.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfltui.c
rename to tests/tcg/or1k/test_sfltui.c
diff --git a/tests/tcg/openrisc/test_sfne.c b/tests/tcg/or1k/test_sfne.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfne.c
rename to tests/tcg/or1k/test_sfne.c
diff --git a/tests/tcg/openrisc/test_sfnei.c b/tests/tcg/or1k/test_sfnei.c
similarity index 100%
rename from tests/tcg/openrisc/test_sfnei.c
rename to tests/tcg/or1k/test_sfnei.c
diff --git a/tests/tcg/openrisc/test_sub.c b/tests/tcg/or1k/test_sub.c
similarity index 100%
rename from tests/tcg/openrisc/test_sub.c
rename to tests/tcg/or1k/test_sub.c